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GET /api/patches/132488/?format=api
{ "id": 132488, "url": "http://patchwork.dpdk.org/api/patches/132488/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20231011015054.524907-2-vattunuru@marvell.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20231011015054.524907-2-vattunuru@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20231011015054.524907-2-vattunuru@marvell.com", "date": "2023-10-11T01:50:52", "name": "[1/3] net/octeon_ep: support 32B IQ descriptor size", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "2413ff2490042ea42a95525cb0d58fae22e32998", "submitter": { "id": 1277, "url": "http://patchwork.dpdk.org/api/people/1277/?format=api", "name": "Vamsi Krishna Attunuru", "email": "vattunuru@marvell.com" }, "delegate": { "id": 310, "url": "http://patchwork.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20231011015054.524907-2-vattunuru@marvell.com/mbox/", "series": [ { "id": 29803, "url": "http://patchwork.dpdk.org/api/series/29803/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=29803", "date": "2023-10-11T01:50:51", "name": "rewrite fastpath routines", "version": 1, "mbox": "http://patchwork.dpdk.org/series/29803/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/132488/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/132488/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 720C342358;\n\tWed, 11 Oct 2023 03:51:17 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 52B55402DA;\n\tWed, 11 Oct 2023 03:51:13 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id 36532400EF\n for <dev@dpdk.org>; Wed, 11 Oct 2023 03:51:11 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id\n 39AIbe4R020001 for <dev@dpdk.org>; Tue, 10 Oct 2023 18:51:10 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3tnc2as6xy-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Tue, 10 Oct 2023 18:51:10 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48;\n Tue, 10 Oct 2023 18:51:09 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend\n Transport; Tue, 10 Oct 2023 18:51:08 -0700", "from localhost.localdomain (unknown [10.28.36.156])\n by maili.marvell.com (Postfix) with ESMTP id 628365B6934;\n Tue, 10 Oct 2023 18:51:07 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=VEvjjFs5jVw++n8MJB8t7s72HGlp5/ALeYTSOQ7d2oY=;\n b=NXl45v5X1IZ99LamQbf7pp3fdMFCFSr15XReR1CJDSCbZfYQGRm2KMAmUI3gMU1XVHgP\n 6JQj2ueCF3ajfUrEtVfsUiQbhRgqi6IlCqPIfEEeQ04H5bSGyxEpb6f4NFjMGuyd5ta6\n NroerJ2oO3z+Kz+giHqO86mSMDXhcpotxTvcjfykIkIJSxP2EhzAd30re7dazfnMdeCI\n FAjcuQI4uV0efg72MhlwdzNkLIcZnEHWxv2Kf9KKLoM2Th7+9xud/VQvo2WVNGeSbUZQ\n mIQzSoF6FgfUIBBkY3Mtu5mGGgqQsqhmeQRZYpASsjjy37qnKkfhzoUxl4iYrIuKxUvv XQ==", "From": "Vamsi Attunuru <vattunuru@marvell.com>", "To": "<dev@dpdk.org>, <jerinj@marvell.com>", "CC": "<sthotton@marvell.com>", "Subject": "[PATCH 1/3] net/octeon_ep: support 32B IQ descriptor size", "Date": "Tue, 10 Oct 2023 18:50:52 -0700", "Message-ID": "<20231011015054.524907-2-vattunuru@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20231011015054.524907-1-vattunuru@marvell.com>", "References": "<20231011015054.524907-1-vattunuru@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "2eAH8QoZ_QOSVHAlPDbhDqWx54mlPY1Y", "X-Proofpoint-ORIG-GUID": "2eAH8QoZ_QOSVHAlPDbhDqWx54mlPY1Y", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.267,Aquarius:18.0.980,Hydra:6.0.619,FMLib:17.11.176.26\n definitions=2023-10-10_19,2023-10-10_01,2023-05-22_02", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Shijith Thotton <sthotton@marvell.com>\n\nUpdate input queue setup to consider descriptor size in driver conf.\nThe default instruction size for otx2 and cnxk devices has been updated\nto 32 bytes.\n\nSigned-off-by: Shijith Thotton <sthotton@marvell.com>\n---\n drivers/net/octeon_ep/cnxk_ep_vf.c | 10 +++++++++-\n drivers/net/octeon_ep/otx2_ep_vf.c | 10 +++++++++-\n drivers/net/octeon_ep/otx_ep_common.h | 4 ++++\n drivers/net/octeon_ep/otx_ep_rxtx.c | 8 +++-----\n drivers/net/octeon_ep/otx_ep_vf.c | 8 ++++++++\n 5 files changed, 33 insertions(+), 7 deletions(-)", "diff": "diff --git a/drivers/net/octeon_ep/cnxk_ep_vf.c b/drivers/net/octeon_ep/cnxk_ep_vf.c\nindex 92c2d2ca5c..7b3669fe0c 100644\n--- a/drivers/net/octeon_ep/cnxk_ep_vf.c\n+++ b/drivers/net/octeon_ep/cnxk_ep_vf.c\n@@ -106,6 +106,14 @@ cnxk_ep_vf_setup_iq_regs(struct otx_ep_device *otx_ep, uint32_t iq_no)\n \t\treturn -EIO;\n \t}\n \n+\t/* Configure input queue instruction size. */\n+\tif (otx_ep->conf->iq.instr_type == OTX_EP_32BYTE_INSTR)\n+\t\treg_val &= ~(CNXK_EP_R_IN_CTL_IS_64B);\n+\telse\n+\t\treg_val |= CNXK_EP_R_IN_CTL_IS_64B;\n+\toct_ep_write64(reg_val, otx_ep->hw_addr + CNXK_EP_R_IN_CONTROL(iq_no));\n+\tiq->desc_size = otx_ep->conf->iq.instr_type;\n+\n \t/* Write the start of the input queue's ring and its size */\n \toct_ep_write64(iq->base_addr_dma, otx_ep->hw_addr + CNXK_EP_R_IN_INSTR_BADDR(iq_no));\n \toct_ep_write64(iq->nb_desc, otx_ep->hw_addr + CNXK_EP_R_IN_INSTR_RSIZE(iq_no));\n@@ -354,7 +362,7 @@ static const struct otx_ep_config default_cnxk_ep_conf = {\n \t/* IQ attributes */\n \t.iq = {\n \t\t.max_iqs = OTX_EP_CFG_IO_QUEUES,\n-\t\t.instr_type = OTX_EP_64BYTE_INSTR,\n+\t\t.instr_type = OTX_EP_32BYTE_INSTR,\n \t\t.pending_list_size = (OTX_EP_MAX_IQ_DESCRIPTORS *\n \t\t\t\t OTX_EP_CFG_IO_QUEUES),\n \t},\ndiff --git a/drivers/net/octeon_ep/otx2_ep_vf.c b/drivers/net/octeon_ep/otx2_ep_vf.c\nindex ced3a415a5..f72b8d25d7 100644\n--- a/drivers/net/octeon_ep/otx2_ep_vf.c\n+++ b/drivers/net/octeon_ep/otx2_ep_vf.c\n@@ -256,6 +256,14 @@ otx2_vf_setup_iq_regs(struct otx_ep_device *otx_ep, uint32_t iq_no)\n \t\treturn -EIO;\n \t}\n \n+\t/* Configure input queue instruction size. */\n+\tif (otx_ep->conf->iq.instr_type == OTX_EP_32BYTE_INSTR)\n+\t\treg_val &= ~(SDP_VF_R_IN_CTL_IS_64B);\n+\telse\n+\t\treg_val |= SDP_VF_R_IN_CTL_IS_64B;\n+\toct_ep_write64(reg_val, otx_ep->hw_addr + SDP_VF_R_IN_CONTROL(iq_no));\n+\tiq->desc_size = otx_ep->conf->iq.instr_type;\n+\n \t/* Write the start of the input queue's ring and its size */\n \toct_ep_write64(iq->base_addr_dma, otx_ep->hw_addr + SDP_VF_R_IN_INSTR_BADDR(iq_no));\n \toct_ep_write64(iq->nb_desc, otx_ep->hw_addr + SDP_VF_R_IN_INSTR_RSIZE(iq_no));\n@@ -500,7 +508,7 @@ static const struct otx_ep_config default_otx2_ep_conf = {\n \t/* IQ attributes */\n \t.iq = {\n \t\t.max_iqs = OTX_EP_CFG_IO_QUEUES,\n-\t\t.instr_type = OTX_EP_64BYTE_INSTR,\n+\t\t.instr_type = OTX_EP_32BYTE_INSTR,\n \t\t.pending_list_size = (OTX_EP_MAX_IQ_DESCRIPTORS *\n \t\t\t\t OTX_EP_CFG_IO_QUEUES),\n \t},\ndiff --git a/drivers/net/octeon_ep/otx_ep_common.h b/drivers/net/octeon_ep/otx_ep_common.h\nindex c150cbe619..90e059cad0 100644\n--- a/drivers/net/octeon_ep/otx_ep_common.h\n+++ b/drivers/net/octeon_ep/otx_ep_common.h\n@@ -11,6 +11,7 @@\n \n #define OTX_EP_MAX_RINGS_PER_VF (8)\n #define OTX_EP_CFG_IO_QUEUES OTX_EP_MAX_RINGS_PER_VF\n+#define OTX_EP_32BYTE_INSTR (32)\n #define OTX_EP_64BYTE_INSTR (64)\n /*\n * Backpressure for SDP is configured on Octeon, and the minimum queue sizes\n@@ -215,6 +216,9 @@ struct otx_ep_instr_queue {\n \t/* Number of descriptors in this ring. */\n \tuint32_t nb_desc;\n \n+\t/* Size of the descriptor. */\n+\tuint8_t desc_size;\n+\n \t/* Input ring index, where the driver should write the next packet */\n \tuint32_t host_write_index;\n \ndiff --git a/drivers/net/octeon_ep/otx_ep_rxtx.c b/drivers/net/octeon_ep/otx_ep_rxtx.c\nindex b37fc8109f..5b759d759b 100644\n--- a/drivers/net/octeon_ep/otx_ep_rxtx.c\n+++ b/drivers/net/octeon_ep/otx_ep_rxtx.c\n@@ -484,7 +484,7 @@ otx_ep_ring_doorbell(struct otx_ep_device *otx_ep __rte_unused,\n static inline int\n post_iqcmd(struct otx_ep_instr_queue *iq, uint8_t *iqcmd)\n {\n-\tuint8_t *iqptr, cmdsize;\n+\tuint8_t *iqptr;\n \n \t/* This ensures that the read index does not wrap around to\n \t * the same position if queue gets full before OCTEON 9 could\n@@ -494,10 +494,8 @@ post_iqcmd(struct otx_ep_instr_queue *iq, uint8_t *iqcmd)\n \t\treturn OTX_EP_IQ_SEND_FAILED;\n \n \t/* Copy cmd into iq */\n-\tcmdsize = 64;\n-\tiqptr = iq->base_addr + (iq->host_write_index << 6);\n-\n-\trte_memcpy(iqptr, iqcmd, cmdsize);\n+\tiqptr = iq->base_addr + (iq->host_write_index * iq->desc_size);\n+\trte_memcpy(iqptr, iqcmd, iq->desc_size);\n \n \t/* Increment the host write index */\n \tiq->host_write_index =\ndiff --git a/drivers/net/octeon_ep/otx_ep_vf.c b/drivers/net/octeon_ep/otx_ep_vf.c\nindex 4f3538146b..236b7a874c 100644\n--- a/drivers/net/octeon_ep/otx_ep_vf.c\n+++ b/drivers/net/octeon_ep/otx_ep_vf.c\n@@ -120,6 +120,14 @@ otx_ep_setup_iq_regs(struct otx_ep_device *otx_ep, uint32_t iq_no)\n \t\t\treturn -EIO;\n \t}\n \n+\t/* Configure input queue instruction size. */\n+\tif (iq->desc_size == OTX_EP_32BYTE_INSTR)\n+\t\treg_val &= ~(OTX_EP_R_IN_CTL_IS_64B);\n+\telse\n+\t\treg_val |= OTX_EP_R_IN_CTL_IS_64B;\n+\toct_ep_write64(reg_val, otx_ep->hw_addr + OTX_EP_R_IN_CONTROL(iq_no));\n+\tiq->desc_size = otx_ep->conf->iq.instr_type;\n+\n \t/* Write the start of the input queue's ring and its size */\n \totx_ep_write64(iq->base_addr_dma, otx_ep->hw_addr,\n \t\t OTX_EP_R_IN_INSTR_BADDR(iq_no));\n", "prefixes": [ "1/3" ] }