Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/132637/?format=api
{ "id": 132637, "url": "http://patchwork.dpdk.org/api/patches/132637/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20231016184235.200427-1-getelson@nvidia.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20231016184235.200427-1-getelson@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20231016184235.200427-1-getelson@nvidia.com", "date": "2023-10-16T18:42:20", "name": "[v2,01/16] net/mlx5/hws: add support for reformat DevX object", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "54090547e7009b8bbb65b4f89acca838d88095b3", "submitter": { "id": 1882, "url": "http://patchwork.dpdk.org/api/people/1882/?format=api", "name": "Gregory Etelson", "email": "getelson@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patchwork.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20231016184235.200427-1-getelson@nvidia.com/mbox/", "series": [ { "id": 29662, "url": "http://patchwork.dpdk.org/api/series/29662/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=29662", "date": "2023-09-27T19:10:46", "name": "net/mlx5: support indirect list actions", "version": 1, "mbox": "http://patchwork.dpdk.org/series/29662/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/132637/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/132637/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id F417D43181;\n\tMon, 16 Oct 2023 20:43:09 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id C0F0F40299;\n\tMon, 16 Oct 2023 20:43:09 +0200 (CEST)", "from NAM04-BN8-obe.outbound.protection.outlook.com\n (mail-bn8nam04on2086.outbound.protection.outlook.com [40.107.100.86])\n by mails.dpdk.org (Postfix) with ESMTP id D513E40269\n for <dev@dpdk.org>; Mon, 16 Oct 2023 20:43:07 +0200 (CEST)", "from SA1P222CA0197.NAMP222.PROD.OUTLOOK.COM (2603:10b6:806:3c4::6)\n by LV3PR12MB9410.namprd12.prod.outlook.com (2603:10b6:408:212::19) with\n Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6886.36; Mon, 16 Oct\n 2023 18:43:06 +0000", "from SN1PEPF0002636C.namprd02.prod.outlook.com\n (2603:10b6:806:3c4:cafe::54) by SA1P222CA0197.outlook.office365.com\n (2603:10b6:806:3c4::6) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6886.36 via Frontend\n Transport; Mon, 16 Oct 2023 18:43:05 +0000", "from mail.nvidia.com (216.228.117.161) by\n SN1PEPF0002636C.mail.protection.outlook.com (10.167.241.137) with Microsoft\n SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.20.6838.22 via Frontend Transport; Mon, 16 Oct 2023 18:43:05 +0000", "from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com\n (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Mon, 16 Oct\n 2023 11:42:52 -0700", "from nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com\n (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Mon, 16 Oct\n 2023 11:42:49 -0700" ], "ARC-Seal": "i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none;\n b=dwcoOFIM64lGfH53ngZZAbo9DF5chd5hds8JvUO8U/2gZSJlfDMLJEMyMIluuyQLhAqSMj7eA43QfETcyDH/fvGc7pls+1Qj5bXSYZtCZGDLdRa56b5qGSfrBhzoNSOvmvQ4zPh0afSwpHsfjUc4aEEtlRXm7rfd1PeJEw7M/euKzT0ZkghLWBu+xvd4rtw3RmDL9Q/xMoBAs0j+9YM9z4dEgjL+wYNF9+6B2ddqhDi1xTXG69AWfxQkmZadVVltDflXcJH6Wx90LrCD+DsoonS8svpgAybARSSNV/dzLaLPu7gnvBTgyQCVUDaMVVW445hOkes2LBX9Mtn9SgtUXw==", "ARC-Message-Signature": "i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector9901;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=MFN9xBubL7vMGWOlF3XPKXk3Hrir//kkRc7zpTo4elE=;\n b=AbkuWh0cIA1aQ6Q5ysciNGiKRIG9Q+gpCuUt/u129Rd2yGZE94pWATewY0GLNiDcEvPfwZjkkHQjCQ7dcml/wKCAou37CWVOmjlr9h5LIG64R6+lRMyf2WdSJc8IKFABLzWCydjhb6fEjR+nuoWOXaiYwUL+XsnqYWgKd7fmQXncpa0bvPXfCz67ShWTZwWLVkvBQO2qIKVHWkPU/JEohTac9m6nSTt7uQ9hdfqlG5qwi1HuE4DoWgxO8AIHS9LSl31cYQtlefb67G1wI/0JgeB7CxnUIX/Y7XJPzijc6FjKQ4CKqyU/b6EA5OoFVTvUz4POMJ8HbP8qRARR9xa6bw==", "ARC-Authentication-Results": "i=1; mx.microsoft.com 1; spf=pass (sender ip is\n 216.228.117.161) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com;\n dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com;\n dkim=none (message not signed); arc=none", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=MFN9xBubL7vMGWOlF3XPKXk3Hrir//kkRc7zpTo4elE=;\n b=KmGOZ9kdsqGfNRhCLhVUp/IhdGC3DNNvEQVmPqaKwmI4XmgaFeyW5Zl9o2rTaK+1n02sVb9c9M5E0gZSDp5QDe2YXMy4k8pVxe0i73h4om/CaGrdagXPvtLQvoCyuF4KKDd65KlO5ilVGUvYCITVm6DdoEyHwe9Xm0j+goHMXPuTYJxXoyN3YPq8L04y6mrecS3wI+ubuEH6S11xsDhPhVc1tOn0ro+rdLhdU0P0ZrfFpiEor7D4B8UhH6NLCqH4C0w5C0UA0oJWOxG80Rz+xE3UzVqVmNfzzoh6CLhqNbpq1fz27oSZO7VWLV6N4HyRmPA2puirAWDXsbe0M9glxw==", "X-MS-Exchange-Authentication-Results": "spf=pass (sender IP is 216.228.117.161)\n smtp.mailfrom=nvidia.com;\n dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.117.161 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C", "From": "Gregory Etelson <getelson@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "<getelson@nvidia.com>, =?utf-8?b?wqA=?= <mkashani@nvidia.com>,\n\t=?utf-8?q?=C2=A0_=2E_=2E_/patches/upstream-pmd-indirect-actions-list/v2/v2-?=\n\t=?utf-8?q?0000-cover-letter_=2E_patch?= <rasland@nvidia.com>,\n Hamdan Igbaria <hamdani@nvidia.com>, Matan Azrad <matan@nvidia.com>,\n Viacheslav Ovsiienko <viacheslavo@nvidia.com>, Ori Kam <orika@nvidia.com>,\n Suanming Mou <suanmingm@nvidia.com>", "Subject": "[PATCH v2 01/16] net/mlx5/hws: add support for reformat DevX object", "Date": "Mon, 16 Oct 2023 21:42:20 +0300", "Message-ID": "<20231016184235.200427-1-getelson@nvidia.com>", "X-Mailer": "git-send-email 2.39.2", "In-Reply-To": "<20230927191046.405282-1-getelson@nvidia.com>", "References": "<20230927191046.405282-1-getelson@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.35]", "X-ClientProxiedBy": "rnnvmail202.nvidia.com (10.129.68.7) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "SN1PEPF0002636C:EE_|LV3PR12MB9410:EE_", "X-MS-Office365-Filtering-Correlation-Id": "68838d7d-94b0-4c63-cf4f-08dbce77bc51", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n GD0o3c0be4ct5kN9wSVPo8SSPX0cSuzBFk4u4SVKalI0S/dT+Tzgu2ViY+2GG6yN1GO+klluqWGMRNc/eVmYUqrUE1uEj1bKDuZj4+i08JzfRamZC3Tly5NAWpkeFz1oxjATYvYD4qi3oDD0pI6iDkI4EbGH5EfOnF4V4biKBUE7tWzwNCDQSSLSixTHbLhAJrRsEIhedBIvXwZHJcVMCiTZg+2hB2dfNDcwpEz/LzpuWEc3DMdfrOM5yfuWSCmVzCj1FqRG7XhI2GiBhmIYHol19ImMaciUks2zujKKmVOjMJHmDO/4BhiO4X5h/98ZvvHHGJnIdLA6AGM2q6ABM3JQ02C+vG3szQ2ihOrcj6PGuanD/mDLfJ7wuHSR0D55edOf18LnRttruyDqLWhQ8mNurbNuDShsA0wtxT1cP4nGfEEQPfK0bcE/InfaomIaQryY2Sa3dNfRAA4fUx1VyFsuanuMz7umkqrXtrmD3oC4zY694KJcvEABr9tiBXhFDWyh0/FeurhyYRv2msZVqWRoxCqA+XqqAPv+MvJJeLnNgFHGR1HvH2d5pGJ/38GkVo6xCBq27p1xim1FvwYU6xA71A8QAoutVi+sdIFTXa1I+0oWz/cVRSzTInUzaWhk8QL6bXQ6sPs2sGGF0eYBf7HkSmKnY77sXqORR9e2iSLv8gsjrEQiUY32+AzKGFsLHCkif428ARE0eFMpPqjPkFzBb1GjeC++JcE8sUtkih6mHzJrw87a7JRyBjAulziO", "X-Forefront-Antispam-Report": "CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE;\n SFS:(13230031)(4636009)(376002)(346002)(136003)(39860400002)(396003)(230922051799003)(1800799009)(451199024)(82310400011)(186009)(64100799003)(40470700004)(46966006)(36840700001)(47076005)(40460700003)(36860700001)(55016003)(7696005)(6916009)(316002)(54906003)(478600001)(70206006)(70586007)(5660300002)(8936002)(8676002)(4326008)(6666004)(2616005)(86362001)(41300700001)(2906002)(66899024)(40480700001)(82740400003)(16526019)(6286002)(107886003)(1076003)(26005)(336012)(426003)(356005)(83380400001)(7636003)(36756003);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "16 Oct 2023 18:43:05.7559 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 68838d7d-94b0-4c63-cf4f-08dbce77bc51", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n SN1PEPF0002636C.namprd02.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "LV3PR12MB9410", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Hamdan Igbaria <hamdani@nvidia.com>\n\nAdd support for creation of packet reformat object,\nvia the ALLOC_PACKET_REFORMAT_CONTEXT command.\n\nSigned-off-by: Hamdan Igbaria <hamdani@nvidia.com>\n---\n drivers/common/mlx5/mlx5_prm.h | 39 +++++++++++++++++\n drivers/net/mlx5/hws/mlx5dr_cmd.c | 60 ++++++++++++++++++++++++++\n drivers/net/mlx5/hws/mlx5dr_cmd.h | 11 +++++\n drivers/net/mlx5/hws/mlx5dr_internal.h | 5 +++\n drivers/net/mlx5/hws/mlx5dr_send.c | 5 ---\n 5 files changed, 115 insertions(+), 5 deletions(-)", "diff": "diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h\nindex 6e181a0eca..4192fff55b 100644\n--- a/drivers/common/mlx5/mlx5_prm.h\n+++ b/drivers/common/mlx5/mlx5_prm.h\n@@ -1218,6 +1218,8 @@ enum {\n \tMLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,\n \tMLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,\n \tMLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c,\n+\tMLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d,\n+\tMLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e,\n \tMLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,\n \tMLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,\n \tMLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00,\n@@ -5191,6 +5193,43 @@ struct mlx5_ifc_modify_flow_table_out_bits {\n \tu8 reserved_at_40[0x60];\n };\n \n+struct mlx5_ifc_packet_reformat_context_in_bits {\n+\tu8 reformat_type[0x8];\n+\tu8 reserved_at_8[0x4];\n+\tu8 reformat_param_0[0x4];\n+\tu8 reserved_at_16[0x6];\n+\tu8 reformat_data_size[0xa];\n+\n+\tu8 reformat_param_1[0x8];\n+\tu8 reserved_at_40[0x8];\n+\tu8 reformat_data[6][0x8];\n+\n+\tu8 more_reformat_data[][0x8];\n+};\n+\n+struct mlx5_ifc_alloc_packet_reformat_context_in_bits {\n+\tu8 opcode[0x10];\n+\tu8 uid[0x10];\n+\n+\tu8 reserved_at_20[0x10];\n+\tu8 op_mod[0x10];\n+\n+\tu8 reserved_at_40[0xa0];\n+\n+\tu8 packet_reformat_context[];\n+};\n+\n+struct mlx5_ifc_alloc_packet_reformat_out_bits {\n+\tu8 status[0x8];\n+\tu8 reserved_at_8[0x18];\n+\n+\tu8 syndrome[0x20];\n+\n+\tu8 packet_reformat_id[0x20];\n+\n+\tu8 reserved_at_60[0x20];\n+};\n+\n /* CQE format mask. */\n #define MLX5E_CQE_FORMAT_MASK 0xc\n \ndiff --git a/drivers/net/mlx5/hws/mlx5dr_cmd.c b/drivers/net/mlx5/hws/mlx5dr_cmd.c\nindex 594c59aee3..0ccbaee961 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_cmd.c\n+++ b/drivers/net/mlx5/hws/mlx5dr_cmd.c\n@@ -780,6 +780,66 @@ mlx5dr_cmd_sq_create(struct ibv_context *ctx,\n \treturn devx_obj;\n }\n \n+struct mlx5dr_devx_obj *\n+mlx5dr_cmd_packet_reformat_create(struct ibv_context *ctx,\n+\t\t\t\t struct mlx5dr_cmd_packet_reformat_create_attr *attr)\n+{\n+\tuint32_t out[MLX5_ST_SZ_DW(alloc_packet_reformat_out)] = {0};\n+\tsize_t insz, cmd_data_sz, cmd_total_sz;\n+\tstruct mlx5dr_devx_obj *devx_obj;\n+\tvoid *prctx;\n+\tvoid *pdata;\n+\tvoid *in;\n+\n+\tcmd_total_sz = MLX5_ST_SZ_BYTES(alloc_packet_reformat_context_in);\n+\tcmd_total_sz += MLX5_ST_SZ_BYTES(packet_reformat_context_in);\n+\tcmd_data_sz = MLX5_FLD_SZ_BYTES(packet_reformat_context_in, reformat_data);\n+\tinsz = align(cmd_total_sz + attr->data_sz - cmd_data_sz, DW_SIZE);\n+\tin = simple_calloc(1, insz);\n+\tif (!in) {\n+\t\trte_errno = ENOMEM;\n+\t\treturn NULL;\n+\t}\n+\n+\tMLX5_SET(alloc_packet_reformat_context_in, in, opcode,\n+\t\t MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT);\n+\n+\tprctx = MLX5_ADDR_OF(alloc_packet_reformat_context_in, in,\n+\t\t\t packet_reformat_context);\n+\tpdata = MLX5_ADDR_OF(packet_reformat_context_in, prctx, reformat_data);\n+\n+\tMLX5_SET(packet_reformat_context_in, prctx, reformat_type, attr->type);\n+\tMLX5_SET(packet_reformat_context_in, prctx, reformat_param_0, attr->reformat_param_0);\n+\tMLX5_SET(packet_reformat_context_in, prctx, reformat_data_size, attr->data_sz);\n+\tmemcpy(pdata, attr->data, attr->data_sz);\n+\n+\tdevx_obj = simple_malloc(sizeof(*devx_obj));\n+\tif (!devx_obj) {\n+\t\tDR_LOG(ERR, \"Failed to allocate memory for packet reformat object\");\n+\t\trte_errno = ENOMEM;\n+\t\tgoto out_free_in;\n+\t}\n+\n+\tdevx_obj->obj = mlx5_glue->devx_obj_create(ctx, in, insz, out, sizeof(out));\n+\tif (!devx_obj->obj) {\n+\t\tDR_LOG(ERR, \"Failed to create packet reformat\");\n+\t\trte_errno = errno;\n+\t\tgoto out_free_devx;\n+\t}\n+\n+\tdevx_obj->id = MLX5_GET(alloc_packet_reformat_out, out, packet_reformat_id);\n+\n+\tsimple_free(in);\n+\n+\treturn devx_obj;\n+\n+out_free_devx:\n+\tsimple_free(devx_obj);\n+out_free_in:\n+\tsimple_free(in);\n+\treturn NULL;\n+}\n+\n int mlx5dr_cmd_sq_modify_rdy(struct mlx5dr_devx_obj *devx_obj)\n {\n \tuint32_t out[MLX5_ST_SZ_DW(modify_sq_out)] = {0};\ndiff --git a/drivers/net/mlx5/hws/mlx5dr_cmd.h b/drivers/net/mlx5/hws/mlx5dr_cmd.h\nindex 8a495db9b3..f45b6c6b07 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_cmd.h\n+++ b/drivers/net/mlx5/hws/mlx5dr_cmd.h\n@@ -155,6 +155,13 @@ struct mlx5dr_cmd_allow_other_vhca_access_attr {\n \tuint8_t access_key[ACCESS_KEY_LEN];\n };\n \n+struct mlx5dr_cmd_packet_reformat_create_attr {\n+\tuint8_t type;\n+\tsize_t data_sz;\n+\tvoid *data;\n+\tuint8_t reformat_param_0;\n+};\n+\n struct mlx5dr_cmd_query_ft_caps {\n \tuint8_t max_level;\n \tuint8_t reparse;\n@@ -285,6 +292,10 @@ mlx5dr_cmd_forward_tbl_create(struct ibv_context *ctx,\n \n void mlx5dr_cmd_forward_tbl_destroy(struct mlx5dr_cmd_forward_tbl *tbl);\n \n+struct mlx5dr_devx_obj *\n+mlx5dr_cmd_packet_reformat_create(struct ibv_context *ctx,\n+\t\t\t\t struct mlx5dr_cmd_packet_reformat_create_attr *attr);\n+\n struct mlx5dr_devx_obj *\n mlx5dr_cmd_alias_obj_create(struct ibv_context *ctx,\n \t\t\t struct mlx5dr_cmd_alias_obj_create_attr *alias_attr);\ndiff --git a/drivers/net/mlx5/hws/mlx5dr_internal.h b/drivers/net/mlx5/hws/mlx5dr_internal.h\nindex c3c077667d..3770d28e62 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_internal.h\n+++ b/drivers/net/mlx5/hws/mlx5dr_internal.h\n@@ -91,4 +91,9 @@ static inline uint64_t roundup_pow_of_two(uint64_t n)\n \treturn n == 1 ? 1 : 1ULL << log2above(n);\n }\n \n+static inline unsigned long align(unsigned long val, unsigned long align)\n+{\n+\treturn (val + align - 1) & ~(align - 1);\n+}\n+\n #endif /* MLX5DR_INTERNAL_H_ */\ndiff --git a/drivers/net/mlx5/hws/mlx5dr_send.c b/drivers/net/mlx5/hws/mlx5dr_send.c\nindex e58fdeb117..622d574bfa 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_send.c\n+++ b/drivers/net/mlx5/hws/mlx5dr_send.c\n@@ -668,11 +668,6 @@ static int mlx5dr_send_ring_create_sq_obj(struct mlx5dr_context *ctx,\n \treturn err;\n }\n \n-static inline unsigned long align(unsigned long val, unsigned long align)\n-{\n-\treturn (val + align - 1) & ~(align - 1);\n-}\n-\n static int mlx5dr_send_ring_open_sq(struct mlx5dr_context *ctx,\n \t\t\t\t struct mlx5dr_send_engine *queue,\n \t\t\t\t struct mlx5dr_send_ring_sq *sq,\n", "prefixes": [ "v2", "01/16" ] }