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{ "id": 132645, "url": "http://patchwork.dpdk.org/api/patches/132645/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20231016184235.200427-9-getelson@nvidia.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20231016184235.200427-9-getelson@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20231016184235.200427-9-getelson@nvidia.com", "date": "2023-10-16T18:42:28", "name": "[v2,09/16] net/mlx5: fix mirror action validation", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "31760c8f36cd1653b744d33a26dc8d32f3383880", "submitter": { "id": 1882, "url": "http://patchwork.dpdk.org/api/people/1882/?format=api", "name": "Gregory Etelson", "email": "getelson@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patchwork.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20231016184235.200427-9-getelson@nvidia.com/mbox/", "series": [ { "id": 29662, "url": "http://patchwork.dpdk.org/api/series/29662/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=29662", "date": "2023-09-27T19:10:46", "name": "net/mlx5: support indirect list actions", "version": 1, "mbox": "http://patchwork.dpdk.org/series/29662/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/132645/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/132645/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 4B8DB43181;\n\tMon, 16 Oct 2023 20:44:12 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id ABE5240EAB;\n\tMon, 16 Oct 2023 20:43:37 +0200 (CEST)", "from NAM11-CO1-obe.outbound.protection.outlook.com\n (mail-co1nam11on2052.outbound.protection.outlook.com [40.107.220.52])\n by mails.dpdk.org (Postfix) with ESMTP id AC70240EAB\n for <dev@dpdk.org>; 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helo=mail.nvidia.com; pr=C", "From": "Gregory Etelson <getelson@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "<getelson@nvidia.com>, =?utf-8?b?wqA=?= <mkashani@nvidia.com>,\n\t=?utf-8?q?=C2=A0_=2E_=2E_/patches/upstream-pmd-indirect-actions-list/v2/v2-?=\n\t=?utf-8?q?0000-cover-letter_=2E_patch?= <rasland@nvidia.com>,\n Matan Azrad <matan@nvidia.com>,\n Viacheslav Ovsiienko <viacheslavo@nvidia.com>, Ori Kam <orika@nvidia.com>,\n Suanming Mou <suanmingm@nvidia.com>", "Subject": "[PATCH v2 09/16] net/mlx5: fix mirror action validation", "Date": "Mon, 16 Oct 2023 21:42:28 +0300", "Message-ID": "<20231016184235.200427-9-getelson@nvidia.com>", "X-Mailer": "git-send-email 2.39.2", "In-Reply-To": "<20231016184235.200427-1-getelson@nvidia.com>", "References": "<20230927191046.405282-1-getelson@nvidia.com>\n <20231016184235.200427-1-getelson@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.35]", "X-ClientProxiedBy": "rnnvmail202.nvidia.com (10.129.68.7) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "MWH0EPF000989E7:EE_|DS7PR12MB5863:EE_", "X-MS-Office365-Filtering-Correlation-Id": "0f35737c-9c31-4ce1-4eda-08dbce77cca5", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n j1bRmioBO40NVa0BX48BuX4majRVtOrgmsDx147FBIFPvwBtnGo6/ei/vAMFXXfJGjT6bSOpmiPkgLjU4EyM/YUwXgiFrkRjUb9gNQGHLfDqDRweR+QE8wjYdvD7vn1j+yaFo/OS+DFAq+NaegwOHQ8SJ5GXkMRmxJNOQv6Y2ihz1cGtvPvSzj/fcFIH5+FArrIIfbCkglB655XxXltf6g6rtIJgAeJD/pDGS0YkaHp3bi8hj0RJKsEBimrzB+cxe0z3JZdrumIalZAFsoQfdwYxj01/ztBOdxKPyZ6g718IfePUezT9ht4H/jNBUR9fPfV2YSJ5EqR/nCesYH1cBpxXYvA/J4q1dv4+EpsCtRHilossuiVHXi+RLuiF+JR+L1SjON6vrC3yl/GSI8vwqZg9CINYgKEMVvFh2UPyY9mVG4ehq0LU9WFDIje9QyRmi6NVAeGqR3kgqWSRdQTzhFtnsS4Jiqqz8rpD1GxH8r4fKInkx5zmdUN+1K7VgJRsoBOxOQkbcYKPnWsfeT+OAZTujD23cUWkdL1Tr0JeX1/Yit/B7n7lfiQ0sGTV9o3OSamjWerHa8Z3kHLg2/tApfpjaKLVWy5ridEtPxGutovgfOa7CBxXxD132dHWMmXj4vNwWvmGVfWJrIk2/ip78bo21wEPwFlHTgEFDmf56Ld8c6Bj0L0SDTzQhH0dJr5V15DpEP0HF0EJNv2CQ/IzWbY1wXC6YlRUsyoy/T2jwIo=", "X-Forefront-Antispam-Report": "CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE;\n SFS:(13230031)(4636009)(136003)(346002)(39860400002)(376002)(396003)(230922051799003)(64100799003)(186009)(451199024)(1800799009)(82310400011)(40470700004)(46966006)(36840700001)(82740400003)(426003)(336012)(47076005)(1076003)(83380400001)(26005)(6286002)(16526019)(2616005)(86362001)(36860700001)(7636003)(356005)(107886003)(36756003)(7696005)(2906002)(6666004)(55016003)(40480700001)(5660300002)(41300700001)(54906003)(6916009)(316002)(70586007)(70206006)(8676002)(478600001)(4326008)(40460700003)(8936002);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "16 Oct 2023 18:43:33.1310 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 0f35737c-9c31-4ce1-4eda-08dbce77cca5", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n MWH0EPF000989E7.namprd02.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DS7PR12MB5863", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "HWS mirror flow action validation rejected flows in NIC domain,\nif PMD FDB mode was active.\n\nThe patch allows NIC mirror action in FDB mode.\n\nFixes: 0284c9b82ee8 (\"net/mlx5: support HWS mirror action\")\nSigned-off-by: Gregory Etelson <getelson@nvidia.com>\n---\n drivers/net/mlx5/mlx5_flow_hw.c | 20 +++++++++++++-------\n 1 file changed, 13 insertions(+), 7 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c\nindex 44ed23b1fd..910d42a5f5 100644\n--- a/drivers/net/mlx5/mlx5_flow_hw.c\n+++ b/drivers/net/mlx5/mlx5_flow_hw.c\n@@ -9547,14 +9547,15 @@ mlx5_mirror_terminal_action(const struct rte_flow_action *action)\n \n static bool\n mlx5_mirror_validate_sample_action(struct rte_eth_dev *dev,\n-\tconst struct rte_flow_action *action)\n+\t\t\t\t const struct rte_flow_attr *flow_attr,\n+\t\t\t\t const struct rte_flow_action *action)\n {\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n \n \tswitch(action->type) {\n \tcase RTE_FLOW_ACTION_TYPE_QUEUE:\n \tcase RTE_FLOW_ACTION_TYPE_RSS:\n-\t\tif (priv->sh->esw_mode)\n+\t\tif (flow_attr->transfer)\n \t\t\treturn false;\n \t\tbreak;\n \tcase RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:\n@@ -9562,7 +9563,7 @@ mlx5_mirror_validate_sample_action(struct rte_eth_dev *dev,\n \tcase RTE_FLOW_ACTION_TYPE_RAW_DECAP:\n \tcase RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:\n \tcase RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:\n-\t\tif (!priv->sh->esw_mode)\n+\t\tif (!priv->sh->esw_mode && !flow_attr->transfer)\n \t\t\treturn false;\n \t\tif (action[0].type == RTE_FLOW_ACTION_TYPE_RAW_DECAP &&\n \t\t action[1].type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP)\n@@ -9584,19 +9585,22 @@ mlx5_mirror_validate_sample_action(struct rte_eth_dev *dev,\n */\n static int\n mlx5_hw_mirror_actions_list_validate(struct rte_eth_dev *dev,\n+\t\t\t\t const struct rte_flow_attr *flow_attr,\n \t\t\t\t const struct rte_flow_action *actions)\n {\n \tif (actions[0].type == RTE_FLOW_ACTION_TYPE_SAMPLE) {\n \t\tint i = 1;\n \t\tbool valid;\n \t\tconst struct rte_flow_action_sample *sample = actions[0].conf;\n-\t\tvalid = mlx5_mirror_validate_sample_action(dev, sample->actions);\n+\t\tvalid = mlx5_mirror_validate_sample_action(dev, flow_attr,\n+\t\t\t\t\t\t\t sample->actions);\n \t\tif (!valid)\n \t\t\treturn -EINVAL;\n \t\tif (actions[1].type == RTE_FLOW_ACTION_TYPE_SAMPLE) {\n \t\t\ti = 2;\n \t\t\tsample = actions[1].conf;\n-\t\t\tvalid = mlx5_mirror_validate_sample_action(dev, sample->actions);\n+\t\t\tvalid = mlx5_mirror_validate_sample_action(dev, flow_attr,\n+\t\t\t\t\t\t\t\t sample->actions);\n \t\t\tif (!valid)\n \t\t\t\treturn -EINVAL;\n \t\t}\n@@ -9780,15 +9784,17 @@ mlx5_hw_mirror_handle_create(struct rte_eth_dev *dev,\n \tstruct mlx5_mirror *mirror;\n \tenum mlx5dr_table_type table_type;\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n+\tconst struct rte_flow_attr *flow_attr = &table_cfg->attr.flow_attr;\n \tstruct mlx5dr_action_dest_attr mirror_attr[MLX5_MIRROR_MAX_CLONES_NUM + 1];\n \tenum mlx5dr_action_type array_action_types[MLX5_MIRROR_MAX_CLONES_NUM + 1]\n \t\t\t\t\t\t [MLX5_MIRROR_MAX_SAMPLE_ACTIONS_LEN + 1];\n \n \tmemset(mirror_attr, 0, sizeof(mirror_attr));\n \tmemset(array_action_types, 0, sizeof(array_action_types));\n-\ttable_type = get_mlx5dr_table_type(&table_cfg->attr.flow_attr);\n+\ttable_type = get_mlx5dr_table_type(flow_attr);\n \thws_flags = mlx5_hw_act_flag[MLX5_HW_ACTION_FLAG_NONE_ROOT][table_type];\n-\tclones_num = mlx5_hw_mirror_actions_list_validate(dev, actions);\n+\tclones_num = mlx5_hw_mirror_actions_list_validate(dev, flow_attr,\n+\t\t\t\t\t\t\t actions);\n \tif (clones_num < 0) {\n \t\trte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,\n \t\t\t\t actions, \"Invalid mirror list format\");\n", "prefixes": [ "v2", "09/16" ] }