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{
    "id": 132699,
    "url": "http://patchwork.dpdk.org/api/patches/132699/?format=api",
    "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20231017054545.1692509-10-chaoyong.he@corigine.com/",
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    "msgid": "<20231017054545.1692509-10-chaoyong.he@corigine.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20231017054545.1692509-10-chaoyong.he@corigine.com",
    "date": "2023-10-17T05:45:29",
    "name": "[09/25] net/nfp: change the parameter of APIs",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "882a0bd63320324a7be1070490fba1aabac4c793",
    "submitter": {
        "id": 2554,
        "url": "http://patchwork.dpdk.org/api/people/2554/?format=api",
        "name": "Chaoyong He",
        "email": "chaoyong.he@corigine.com"
    },
    "delegate": {
        "id": 319,
        "url": "http://patchwork.dpdk.org/api/users/319/?format=api",
        "username": "fyigit",
        "first_name": "Ferruh",
        "last_name": "Yigit",
        "email": "ferruh.yigit@amd.com"
    },
    "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20231017054545.1692509-10-chaoyong.he@corigine.com/mbox/",
    "series": [
        {
            "id": 29865,
            "url": "http://patchwork.dpdk.org/api/series/29865/?format=api",
            "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=29865",
            "date": "2023-10-17T05:45:20",
            "name": "add the NFP vDPA PMD",
            "version": 1,
            "mbox": "http://patchwork.dpdk.org/series/29865/mbox/"
        }
    ],
    "comments": "http://patchwork.dpdk.org/api/patches/132699/comments/",
    "check": "success",
    "checks": "http://patchwork.dpdk.org/api/patches/132699/checks/",
    "tags": {},
    "related": [],
    "headers": {
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        "From": "Chaoyong He <chaoyong.he@corigine.com>",
        "To": "dev@dpdk.org",
        "Cc": "oss-drivers@corigine.com, Chaoyong He <chaoyong.he@corigine.com>,\n Long Wu <long.wu@corigine.com>, Peng Zhang <peng.zhang@corigine.com>",
        "Subject": "[PATCH 09/25] net/nfp: change the parameter of APIs",
        "Date": "Tue, 17 Oct 2023 13:45:29 +0800",
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    "content": "Change the parameter of some APIs from 'struct nfp_net_hw' into the\nsuper class 'struct nfp_hw', prepare for the upcoming common library.\n\nSigned-off-by: Chaoyong He <chaoyong.he@corigine.com>\nReviewed-by: Long Wu <long.wu@corigine.com>\nReviewed-by: Peng Zhang <peng.zhang@corigine.com>\n---\n drivers/net/nfp/flower/nfp_flower.c           |  24 ++--\n .../net/nfp/flower/nfp_flower_representor.c   |  10 +-\n drivers/net/nfp/nfd3/nfp_nfd3_dp.c            |   4 +-\n drivers/net/nfp/nfdk/nfp_nfdk_dp.c            |   4 +-\n drivers/net/nfp/nfp_ethdev.c                  |   8 +-\n drivers/net/nfp/nfp_ethdev_vf.c               |  12 +-\n drivers/net/nfp/nfp_ipsec.c                   |   4 +-\n drivers/net/nfp/nfp_net_common.c              | 129 +++++++++---------\n drivers/net/nfp/nfp_net_common.h              |  32 ++---\n drivers/net/nfp/nfp_rxtx.c                    |   4 +-\n 10 files changed, 116 insertions(+), 115 deletions(-)",
    "diff": "diff --git a/drivers/net/nfp/flower/nfp_flower.c b/drivers/net/nfp/flower/nfp_flower.c\nindex 2aa0d9939e..0fc1342740 100644\n--- a/drivers/net/nfp/flower/nfp_flower.c\n+++ b/drivers/net/nfp/flower/nfp_flower.c\n@@ -36,7 +36,7 @@ nfp_pf_repr_enable_queues(struct rte_eth_dev *dev)\n \tfor (i = 0; i < dev->data->nb_tx_queues; i++)\n \t\tenabled_queues |= (1 << i);\n \n-\tnn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, enabled_queues);\n+\tnn_cfg_writeq(&hw->super, NFP_NET_CFG_TXRS_ENABLE, enabled_queues);\n \n \tenabled_queues = 0;\n \n@@ -44,7 +44,7 @@ nfp_pf_repr_enable_queues(struct rte_eth_dev *dev)\n \tfor (i = 0; i < dev->data->nb_rx_queues; i++)\n \t\tenabled_queues |= (1 << i);\n \n-\tnn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, enabled_queues);\n+\tnn_cfg_writeq(&hw->super, NFP_NET_CFG_RXRS_ENABLE, enabled_queues);\n }\n \n static void\n@@ -58,8 +58,8 @@ nfp_pf_repr_disable_queues(struct rte_eth_dev *dev)\n \trepr = dev->data->dev_private;\n \thw = repr->app_fw_flower->pf_hw;\n \n-\tnn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, 0);\n-\tnn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, 0);\n+\tnn_cfg_writeq(&hw->super, NFP_NET_CFG_TXRS_ENABLE, 0);\n+\tnn_cfg_writeq(&hw->super, NFP_NET_CFG_RXRS_ENABLE, 0);\n \n \tnew_ctrl = hw->super.ctrl & ~NFP_NET_CFG_CTRL_ENABLE;\n \tupdate = NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING |\n@@ -114,7 +114,7 @@ nfp_flower_pf_start(struct rte_eth_dev *dev)\n \tif ((hw->super.cap & NFP_NET_CFG_CTRL_RINGCFG) != 0)\n \t\tnew_ctrl |= NFP_NET_CFG_CTRL_RINGCFG;\n \n-\tnn_cfg_writel(hw, NFP_NET_CFG_CTRL, new_ctrl);\n+\tnn_cfg_writel(&hw->super, NFP_NET_CFG_CTRL, new_ctrl);\n \n \t/* If an error when reconfig we avoid to change hw state */\n \tret = nfp_net_reconfig(hw, new_ctrl, update);\n@@ -219,7 +219,7 @@ nfp_flower_pf_close(struct rte_eth_dev *dev)\n \t/* Cancel possible impending LSC work here before releasing the port */\n \trte_eal_alarm_cancel(nfp_net_dev_interrupt_delayed_handler, (void *)dev);\n \n-\tnn_cfg_writeb(hw, NFP_NET_CFG_LSC, 0xff);\n+\tnn_cfg_writeb(&hw->super, NFP_NET_CFG_LSC, 0xff);\n \n \trte_eth_dev_release_port(dev);\n \n@@ -358,9 +358,9 @@ nfp_flower_init_vnic_common(struct nfp_net_hw *hw,\n \t\treturn err;\n \n \t/* Work out where in the BAR the queues start */\n-\tstart_q = nn_cfg_readl(hw, NFP_NET_CFG_START_TXQ);\n+\tstart_q = nn_cfg_readl(&hw->super, NFP_NET_CFG_START_TXQ);\n \ttx_bar_off = (uint64_t)start_q * NFP_QCP_QUEUE_ADDR_SZ;\n-\tstart_q = nn_cfg_readl(hw, NFP_NET_CFG_START_RXQ);\n+\tstart_q = nn_cfg_readl(&hw->super, NFP_NET_CFG_START_RXQ);\n \trx_bar_off = (uint64_t)start_q * NFP_QCP_QUEUE_ADDR_SZ;\n \n \thw->tx_bar = pf_dev->qc_bar + tx_bar_off;\n@@ -545,8 +545,8 @@ nfp_flower_init_ctrl_vnic(struct nfp_net_hw *hw)\n \t\t * Telling the HW about the physical address of the RX ring and number\n \t\t * of descriptors in log2 format.\n \t\t */\n-\t\tnn_cfg_writeq(hw, NFP_NET_CFG_RXR_ADDR(i), rxq->dma);\n-\t\tnn_cfg_writeb(hw, NFP_NET_CFG_RXR_SZ(i), rte_log2_u32(CTRL_VNIC_NB_DESC));\n+\t\tnn_cfg_writeq(&hw->super, NFP_NET_CFG_RXR_ADDR(i), rxq->dma);\n+\t\tnn_cfg_writeb(&hw->super, NFP_NET_CFG_RXR_SZ(i), rte_log2_u32(CTRL_VNIC_NB_DESC));\n \t}\n \n \tsnprintf(ctrl_txring_name, sizeof(ctrl_txring_name), \"%s_cttx_ring\", pci_name);\n@@ -610,8 +610,8 @@ nfp_flower_init_ctrl_vnic(struct nfp_net_hw *hw)\n \t\t * Telling the HW about the physical address of the TX ring and number\n \t\t * of descriptors in log2 format.\n \t\t */\n-\t\tnn_cfg_writeq(hw, NFP_NET_CFG_TXR_ADDR(i), txq->dma);\n-\t\tnn_cfg_writeb(hw, NFP_NET_CFG_TXR_SZ(i), rte_log2_u32(CTRL_VNIC_NB_DESC));\n+\t\tnn_cfg_writeq(&hw->super, NFP_NET_CFG_TXR_ADDR(i), txq->dma);\n+\t\tnn_cfg_writeb(&hw->super, NFP_NET_CFG_TXR_SZ(i), rte_log2_u32(CTRL_VNIC_NB_DESC));\n \t}\n \n \treturn 0;\ndiff --git a/drivers/net/nfp/flower/nfp_flower_representor.c b/drivers/net/nfp/flower/nfp_flower_representor.c\nindex 650f09a475..b52c6f514a 100644\n--- a/drivers/net/nfp/flower/nfp_flower_representor.c\n+++ b/drivers/net/nfp/flower/nfp_flower_representor.c\n@@ -97,8 +97,8 @@ nfp_pf_repr_rx_queue_setup(struct rte_eth_dev *dev,\n \t * Telling the HW about the physical address of the RX ring and number\n \t * of descriptors in log2 format.\n \t */\n-\tnn_cfg_writeq(hw, NFP_NET_CFG_RXR_ADDR(queue_idx), rxq->dma);\n-\tnn_cfg_writeb(hw, NFP_NET_CFG_RXR_SZ(queue_idx), rte_log2_u32(nb_desc));\n+\tnn_cfg_writeq(&hw->super, NFP_NET_CFG_RXR_ADDR(queue_idx), rxq->dma);\n+\tnn_cfg_writeb(&hw->super, NFP_NET_CFG_RXR_SZ(queue_idx), rte_log2_u32(nb_desc));\n \n \treturn 0;\n }\n@@ -181,8 +181,8 @@ nfp_pf_repr_tx_queue_setup(struct rte_eth_dev *dev,\n \t * Telling the HW about the physical address of the TX ring and number\n \t * of descriptors in log2 format.\n \t */\n-\tnn_cfg_writeq(hw, NFP_NET_CFG_TXR_ADDR(queue_idx), txq->dma);\n-\tnn_cfg_writeb(hw, NFP_NET_CFG_TXR_SZ(queue_idx), rte_log2_u32(nb_desc));\n+\tnn_cfg_writeq(&hw->super, NFP_NET_CFG_TXR_ADDR(queue_idx), txq->dma);\n+\tnn_cfg_writeb(&hw->super, NFP_NET_CFG_TXR_SZ(queue_idx), rte_log2_u32(nb_desc));\n \n \treturn 0;\n }\n@@ -228,7 +228,7 @@ nfp_flower_repr_link_update(struct rte_eth_dev *dev,\n \t\t\t\t}\n \t\t\t}\n \t\t} else {\n-\t\t\tnn_link_status = nn_cfg_readw(pf_hw, NFP_NET_CFG_STS);\n+\t\t\tnn_link_status = nn_cfg_readw(&pf_hw->super, NFP_NET_CFG_STS);\n \t\t\tnn_link_status = (nn_link_status >> NFP_NET_CFG_STS_LINK_RATE_SHIFT) &\n \t\t\t\t\tNFP_NET_CFG_STS_LINK_RATE_MASK;\n \ndiff --git a/drivers/net/nfp/nfd3/nfp_nfd3_dp.c b/drivers/net/nfp/nfd3/nfp_nfd3_dp.c\nindex 9f03b56c0c..68a841b69e 100644\n--- a/drivers/net/nfp/nfd3/nfp_nfd3_dp.c\n+++ b/drivers/net/nfp/nfd3/nfp_nfd3_dp.c\n@@ -465,8 +465,8 @@ nfp_net_nfd3_tx_queue_setup(struct rte_eth_dev *dev,\n \t * Telling the HW about the physical address of the TX ring and number\n \t * of descriptors in log2 format.\n \t */\n-\tnn_cfg_writeq(hw, NFP_NET_CFG_TXR_ADDR(queue_idx), txq->dma);\n-\tnn_cfg_writeb(hw, NFP_NET_CFG_TXR_SZ(queue_idx), rte_log2_u32(txq->tx_count));\n+\tnn_cfg_writeq(&hw->super, NFP_NET_CFG_TXR_ADDR(queue_idx), txq->dma);\n+\tnn_cfg_writeb(&hw->super, NFP_NET_CFG_TXR_SZ(queue_idx), rte_log2_u32(txq->tx_count));\n \n \treturn 0;\n }\ndiff --git a/drivers/net/nfp/nfdk/nfp_nfdk_dp.c b/drivers/net/nfp/nfdk/nfp_nfdk_dp.c\nindex bc027210af..cef27b0d92 100644\n--- a/drivers/net/nfp/nfdk/nfp_nfdk_dp.c\n+++ b/drivers/net/nfp/nfdk/nfp_nfdk_dp.c\n@@ -542,8 +542,8 @@ nfp_net_nfdk_tx_queue_setup(struct rte_eth_dev *dev,\n \t * Telling the HW about the physical address of the TX ring and number\n \t * of descriptors in log2 format.\n \t */\n-\tnn_cfg_writeq(hw, NFP_NET_CFG_TXR_ADDR(queue_idx), txq->dma);\n-\tnn_cfg_writeb(hw, NFP_NET_CFG_TXR_SZ(queue_idx), rte_log2_u32(txq->tx_count));\n+\tnn_cfg_writeq(&hw->super, NFP_NET_CFG_TXR_ADDR(queue_idx), txq->dma);\n+\tnn_cfg_writeb(&hw->super, NFP_NET_CFG_TXR_SZ(queue_idx), rte_log2_u32(txq->tx_count));\n \n \treturn 0;\n }\ndiff --git a/drivers/net/nfp/nfp_ethdev.c b/drivers/net/nfp/nfp_ethdev.c\nindex ec9f6041fd..6a4455e50f 100644\n--- a/drivers/net/nfp/nfp_ethdev.c\n+++ b/drivers/net/nfp/nfp_ethdev.c\n@@ -284,7 +284,7 @@ nfp_net_close(struct rte_eth_dev *dev)\n \n \t/* Only free PF resources after all physical ports have been closed */\n \t/* Mark this port as unused and free device priv resources */\n-\tnn_cfg_writeb(hw, NFP_NET_CFG_LSC, 0xff);\n+\tnn_cfg_writeb(&hw->super, NFP_NET_CFG_LSC, 0xff);\n \tapp_fw_nic->ports[hw->idx] = NULL;\n \trte_eth_dev_release_port(dev);\n \n@@ -566,8 +566,8 @@ nfp_net_init(struct rte_eth_dev *eth_dev)\n \t}\n \n \t/* Work out where in the BAR the queues start. */\n-\ttx_base = nn_cfg_readl(hw, NFP_NET_CFG_START_TXQ);\n-\trx_base = nn_cfg_readl(hw, NFP_NET_CFG_START_RXQ);\n+\ttx_base = nn_cfg_readl(&hw->super, NFP_NET_CFG_START_TXQ);\n+\trx_base = nn_cfg_readl(&hw->super, NFP_NET_CFG_START_RXQ);\n \n \thw->tx_bar = pf_dev->qc_bar + tx_base * NFP_QCP_QUEUE_ADDR_SZ;\n \thw->rx_bar = pf_dev->qc_bar + rx_base * NFP_QCP_QUEUE_ADDR_SZ;\n@@ -624,7 +624,7 @@ nfp_net_init(struct rte_eth_dev *eth_dev)\n \trte_intr_callback_register(pci_dev->intr_handle,\n \t\t\tnfp_net_dev_interrupt_handler, (void *)eth_dev);\n \t/* Telling the firmware about the LSC interrupt entry */\n-\tnn_cfg_writeb(hw, NFP_NET_CFG_LSC, NFP_NET_IRQ_LSC_IDX);\n+\tnn_cfg_writeb(&hw->super, NFP_NET_CFG_LSC, NFP_NET_IRQ_LSC_IDX);\n \t/* Recording current stats counters values */\n \tnfp_net_stats_reset(eth_dev);\n \ndiff --git a/drivers/net/nfp/nfp_ethdev_vf.c b/drivers/net/nfp/nfp_ethdev_vf.c\nindex 684968903c..7fb2a3d378 100644\n--- a/drivers/net/nfp/nfp_ethdev_vf.c\n+++ b/drivers/net/nfp/nfp_ethdev_vf.c\n@@ -20,10 +20,10 @@ nfp_netvf_read_mac(struct nfp_net_hw *hw)\n {\n \tuint32_t tmp;\n \n-\ttmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR));\n+\ttmp = rte_be_to_cpu_32(nn_cfg_readl(&hw->super, NFP_NET_CFG_MACADDR));\n \tmemcpy(&hw->mac_addr.addr_bytes[0], &tmp, 4);\n \n-\ttmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR + 4));\n+\ttmp = rte_be_to_cpu_32(nn_cfg_readl(&hw->super, NFP_NET_CFG_MACADDR + 4));\n \tmemcpy(&hw->mac_addr.addr_bytes[4], &tmp, 2);\n }\n \n@@ -97,7 +97,7 @@ nfp_netvf_start(struct rte_eth_dev *dev)\n \tif ((hw->super.cap & NFP_NET_CFG_CTRL_RINGCFG) != 0)\n \t\tnew_ctrl |= NFP_NET_CFG_CTRL_RINGCFG;\n \n-\tnn_cfg_writel(hw, NFP_NET_CFG_CTRL, new_ctrl);\n+\tnn_cfg_writel(&hw->super, NFP_NET_CFG_CTRL, new_ctrl);\n \tif (nfp_net_reconfig(hw, new_ctrl, update) != 0)\n \t\treturn -EIO;\n \n@@ -299,9 +299,9 @@ nfp_netvf_init(struct rte_eth_dev *eth_dev)\n \t}\n \n \t/* Work out where in the BAR the queues start. */\n-\tstart_q = nn_cfg_readl(hw, NFP_NET_CFG_START_TXQ);\n+\tstart_q = nn_cfg_readl(&hw->super, NFP_NET_CFG_START_TXQ);\n \ttx_bar_off = nfp_qcp_queue_offset(dev_info, start_q);\n-\tstart_q = nn_cfg_readl(hw, NFP_NET_CFG_START_RXQ);\n+\tstart_q = nn_cfg_readl(&hw->super, NFP_NET_CFG_START_RXQ);\n \trx_bar_off = nfp_qcp_queue_offset(dev_info, start_q);\n \n \thw->tx_bar = (uint8_t *)pci_dev->mem_resource[2].addr + tx_bar_off;\n@@ -357,7 +357,7 @@ nfp_netvf_init(struct rte_eth_dev *eth_dev)\n \t\trte_intr_callback_register(pci_dev->intr_handle,\n \t\t\t\tnfp_net_dev_interrupt_handler, (void *)eth_dev);\n \t\t/* Telling the firmware about the LSC interrupt entry */\n-\t\tnn_cfg_writeb(hw, NFP_NET_CFG_LSC, NFP_NET_IRQ_LSC_IDX);\n+\t\tnn_cfg_writeb(&hw->super, NFP_NET_CFG_LSC, NFP_NET_IRQ_LSC_IDX);\n \t\t/* Recording current stats counters values */\n \t\tnfp_net_stats_reset(eth_dev);\n \t}\ndiff --git a/drivers/net/nfp/nfp_ipsec.c b/drivers/net/nfp/nfp_ipsec.c\nindex af85e8575c..db3b7492e1 100644\n--- a/drivers/net/nfp/nfp_ipsec.c\n+++ b/drivers/net/nfp/nfp_ipsec.c\n@@ -445,7 +445,7 @@ nfp_ipsec_cfg_cmd_issue(struct nfp_net_hw *hw,\n \tmsg->rsp = NFP_IPSEC_CFG_MSG_OK;\n \n \tfor (i = 0; i < msg_size; i++)\n-\t\tnn_cfg_writel(hw, NFP_NET_CFG_MBOX_VAL + 4 * i, msg->raw[i]);\n+\t\tnn_cfg_writel(&hw->super, NFP_NET_CFG_MBOX_VAL + 4 * i, msg->raw[i]);\n \n \tret = nfp_net_mbox_reconfig(hw, NFP_NET_CFG_MBOX_CMD_IPSEC);\n \tif (ret < 0) {\n@@ -459,7 +459,7 @@ nfp_ipsec_cfg_cmd_issue(struct nfp_net_hw *hw,\n \t * response. One example where the data is needed is for statistics.\n \t */\n \tfor (i = 0; i < msg_size; i++)\n-\t\tmsg->raw[i] = nn_cfg_readl(hw, NFP_NET_CFG_MBOX_VAL + 4 * i);\n+\t\tmsg->raw[i] = nn_cfg_readl(&hw->super, NFP_NET_CFG_MBOX_VAL + 4 * i);\n \n \tswitch (msg->rsp) {\n \tcase NFP_IPSEC_CFG_MSG_OK:\ndiff --git a/drivers/net/nfp/nfp_net_common.c b/drivers/net/nfp/nfp_net_common.c\nindex 25b8e3a613..4f830f2a2a 100644\n--- a/drivers/net/nfp/nfp_net_common.c\n+++ b/drivers/net/nfp/nfp_net_common.c\n@@ -182,7 +182,8 @@ nfp_net_notify_port_speed(struct nfp_net_hw *hw,\n \t * NFP_NET_CFG_STS_NSP_LINK_RATE.\n \t */\n \tif (link->link_status == RTE_ETH_LINK_DOWN) {\n-\t\tnn_cfg_writew(hw, NFP_NET_CFG_STS_NSP_LINK_RATE, NFP_NET_CFG_STS_LINK_RATE_UNKNOWN);\n+\t\tnn_cfg_writew(&hw->super, NFP_NET_CFG_STS_NSP_LINK_RATE,\n+\t\t\t\tNFP_NET_CFG_STS_LINK_RATE_UNKNOWN);\n \t\treturn;\n \t}\n \n@@ -190,7 +191,7 @@ nfp_net_notify_port_speed(struct nfp_net_hw *hw,\n \t * Link is up so write the link speed from the eth_table to\n \t * NFP_NET_CFG_STS_NSP_LINK_RATE.\n \t */\n-\tnn_cfg_writew(hw, NFP_NET_CFG_STS_NSP_LINK_RATE,\n+\tnn_cfg_writew(&hw->super, NFP_NET_CFG_STS_NSP_LINK_RATE,\n \t\t\tnfp_net_link_speed_rte2nfp(link->link_speed));\n }\n \n@@ -222,7 +223,7 @@ __nfp_net_reconfig(struct nfp_net_hw *hw,\n \n \t/* Poll update field, waiting for NFP to ack the config */\n \tfor (cnt = 0; ; cnt++) {\n-\t\tnew = nn_cfg_readl(hw, NFP_NET_CFG_UPDATE);\n+\t\tnew = nn_cfg_readl(&hw->super, NFP_NET_CFG_UPDATE);\n \t\tif (new == 0)\n \t\t\tbreak;\n \n@@ -270,8 +271,8 @@ nfp_net_reconfig(struct nfp_net_hw *hw,\n \n \trte_spinlock_lock(&hw->reconfig_lock);\n \n-\tnn_cfg_writel(hw, NFP_NET_CFG_CTRL, ctrl);\n-\tnn_cfg_writel(hw, NFP_NET_CFG_UPDATE, update);\n+\tnn_cfg_writel(&hw->super, NFP_NET_CFG_CTRL, ctrl);\n+\tnn_cfg_writel(&hw->super, NFP_NET_CFG_UPDATE, update);\n \n \trte_wmb();\n \n@@ -314,8 +315,8 @@ nfp_net_ext_reconfig(struct nfp_net_hw *hw,\n \n \trte_spinlock_lock(&hw->reconfig_lock);\n \n-\tnn_cfg_writel(hw, NFP_NET_CFG_CTRL_WORD1, ctrl_ext);\n-\tnn_cfg_writel(hw, NFP_NET_CFG_UPDATE, update);\n+\tnn_cfg_writel(&hw->super, NFP_NET_CFG_CTRL_WORD1, ctrl_ext);\n+\tnn_cfg_writel(&hw->super, NFP_NET_CFG_UPDATE, update);\n \n \trte_wmb();\n \n@@ -355,8 +356,8 @@ nfp_net_mbox_reconfig(struct nfp_net_hw *hw,\n \n \trte_spinlock_lock(&hw->reconfig_lock);\n \n-\tnn_cfg_writeq(hw, mbox + NFP_NET_CFG_MBOX_SIMPLE_CMD, mbox_cmd);\n-\tnn_cfg_writel(hw, NFP_NET_CFG_UPDATE, NFP_NET_CFG_UPDATE_MBOX);\n+\tnn_cfg_writeq(&hw->super, mbox + NFP_NET_CFG_MBOX_SIMPLE_CMD, mbox_cmd);\n+\tnn_cfg_writel(&hw->super, NFP_NET_CFG_UPDATE, NFP_NET_CFG_UPDATE_MBOX);\n \n \trte_wmb();\n \n@@ -370,7 +371,7 @@ nfp_net_mbox_reconfig(struct nfp_net_hw *hw,\n \t\treturn -EIO;\n \t}\n \n-\treturn nn_cfg_readl(hw, mbox + NFP_NET_CFG_MBOX_SIMPLE_RET);\n+\treturn nn_cfg_readl(&hw->super, mbox + NFP_NET_CFG_MBOX_SIMPLE_RET);\n }\n \n /*\n@@ -478,14 +479,14 @@ nfp_net_enable_queues(struct rte_eth_dev *dev)\n \tfor (i = 0; i < dev->data->nb_tx_queues; i++)\n \t\tenabled_queues |= (1 << i);\n \n-\tnn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, enabled_queues);\n+\tnn_cfg_writeq(&hw->super, NFP_NET_CFG_TXRS_ENABLE, enabled_queues);\n \n \t/* Enabling the required RX queues in the device */\n \tenabled_queues = 0;\n \tfor (i = 0; i < dev->data->nb_rx_queues; i++)\n \t\tenabled_queues |= (1 << i);\n \n-\tnn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, enabled_queues);\n+\tnn_cfg_writeq(&hw->super, NFP_NET_CFG_RXRS_ENABLE, enabled_queues);\n }\n \n void\n@@ -497,8 +498,8 @@ nfp_net_disable_queues(struct rte_eth_dev *dev)\n \n \thw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n \n-\tnn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, 0);\n-\tnn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, 0);\n+\tnn_cfg_writeq(&hw->super, NFP_NET_CFG_TXRS_ENABLE, 0);\n+\tnn_cfg_writeq(&hw->super, NFP_NET_CFG_RXRS_ENABLE, 0);\n \n \tnew_ctrl = hw->super.ctrl & ~NFP_NET_CFG_CTRL_ENABLE;\n \tupdate = NFP_NET_CFG_UPDATE_GEN |\n@@ -518,8 +519,8 @@ nfp_net_disable_queues(struct rte_eth_dev *dev)\n void\n nfp_net_params_setup(struct nfp_net_hw *hw)\n {\n-\tnn_cfg_writel(hw, NFP_NET_CFG_MTU, hw->mtu);\n-\tnn_cfg_writel(hw, NFP_NET_CFG_FLBUFSZ, hw->flbufsz);\n+\tnn_cfg_writel(&hw->super, NFP_NET_CFG_MTU, hw->mtu);\n+\tnn_cfg_writel(&hw->super, NFP_NET_CFG_FLBUFSZ, hw->flbufsz);\n }\n \n void\n@@ -596,7 +597,7 @@ nfp_configure_rx_interrupt(struct rte_eth_dev *dev,\n \tif (rte_intr_type_get(intr_handle) == RTE_INTR_HANDLE_UIO) {\n \t\tPMD_DRV_LOG(INFO, \"VF: enabling RX interrupt with UIO\");\n \t\t/* UIO just supports one queue and no LSC */\n-\t\tnn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(0), 0);\n+\t\tnn_cfg_writeb(&hw->super, NFP_NET_CFG_RXR_VEC(0), 0);\n \t\tif (rte_intr_vec_list_index_set(intr_handle, 0, 0) != 0)\n \t\t\treturn -1;\n \t} else {\n@@ -606,7 +607,7 @@ nfp_configure_rx_interrupt(struct rte_eth_dev *dev,\n \t\t\t * The first msix vector is reserved for non\n \t\t\t * efd interrupts.\n \t\t\t */\n-\t\t\tnn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(i), i + 1);\n+\t\t\tnn_cfg_writeb(&hw->super, NFP_NET_CFG_RXR_VEC(i), i + 1);\n \t\t\tif (rte_intr_vec_list_index_set(intr_handle, i, i + 1) != 0)\n \t\t\t\treturn -1;\n \t\t}\n@@ -771,7 +772,7 @@ nfp_net_link_update(struct rte_eth_dev *dev,\n \tmemset(&link, 0, sizeof(struct rte_eth_link));\n \n \t/* Read link status */\n-\tnn_link_status = nn_cfg_readw(hw, NFP_NET_CFG_STS);\n+\tnn_link_status = nn_cfg_readw(&hw->super, NFP_NET_CFG_STS);\n \tif ((nn_link_status & NFP_NET_CFG_STS_LINK) != 0)\n \t\tlink.link_status = RTE_ETH_LINK_UP;\n \n@@ -842,12 +843,12 @@ nfp_net_stats_get(struct rte_eth_dev *dev,\n \t\t\tbreak;\n \n \t\tnfp_dev_stats.q_ipackets[i] =\n-\t\t\t\tnn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));\n+\t\t\t\tnn_cfg_readq(&hw->super, NFP_NET_CFG_RXR_STATS(i));\n \t\tnfp_dev_stats.q_ipackets[i] -=\n \t\t\t\thw->eth_stats_base.q_ipackets[i];\n \n \t\tnfp_dev_stats.q_ibytes[i] =\n-\t\t\t\tnn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);\n+\t\t\t\tnn_cfg_readq(&hw->super, NFP_NET_CFG_RXR_STATS(i) + 0x8);\n \t\tnfp_dev_stats.q_ibytes[i] -=\n \t\t\t\thw->eth_stats_base.q_ibytes[i];\n \t}\n@@ -858,42 +859,42 @@ nfp_net_stats_get(struct rte_eth_dev *dev,\n \t\t\tbreak;\n \n \t\tnfp_dev_stats.q_opackets[i] =\n-\t\t\t\tnn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));\n+\t\t\t\tnn_cfg_readq(&hw->super, NFP_NET_CFG_TXR_STATS(i));\n \t\tnfp_dev_stats.q_opackets[i] -= hw->eth_stats_base.q_opackets[i];\n \n \t\tnfp_dev_stats.q_obytes[i] =\n-\t\t\t\tnn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);\n+\t\t\t\tnn_cfg_readq(&hw->super, NFP_NET_CFG_TXR_STATS(i) + 0x8);\n \t\tnfp_dev_stats.q_obytes[i] -= hw->eth_stats_base.q_obytes[i];\n \t}\n \n-\tnfp_dev_stats.ipackets = nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);\n+\tnfp_dev_stats.ipackets = nn_cfg_readq(&hw->super, NFP_NET_CFG_STATS_RX_FRAMES);\n \tnfp_dev_stats.ipackets -= hw->eth_stats_base.ipackets;\n \n-\tnfp_dev_stats.ibytes = nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);\n+\tnfp_dev_stats.ibytes = nn_cfg_readq(&hw->super, NFP_NET_CFG_STATS_RX_OCTETS);\n \tnfp_dev_stats.ibytes -= hw->eth_stats_base.ibytes;\n \n \tnfp_dev_stats.opackets =\n-\t\t\tnn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);\n+\t\t\tnn_cfg_readq(&hw->super, NFP_NET_CFG_STATS_TX_FRAMES);\n \tnfp_dev_stats.opackets -= hw->eth_stats_base.opackets;\n \n \tnfp_dev_stats.obytes =\n-\t\t\tnn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);\n+\t\t\tnn_cfg_readq(&hw->super, NFP_NET_CFG_STATS_TX_OCTETS);\n \tnfp_dev_stats.obytes -= hw->eth_stats_base.obytes;\n \n \t/* Reading general device stats */\n \tnfp_dev_stats.ierrors =\n-\t\t\tnn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);\n+\t\t\tnn_cfg_readq(&hw->super, NFP_NET_CFG_STATS_RX_ERRORS);\n \tnfp_dev_stats.ierrors -= hw->eth_stats_base.ierrors;\n \n \tnfp_dev_stats.oerrors =\n-\t\t\tnn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);\n+\t\t\tnn_cfg_readq(&hw->super, NFP_NET_CFG_STATS_TX_ERRORS);\n \tnfp_dev_stats.oerrors -= hw->eth_stats_base.oerrors;\n \n \t/* RX ring mbuf allocation failures */\n \tnfp_dev_stats.rx_nombuf = dev->data->rx_mbuf_alloc_failed;\n \n \tnfp_dev_stats.imissed =\n-\t\t\tnn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);\n+\t\t\tnn_cfg_readq(&hw->super, NFP_NET_CFG_STATS_RX_DISCARDS);\n \tnfp_dev_stats.imissed -= hw->eth_stats_base.imissed;\n \n \tmemcpy(stats, &nfp_dev_stats, sizeof(*stats));\n@@ -918,10 +919,10 @@ nfp_net_stats_reset(struct rte_eth_dev *dev)\n \t\t\tbreak;\n \n \t\thw->eth_stats_base.q_ipackets[i] =\n-\t\t\t\tnn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));\n+\t\t\t\tnn_cfg_readq(&hw->super, NFP_NET_CFG_RXR_STATS(i));\n \n \t\thw->eth_stats_base.q_ibytes[i] =\n-\t\t\t\tnn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);\n+\t\t\t\tnn_cfg_readq(&hw->super, NFP_NET_CFG_RXR_STATS(i) + 0x8);\n \t}\n \n \t/* Reading per TX ring stats */\n@@ -930,36 +931,36 @@ nfp_net_stats_reset(struct rte_eth_dev *dev)\n \t\t\tbreak;\n \n \t\thw->eth_stats_base.q_opackets[i] =\n-\t\t\t\tnn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));\n+\t\t\t\tnn_cfg_readq(&hw->super, NFP_NET_CFG_TXR_STATS(i));\n \n \t\thw->eth_stats_base.q_obytes[i] =\n-\t\t\t\tnn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);\n+\t\t\t\tnn_cfg_readq(&hw->super, NFP_NET_CFG_TXR_STATS(i) + 0x8);\n \t}\n \n \thw->eth_stats_base.ipackets =\n-\t\t\tnn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);\n+\t\t\tnn_cfg_readq(&hw->super, NFP_NET_CFG_STATS_RX_FRAMES);\n \n \thw->eth_stats_base.ibytes =\n-\t\t\tnn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);\n+\t\t\tnn_cfg_readq(&hw->super, NFP_NET_CFG_STATS_RX_OCTETS);\n \n \thw->eth_stats_base.opackets =\n-\t\t\tnn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);\n+\t\t\tnn_cfg_readq(&hw->super, NFP_NET_CFG_STATS_TX_FRAMES);\n \n \thw->eth_stats_base.obytes =\n-\t\t\tnn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);\n+\t\t\tnn_cfg_readq(&hw->super, NFP_NET_CFG_STATS_TX_OCTETS);\n \n \t/* Reading general device stats */\n \thw->eth_stats_base.ierrors =\n-\t\t\tnn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);\n+\t\t\tnn_cfg_readq(&hw->super, NFP_NET_CFG_STATS_RX_ERRORS);\n \n \thw->eth_stats_base.oerrors =\n-\t\t\tnn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);\n+\t\t\tnn_cfg_readq(&hw->super, NFP_NET_CFG_STATS_TX_ERRORS);\n \n \t/* RX ring mbuf allocation failures */\n \tdev->data->rx_mbuf_alloc_failed = 0;\n \n \thw->eth_stats_base.imissed =\n-\t\t\tnn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);\n+\t\t\tnn_cfg_readq(&hw->super, NFP_NET_CFG_STATS_RX_DISCARDS);\n \n \treturn 0;\n }\n@@ -1012,7 +1013,7 @@ nfp_net_xstats_value(const struct rte_eth_dev *dev,\n \tif (xstat.group == NFP_XSTAT_GROUP_MAC)\n \t\tvalue = nn_readq(hw->mac_stats + xstat.offset);\n \telse\n-\t\tvalue = nn_cfg_readq(hw, xstat.offset);\n+\t\tvalue = nn_cfg_readq(&hw->super, xstat.offset);\n \n \tif (raw)\n \t\treturn value;\n@@ -1320,8 +1321,8 @@ nfp_net_common_init(struct rte_pci_device *pci_dev,\n \thw->subsystem_device_id = pci_dev->id.subsystem_device_id;\n \thw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;\n \n-\thw->max_rx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_RXRINGS);\n-\thw->max_tx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_TXRINGS);\n+\thw->max_rx_queues = nn_cfg_readl(&hw->super, NFP_NET_CFG_MAX_RXRINGS);\n+\thw->max_tx_queues = nn_cfg_readl(&hw->super, NFP_NET_CFG_MAX_TXRINGS);\n \tif (hw->max_rx_queues == 0 || hw->max_tx_queues == 0) {\n \t\tPMD_INIT_LOG(ERR, \"Device %s can not be used, there are no valid queue \"\n \t\t\t\t\"pairs for use\", pci_dev->name);\n@@ -1336,9 +1337,9 @@ nfp_net_common_init(struct rte_pci_device *pci_dev,\n \t\treturn -ENODEV;\n \n \t/* Get some of the read-only fields from the config BAR */\n-\thw->super.cap = nn_cfg_readl(hw, NFP_NET_CFG_CAP);\n-\thw->cap_ext = nn_cfg_readl(hw, NFP_NET_CFG_CAP_WORD1);\n-\thw->max_mtu = nn_cfg_readl(hw, NFP_NET_CFG_MAX_MTU);\n+\thw->super.cap = nn_cfg_readl(&hw->super, NFP_NET_CFG_CAP);\n+\thw->cap_ext = nn_cfg_readl(&hw->super, NFP_NET_CFG_CAP_WORD1);\n+\thw->max_mtu = nn_cfg_readl(&hw->super, NFP_NET_CFG_MAX_MTU);\n \thw->flbufsz = DEFAULT_FLBUF_SIZE;\n \n \tnfp_net_init_metadata_format(hw);\n@@ -1347,7 +1348,7 @@ nfp_net_common_init(struct rte_pci_device *pci_dev,\n \tif (hw->ver.major < 2)\n \t\thw->rx_offset = NFP_NET_RX_OFFSET;\n \telse\n-\t\thw->rx_offset = nn_cfg_readl(hw, NFP_NET_CFG_RX_OFFSET_ADDR);\n+\t\thw->rx_offset = nn_cfg_readl(&hw->super, NFP_NET_CFG_RX_OFFSET_ADDR);\n \n \thw->super.ctrl = 0;\n \thw->stride_rx = stride;\n@@ -1389,7 +1390,7 @@ nfp_rx_queue_intr_enable(struct rte_eth_dev *dev,\n \trte_wmb();\n \n \thw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n-\tnn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id),\n+\tnn_cfg_writeb(&hw->super, NFP_NET_CFG_ICR(base + queue_id),\n \t\t\tNFP_NET_CFG_ICR_UNMASKED);\n \treturn 0;\n }\n@@ -1410,7 +1411,7 @@ nfp_rx_queue_intr_disable(struct rte_eth_dev *dev,\n \trte_wmb();\n \n \thw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n-\tnn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id), NFP_NET_CFG_ICR_RXTX);\n+\tnn_cfg_writeb(&hw->super, NFP_NET_CFG_ICR(base + queue_id), NFP_NET_CFG_ICR_RXTX);\n \n \treturn 0;\n }\n@@ -1457,7 +1458,7 @@ nfp_net_irq_unmask(struct rte_eth_dev *dev)\n \t\t/* If MSI-X auto-masking is used, clear the entry */\n \t\trte_intr_ack(pci_dev->intr_handle);\n \t} else {\n-\t\tnn_cfg_writeb(hw, NFP_NET_CFG_ICR(NFP_NET_IRQ_LSC_IDX),\n+\t\tnn_cfg_writeb(&hw->super, NFP_NET_CFG_ICR(NFP_NET_IRQ_LSC_IDX),\n \t\t\t\tNFP_NET_CFG_ICR_UNMASKED);\n \t}\n }\n@@ -1539,7 +1540,7 @@ nfp_net_dev_mtu_set(struct rte_eth_dev *dev,\n \t}\n \n \t/* Writing to configuration space */\n-\tnn_cfg_writel(hw, NFP_NET_CFG_MTU, mtu);\n+\tnn_cfg_writel(&hw->super, NFP_NET_CFG_MTU, mtu);\n \n \thw->mtu = mtu;\n \n@@ -1630,7 +1631,7 @@ nfp_net_rss_reta_write(struct rte_eth_dev *dev,\n \n \t\t/* If all 4 entries were set, don't need read RETA register */\n \t\tif (mask != 0xF)\n-\t\t\treta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + i);\n+\t\t\treta = nn_cfg_readl(&hw->super, NFP_NET_CFG_RSS_ITBL + i);\n \n \t\tfor (j = 0; j < 4; j++) {\n \t\t\tif ((mask & (0x1 << j)) == 0)\n@@ -1643,7 +1644,7 @@ nfp_net_rss_reta_write(struct rte_eth_dev *dev,\n \t\t\treta |= reta_conf[idx].reta[shift + j] << (8 * j);\n \t\t}\n \n-\t\tnn_cfg_writel(hw, NFP_NET_CFG_RSS_ITBL + (idx * 64) + shift, reta);\n+\t\tnn_cfg_writel(&hw->super, NFP_NET_CFG_RSS_ITBL + (idx * 64) + shift, reta);\n \t}\n \n \treturn 0;\n@@ -1713,7 +1714,7 @@ nfp_net_reta_query(struct rte_eth_dev *dev,\n \t\tif (mask == 0)\n \t\t\tcontinue;\n \n-\t\treta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + (idx * 64) + shift);\n+\t\treta = nn_cfg_readl(&hw->super, NFP_NET_CFG_RSS_ITBL + (idx * 64) + shift);\n \t\tfor (j = 0; j < 4; j++) {\n \t\t\tif ((mask & (0x1 << j)) == 0)\n \t\t\t\tcontinue;\n@@ -1741,7 +1742,7 @@ nfp_net_rss_hash_write(struct rte_eth_dev *dev,\n \t/* Writing the key byte by byte */\n \tfor (i = 0; i < rss_conf->rss_key_len; i++) {\n \t\tmemcpy(&key, &rss_conf->rss_key[i], 1);\n-\t\tnn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY + i, key);\n+\t\tnn_cfg_writeb(&hw->super, NFP_NET_CFG_RSS_KEY + i, key);\n \t}\n \n \trss_hf = rss_conf->rss_hf;\n@@ -1774,10 +1775,10 @@ nfp_net_rss_hash_write(struct rte_eth_dev *dev,\n \tcfg_rss_ctrl |= NFP_NET_CFG_RSS_TOEPLITZ;\n \n \t/* Configuring where to apply the RSS hash */\n-\tnn_cfg_writel(hw, NFP_NET_CFG_RSS_CTRL, cfg_rss_ctrl);\n+\tnn_cfg_writel(&hw->super, NFP_NET_CFG_RSS_CTRL, cfg_rss_ctrl);\n \n \t/* Writing the key size */\n-\tnn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY_SZ, rss_conf->rss_key_len);\n+\tnn_cfg_writeb(&hw->super, NFP_NET_CFG_RSS_KEY_SZ, rss_conf->rss_key_len);\n \n \treturn 0;\n }\n@@ -1835,7 +1836,7 @@ nfp_net_rss_hash_conf_get(struct rte_eth_dev *dev,\n \t\treturn -EINVAL;\n \n \trss_hf = rss_conf->rss_hf;\n-\tcfg_rss_ctrl = nn_cfg_readl(hw, NFP_NET_CFG_RSS_CTRL);\n+\tcfg_rss_ctrl = nn_cfg_readl(&hw->super, NFP_NET_CFG_RSS_CTRL);\n \n \tif ((cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4) != 0)\n \t\trss_hf |= RTE_ETH_RSS_IPV4;\n@@ -1865,11 +1866,11 @@ nfp_net_rss_hash_conf_get(struct rte_eth_dev *dev,\n \trss_conf->rss_hf = rss_hf;\n \n \t/* Reading the key size */\n-\trss_conf->rss_key_len = nn_cfg_readl(hw, NFP_NET_CFG_RSS_KEY_SZ);\n+\trss_conf->rss_key_len = nn_cfg_readl(&hw->super, NFP_NET_CFG_RSS_KEY_SZ);\n \n \t/* Reading the key byte a byte */\n \tfor (i = 0; i < rss_conf->rss_key_len; i++) {\n-\t\tkey = nn_cfg_readb(hw, NFP_NET_CFG_RSS_KEY + i);\n+\t\tkey = nn_cfg_readb(&hw->super, NFP_NET_CFG_RSS_KEY + i);\n \t\tmemcpy(&rss_conf->rss_key[i], &key, 1);\n \t}\n \n@@ -1983,13 +1984,13 @@ nfp_net_set_vxlan_port(struct nfp_net_hw *hw,\n \thw->vxlan_ports[idx] = port;\n \n \tfor (i = 0; i < NFP_NET_N_VXLAN_PORTS; i += 2) {\n-\t\tnn_cfg_writel(hw, NFP_NET_CFG_VXLAN_PORT + i * sizeof(port),\n+\t\tnn_cfg_writel(&hw->super, NFP_NET_CFG_VXLAN_PORT + i * sizeof(port),\n \t\t\t\t(hw->vxlan_ports[i + 1] << 16) | hw->vxlan_ports[i]);\n \t}\n \n \trte_spinlock_lock(&hw->reconfig_lock);\n \n-\tnn_cfg_writel(hw, NFP_NET_CFG_UPDATE, NFP_NET_CFG_UPDATE_VXLAN);\n+\tnn_cfg_writel(&hw->super, NFP_NET_CFG_UPDATE, NFP_NET_CFG_UPDATE_VXLAN);\n \trte_wmb();\n \n \tret = __nfp_net_reconfig(hw, NFP_NET_CFG_UPDATE_VXLAN);\n@@ -2048,7 +2049,7 @@ nfp_net_cfg_read_version(struct nfp_net_hw *hw)\n \t\tstruct nfp_net_fw_ver split;\n \t} version;\n \n-\tversion.whole = nn_cfg_readl(hw, NFP_NET_CFG_VERSION);\n+\tversion.whole = nn_cfg_readl(&hw->super, NFP_NET_CFG_VERSION);\n \thw->ver = version.split;\n }\n \ndiff --git a/drivers/net/nfp/nfp_net_common.h b/drivers/net/nfp/nfp_net_common.h\nindex 375e26bfc2..6576769214 100644\n--- a/drivers/net/nfp/nfp_net_common.h\n+++ b/drivers/net/nfp/nfp_net_common.h\n@@ -246,63 +246,63 @@ nn_writeq(uint64_t val,\n }\n \n static inline uint8_t\n-nn_cfg_readb(struct nfp_net_hw *hw,\n+nn_cfg_readb(struct nfp_hw *hw,\n \t\tuint32_t off)\n {\n-\treturn nn_readb(hw->super.ctrl_bar + off);\n+\treturn nn_readb(hw->ctrl_bar + off);\n }\n \n static inline void\n-nn_cfg_writeb(struct nfp_net_hw *hw,\n+nn_cfg_writeb(struct nfp_hw *hw,\n \t\tuint32_t off,\n \t\tuint8_t val)\n {\n-\tnn_writeb(val, hw->super.ctrl_bar + off);\n+\tnn_writeb(val, hw->ctrl_bar + off);\n }\n \n static inline uint16_t\n-nn_cfg_readw(struct nfp_net_hw *hw,\n+nn_cfg_readw(struct nfp_hw *hw,\n \t\tuint32_t off)\n {\n-\treturn rte_le_to_cpu_16(nn_readw(hw->super.ctrl_bar + off));\n+\treturn rte_le_to_cpu_16(nn_readw(hw->ctrl_bar + off));\n }\n \n static inline void\n-nn_cfg_writew(struct nfp_net_hw *hw,\n+nn_cfg_writew(struct nfp_hw *hw,\n \t\tuint32_t off,\n \t\tuint16_t val)\n {\n-\tnn_writew(rte_cpu_to_le_16(val), hw->super.ctrl_bar + off);\n+\tnn_writew(rte_cpu_to_le_16(val), hw->ctrl_bar + off);\n }\n \n static inline uint32_t\n-nn_cfg_readl(struct nfp_net_hw *hw,\n+nn_cfg_readl(struct nfp_hw *hw,\n \t\tuint32_t off)\n {\n-\treturn rte_le_to_cpu_32(nn_readl(hw->super.ctrl_bar + off));\n+\treturn rte_le_to_cpu_32(nn_readl(hw->ctrl_bar + off));\n }\n \n static inline void\n-nn_cfg_writel(struct nfp_net_hw *hw,\n+nn_cfg_writel(struct nfp_hw *hw,\n \t\tuint32_t off,\n \t\tuint32_t val)\n {\n-\tnn_writel(rte_cpu_to_le_32(val), hw->super.ctrl_bar + off);\n+\tnn_writel(rte_cpu_to_le_32(val), hw->ctrl_bar + off);\n }\n \n static inline uint64_t\n-nn_cfg_readq(struct nfp_net_hw *hw,\n+nn_cfg_readq(struct nfp_hw *hw,\n \t\tuint32_t off)\n {\n-\treturn rte_le_to_cpu_64(nn_readq(hw->super.ctrl_bar + off));\n+\treturn rte_le_to_cpu_64(nn_readq(hw->ctrl_bar + off));\n }\n \n static inline void\n-nn_cfg_writeq(struct nfp_net_hw *hw,\n+nn_cfg_writeq(struct nfp_hw *hw,\n \t\tuint32_t off,\n \t\tuint64_t val)\n {\n-\tnn_writeq(rte_cpu_to_le_64(val), hw->super.ctrl_bar + off);\n+\tnn_writeq(rte_cpu_to_le_64(val), hw->ctrl_bar + off);\n }\n \n /**\ndiff --git a/drivers/net/nfp/nfp_rxtx.c b/drivers/net/nfp/nfp_rxtx.c\nindex a9dd464a6a..f17cc13cc1 100644\n--- a/drivers/net/nfp/nfp_rxtx.c\n+++ b/drivers/net/nfp/nfp_rxtx.c\n@@ -925,8 +925,8 @@ nfp_net_rx_queue_setup(struct rte_eth_dev *dev,\n \t * Telling the HW about the physical address of the RX ring and number\n \t * of descriptors in log2 format.\n \t */\n-\tnn_cfg_writeq(hw, NFP_NET_CFG_RXR_ADDR(queue_idx), rxq->dma);\n-\tnn_cfg_writeb(hw, NFP_NET_CFG_RXR_SZ(queue_idx), rte_log2_u32(nb_desc));\n+\tnn_cfg_writeq(&hw->super, NFP_NET_CFG_RXR_ADDR(queue_idx), rxq->dma);\n+\tnn_cfg_writeb(&hw->super, NFP_NET_CFG_RXR_SZ(queue_idx), rte_log2_u32(nb_desc));\n \n \treturn 0;\n }\n",
    "prefixes": [
        "09/25"
    ]
}