Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/132704/?format=api
http://patchwork.dpdk.org/api/patches/132704/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20231017054545.1692509-15-chaoyong.he@corigine.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20231017054545.1692509-15-chaoyong.he@corigine.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20231017054545.1692509-15-chaoyong.he@corigine.com", "date": "2023-10-17T05:45:34", "name": "[14/25] drivers: add the nfp common module", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "947dc5d2af01c8de01a1e7322aa3ecc74e6820fa", "submitter": { "id": 2554, "url": "http://patchwork.dpdk.org/api/people/2554/?format=api", "name": "Chaoyong He", "email": "chaoyong.he@corigine.com" }, "delegate": { "id": 319, "url": "http://patchwork.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20231017054545.1692509-15-chaoyong.he@corigine.com/mbox/", "series": [ { "id": 29865, "url": "http://patchwork.dpdk.org/api/series/29865/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=29865", "date": "2023-10-17T05:45:20", "name": "add the NFP vDPA PMD", "version": 1, "mbox": "http://patchwork.dpdk.org/series/29865/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/132704/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/132704/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 729FE43186;\n\tTue, 17 Oct 2023 07:48:07 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 3BB8241157;\n\tTue, 17 Oct 2023 07:46:55 +0200 (CEST)", "from NAM12-MW2-obe.outbound.protection.outlook.com\n (mail-mw2nam12on2133.outbound.protection.outlook.com [40.107.244.133])\n by mails.dpdk.org (Postfix) with ESMTP id 77E2A4113D\n for <dev@dpdk.org>; Tue, 17 Oct 2023 07:46:54 +0200 (CEST)", "from PH0PR13MB5568.namprd13.prod.outlook.com (2603:10b6:510:12b::16)\n by MW5PR13MB5904.namprd13.prod.outlook.com (2603:10b6:303:1ce::13)\n with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6863.45; Tue, 17 Oct\n 2023 05:46:52 +0000", "from PH0PR13MB5568.namprd13.prod.outlook.com\n ([fe80::b070:92e1:931e:fee7]) by PH0PR13MB5568.namprd13.prod.outlook.com\n ([fe80::b070:92e1:931e:fee7%4]) with mapi id 15.20.6863.047; Tue, 17 Oct 2023\n 05:46:52 +0000" ], "ARC-Seal": "i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none;\n b=dCEWnzkYRGpQ7qL54vepR3jyPkEm5ca+vnRQfUHw3JB7kkMsR+oPpmrCI92s8WyEtBZPOyGNQbb7/dG+iwcqDFWfrQ+RUlsZd3MJ/ev2PSjGUUgzhHAGCcE0BNAw1dJEUT5yStj5obtBklpPEopGub6Vj1gyCMCEcVsCueiOvTg1T60eN56qfYTDuh7wqnkknnXRyypyYHit5iWKqb6+rEKxY2hrw20n/pqzwNcK/MupBEuDb0j3F8/3mfzIW5vDODTxpmn6xhNyNmTaDdZJ2vzLmbXVT/JHqnFTjWKW++bITFG86Due/E47BfTZaPGY4Q6kGzFEkW50TUs5+JDwqg==", "ARC-Message-Signature": "i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector9901;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=bWMRq19mObk9qVWmYCDmQSjfB+nDWHAjj8DO+1drT7I=;\n b=PSCsAZaTcx0RPd9I3cW5vOKxmonvogXCDixEmOJ1skziEKx4q4+712cpvlQY4pP2G7RNMSmsfTmy6HOcFai+/XKyAOap4L9pvOtDselqaP/WzamK10MvtoBfH8RdyfWfcg14x/9zTp4QT6zMNSZhE6RseoggskGM2R1QaH561if0elZUIOTrHasT3o9qng53WkN2PHTd2h7L4zp4FGrLBgKDtYGp5s11UplhnUSE2+G/mN81wvil9p2/2MePuiiPNN1MN8OQ3rAWCKAp9fOku57XxIn9yHjQGCwLwzO05NzPAqEkGEbMX9HGX5RTz/KmA1U0318UraZ69uCq1t14Pw==", "ARC-Authentication-Results": "i=1; mx.microsoft.com 1; spf=pass\n smtp.mailfrom=corigine.com; dmarc=pass action=none header.from=corigine.com;\n dkim=pass header.d=corigine.com; arc=none", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=corigine.onmicrosoft.com; s=selector2-corigine-onmicrosoft-com;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=bWMRq19mObk9qVWmYCDmQSjfB+nDWHAjj8DO+1drT7I=;\n b=pjsjDpC9iv9fR4bg+MVEusck4wqd6MPdXVKIn8pGgJKuOoJCf/hXK1HHLwZfWKsiPJ5AYwUvD1I7MdTw715XKCBPT8A3/LoE8JDlLXO9CwOsuDGY6NweBnIIDxku50rLi75zaGY6rAL0sN8UsOu8/DoTYNPEq6lfxEnlZ2w2AsQ=", "Authentication-Results": "dkim=none (message not signed)\n header.d=none;dmarc=none action=none header.from=corigine.com;", "From": "Chaoyong He <chaoyong.he@corigine.com>", "To": "dev@dpdk.org", "Cc": "oss-drivers@corigine.com, Chaoyong He <chaoyong.he@corigine.com>,\n Long Wu <long.wu@corigine.com>, Peng Zhang <peng.zhang@corigine.com>", "Subject": "[PATCH 14/25] drivers: add the nfp common module", "Date": "Tue, 17 Oct 2023 13:45:34 +0800", "Message-Id": "<20231017054545.1692509-15-chaoyong.he@corigine.com>", "X-Mailer": "git-send-email 2.39.1", "In-Reply-To": "<20231017054545.1692509-1-chaoyong.he@corigine.com>", "References": "<20231017054545.1692509-1-chaoyong.he@corigine.com>", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-ClientProxiedBy": "PH7PR17CA0069.namprd17.prod.outlook.com\n (2603:10b6:510:325::29) To PH0PR13MB5568.namprd13.prod.outlook.com\n (2603:10b6:510:12b::16)", "MIME-Version": "1.0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "PH0PR13MB5568:EE_|MW5PR13MB5904:EE_", "X-MS-Office365-Filtering-Correlation-Id": "3feec343-0bb7-4b7b-a67b-08dbced47502", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n GTqm0ZjUoo7u92HAFQ0ZTepthJsFNI3SZmQEAoHwmu51qtpay97RuV8nuWOXh5b5M97Qv+kIwK7aysP7ZP4x3c18idq77418gbdbgqwlGcGH022juqWTOMvtW++sZgcELYHF0oKaZVLL9qLvq7ocoLR/cNZHRLy29eJPgaWf/ODh5+/6erbKj2KEcEyjB8eognzII3y0DxSpK9d8YOAmBQFofEKayG0fJtOutoauM0QBrhRMeXkFEcnmghpzWBVX2sBStNeO46zLXuOf7RcH1uYdAabnYe9XSlhH7Mtyc3NTlcrNHUqE7nxZwtWrMlwM51XgY3YKafHVsTU0jaARrXGt1Yhzkc5dq2x9J5lIor8IHolvWVbbMsizdL43HQ09dw3cZuf/f5iiPsFYNk2opymc2faLX4ZgM9rDqcxRkqHq850ta9ZmKs7ftC2IksY8hOXJRPMRvGeNKPb6cFZ1TyT/YXtUwQ3xHWAU7TsBoAn0MMxzlRDRrUmMIrFC52EJxOZpeWBmZQxdZOlBXhiAUrWLBtn4IsxkUD2f2S6n6Gbv0WprDUCWaInLG7+1pdUa/XlCzty59QhqVe2rkvVW6L5LSh67bCoXLxRo95O20kpEygezcafVVInhrKzkgsjVWywapL58fYneNjWmtsTQP4i/8PBlxF+BcVetVfHQ/4k=", "X-Forefront-Antispam-Report": "CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:;\n IPV:NLI; SFV:NSPM; H:PH0PR13MB5568.namprd13.prod.outlook.com; PTR:; CAT:NONE;\n SFS:(13230031)(136003)(366004)(376002)(39830400003)(346002)(396003)(230922051799003)(186009)(1800799009)(451199024)(64100799003)(2906002)(5660300002)(8936002)(8676002)(30864003)(83380400001)(66556008)(66476007)(6916009)(316002)(66946007)(54906003)(41300700001)(478600001)(4326008)(6486002)(44832011)(6666004)(6512007)(6506007)(107886003)(38350700005)(2616005)(1076003)(26005)(36756003)(38100700002)(52116002)(86362001);\n DIR:OUT; SFP:1102;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n 4zmYcjsjmZoWUcRLTIE7dgNyPFA1h4XN+MWtR19FATxdgnVr8PBg1Zfohs2eQhY+fDtXJrZga3Kf5WCCkMqPBJBhTqro2szIRYv1mMEvhhm3ey0Gh+/1V7/SSESkNk8LAwwf5a8pVpHXHqdiAh/bLxA6SngCtcF5cwQC+CI6pXBJj3j6dkrxcDsCjiZdkeVcZQxX/n8JE6v2v947rEBfY4CPfXMNgWiE/0bK8UyRmVfNDPjFVjM840u54u9sZoolLT27O+PRBJWTyiP2eEHl/WPNAklaxOQARA8OPotmGK6f1uNvbxZo2Hv0wxNshFFwdBQRsx29n8aJdEjz9gD/c9oB1vCByDUz3HJVhDGc+rJ55/VzX1WCqrql9CnakoRPBiDuj/bhnm8t3EJeTkboFlO5q7qCPBBSZIpE44CWcs1q6PnD91o/ZcduHTuBnF9VBxn9+14rx5AZ1GreqxjwsvetoVy/L5hbBkQsah/m5jMy2PLzHl+aGclkxh/asjMtxmBkedTn2pc52aj4I0a/C+kgv/JNeuQXZIudHZ0a8ZiNNQ+kQN8QHgCwIkYoKN1T7Krulz8FZClBxt17HZTy03j5VQcurBBaUJcXjePvt0sfBCcvq7xQoLswmQXTJWeyQHVJkVI7c4S8BjKsgPKiChG1JeRJ21IZm3/kMxm2Nxdn2JA0166IGZEiK/D+njwKFtZ1/QdldRboexP53GUK7oqh1kpj2chrZBvxWbQGJGQJ5UNZgWcogDsMDgt+Xvti6f24N4dGfEZUuyHtRW4ynxFiP2RIA5zN8iztG5IxMoAghGMHZuKmD0lWs+v02Qi4rJ1oCvWlG9mK3auAOU/8GlF8hQcKbfxVYPPSmSa5LeRFN6fgYZv8uOsOha6dXU+BZHxWGcFeSjhios0KhLM1wWeiLaQicLVkJBUEE30f6Pbvuz1VZlhbrrO8BZ7IDurhnN9vBMuWbUa3iUMF3GpdGW8/5YB2qr2bLLmv3veNUq9PXxZbEiDJvMg1j9cy2a4zO6133FotdT7fJ+0nFRTh6vAHJrJGHUtUWYiMLFu4zqdBbd//m+3REM64XnpKFEKRLq+nnpKB1x0QR2u0QsWKZrbsfSXokwaN7I2wjca0ePdnqiVs40muS24aI/g6c6wpngnUDSFMowsoHJfShdbzjdrolD0bw+OG8vYDoc74hjhFegJy4p9Y4BkGm6JwRRRtck1C4Hy/Sq+CswizBkgKgRzwcz7kTOg3VIUeVqA2XfXLeIdR0CS3RZHS42LxwPDJ4yGwddkjLiFN4XmLOwMDm0E2PPkyhEARQjae/difb0lna4jJTkEoCudktg8PJkkZhQR8bw3QChUsUSReEIaCEeIXMyTX2Ms2BYxjnAyawqH2ErtZg0Z+t4bysZLk2V01OAbqPklNUOLYROYyXAD4flPam2upyoky725ImFBok7DaQkMifqBrJdyU8uiZXuhgy7p1sjlvmG1TTrElOgt63cE8rtKATM37SW5+jV5bQAHP9+btGsDmIwd7Jjx4zFNT3xeVU0HKkmnd7TrtnMsM6E9a9xZzdIXcz8Ot48ND01tNq+juS2z1CzFYEzki/guaZpNazWIX17p26UBLADXvlA==", "X-OriginatorOrg": "corigine.com", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 3feec343-0bb7-4b7b-a67b-08dbced47502", "X-MS-Exchange-CrossTenant-AuthSource": "PH0PR13MB5568.namprd13.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Internal", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "17 Oct 2023 05:46:52.1224 (UTC)", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "fe128f2c-073b-4c20-818e-7246a585940c", "X-MS-Exchange-CrossTenant-MailboxType": "HOSTED", "X-MS-Exchange-CrossTenant-UserPrincipalName": "\n 2SZvA6aeD/IUhXmLLLmPV0AEAcQWYHq+rikDJW0NnYEsEg/vfVrqyjrke9tqEbOsscSMvbVBVA1nn6059vGk47PkE4RmuVZqUkhfzodF2Ds=", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "MW5PR13MB5904", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Add the nfp common module in the nfp common library.\n\nSigned-off-by: Chaoyong He <chaoyong.he@corigine.com>\nReviewed-by: Long Wu <long.wu@corigine.com>\nReviewed-by: Peng Zhang <peng.zhang@corigine.com>\n---\n drivers/common/nfp/meson.build | 3 +-\n drivers/common/nfp/nfp_common.c | 133 ++++++++++++++++++\n drivers/common/nfp/nfp_common.h | 227 +++++++++++++++++++++++++++++++\n drivers/common/nfp/version.map | 5 +\n drivers/net/nfp/nfp_ethdev.c | 4 +-\n drivers/net/nfp/nfp_ethdev_vf.c | 16 +--\n drivers/net/nfp/nfp_net_common.c | 109 +--------------\n drivers/net/nfp/nfp_net_common.h | 203 +--------------------------\n 8 files changed, 373 insertions(+), 327 deletions(-)\n create mode 100644 drivers/common/nfp/nfp_common.c\n create mode 100644 drivers/common/nfp/nfp_common.h", "diff": "diff --git a/drivers/common/nfp/meson.build b/drivers/common/nfp/meson.build\nindex 45871dfe35..727d21e00b 100644\n--- a/drivers/common/nfp/meson.build\n+++ b/drivers/common/nfp/meson.build\n@@ -6,9 +6,10 @@ if not is_linux or not dpdk_conf.get('RTE_ARCH_64')\n reason = 'only supported on 64-bit Linux'\n endif\n \n-deps += ['bus_pci']\n+deps += ['bus_pci', 'net']\n \n sources = files(\n+ 'nfp_common.c',\n 'nfp_common_log.c',\n 'nfp_common_pci.c',\n )\ndiff --git a/drivers/common/nfp/nfp_common.c b/drivers/common/nfp/nfp_common.c\nnew file mode 100644\nindex 0000000000..00dad4736e\n--- /dev/null\n+++ b/drivers/common/nfp/nfp_common.c\n@@ -0,0 +1,133 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright (c) 2023 Corigine, Inc.\n+ * All rights reserved.\n+ */\n+\n+#include \"nfp_common.h\"\n+\n+#include \"nfp_common_log.h\"\n+\n+/*\n+ * This is used by the reconfig protocol. It sets the maximum time waiting in\n+ * milliseconds before a reconfig timeout happens.\n+ */\n+#define NFP_NET_POLL_TIMEOUT 5000\n+\n+int\n+nfp_reconfig_real(struct nfp_hw *hw,\n+\t\tuint32_t update)\n+{\n+\tuint32_t cnt;\n+\tuint32_t new;\n+\tstruct timespec wait;\n+\n+\tPMD_DRV_LOG(DEBUG, \"Writing to the configuration queue (%p)...\",\n+\t\t\thw->qcp_cfg);\n+\n+\tif (hw->qcp_cfg == NULL) {\n+\t\tPMD_DRV_LOG(ERR, \"Bad configuration queue pointer\");\n+\t\treturn -ENXIO;\n+\t}\n+\n+\tnfp_qcp_ptr_add(hw->qcp_cfg, NFP_QCP_WRITE_PTR, 1);\n+\n+\twait.tv_sec = 0;\n+\twait.tv_nsec = 1000000; /* 1ms */\n+\n+\tPMD_DRV_LOG(DEBUG, \"Polling for update ack...\");\n+\n+\t/* Poll update field, waiting for NFP to ack the config */\n+\tfor (cnt = 0; ; cnt++) {\n+\t\tnew = nn_cfg_readl(hw, NFP_NET_CFG_UPDATE);\n+\t\tif (new == 0)\n+\t\t\tbreak;\n+\n+\t\tif ((new & NFP_NET_CFG_UPDATE_ERR) != 0) {\n+\t\t\tPMD_DRV_LOG(ERR, \"Reconfig error: %#08x\", new);\n+\t\t\treturn -1;\n+\t\t}\n+\n+\t\tif (cnt >= NFP_NET_POLL_TIMEOUT) {\n+\t\t\tPMD_DRV_LOG(ERR, \"Reconfig timeout for %#08x after %u ms\",\n+\t\t\t\t\tupdate, cnt);\n+\t\t\treturn -EIO;\n+\t\t}\n+\n+\t\tnanosleep(&wait, 0); /* waiting for a 1ms */\n+\t}\n+\n+\tPMD_DRV_LOG(DEBUG, \"Ack DONE\");\n+\treturn 0;\n+}\n+\n+/**\n+ * Reconfigure the NIC.\n+ *\n+ * Write the update word to the BAR and ping the reconfig queue. Then poll\n+ * until the firmware has acknowledged the update by zeroing the update word.\n+ *\n+ * @param hw\n+ * Device to reconfigure.\n+ * @param ctrl\n+ * The value for the ctrl field in the BAR config.\n+ * @param update\n+ * The value for the update field in the BAR config.\n+ *\n+ * @return\n+ * - (0) if OK to reconfigure the device.\n+ * - (-EIO) if I/O err and fail to reconfigure the device.\n+ */\n+int\n+nfp_reconfig(struct nfp_hw *hw,\n+\t\tuint32_t ctrl,\n+\t\tuint32_t update)\n+{\n+\tint ret;\n+\n+\trte_spinlock_lock(&hw->reconfig_lock);\n+\n+\tnn_cfg_writel(hw, NFP_NET_CFG_CTRL, ctrl);\n+\tnn_cfg_writel(hw, NFP_NET_CFG_UPDATE, update);\n+\n+\trte_wmb();\n+\n+\tret = nfp_reconfig_real(hw, update);\n+\n+\trte_spinlock_unlock(&hw->reconfig_lock);\n+\n+\tif (ret != 0) {\n+\t\tPMD_DRV_LOG(ERR, \"Error nfp net reconfig: ctrl=%#08x update=%#08x\",\n+\t\t\t\tctrl, update);\n+\t\treturn -EIO;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+void\n+nfp_read_mac(struct nfp_hw *hw)\n+{\n+\tuint32_t tmp;\n+\n+\ttmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR));\n+\tmemcpy(&hw->mac_addr.addr_bytes[0], &tmp, 4);\n+\n+\ttmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR + 4));\n+\tmemcpy(&hw->mac_addr.addr_bytes[4], &tmp, 2);\n+}\n+\n+void\n+nfp_write_mac(struct nfp_hw *hw,\n+\t\tuint8_t *mac)\n+{\n+\tuint32_t mac0;\n+\tuint16_t mac1;\n+\n+\tmac0 = *(uint32_t *)mac;\n+\tnn_writel(rte_cpu_to_be_32(mac0), hw->ctrl_bar + NFP_NET_CFG_MACADDR);\n+\n+\tmac += 4;\n+\tmac1 = *(uint16_t *)mac;\n+\tnn_writew(rte_cpu_to_be_16(mac1),\n+\t\t\thw->ctrl_bar + NFP_NET_CFG_MACADDR + 6);\n+}\ndiff --git a/drivers/common/nfp/nfp_common.h b/drivers/common/nfp/nfp_common.h\nnew file mode 100644\nindex 0000000000..c3645b6ec5\n--- /dev/null\n+++ b/drivers/common/nfp/nfp_common.h\n@@ -0,0 +1,227 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright (c) 2023 Corigine, Inc.\n+ * All rights reserved.\n+ */\n+\n+#ifndef __NFP_COMMON_H__\n+#define __NFP_COMMON_H__\n+\n+#include <rte_byteorder.h>\n+#include <rte_ether.h>\n+#include <rte_io.h>\n+#include <rte_spinlock.h>\n+\n+#include \"nfp_common_ctrl.h\"\n+\n+#define NFP_QCP_QUEUE_ADDR_SZ (0x800)\n+\n+/* Macros for accessing the Queue Controller Peripheral 'CSRs' */\n+#define NFP_QCP_QUEUE_OFF(_x) ((_x) * 0x800)\n+#define NFP_QCP_QUEUE_ADD_RPTR 0x0000\n+#define NFP_QCP_QUEUE_ADD_WPTR 0x0004\n+#define NFP_QCP_QUEUE_STS_LO 0x0008\n+#define NFP_QCP_QUEUE_STS_LO_READPTR_MASK (0x3ffff)\n+#define NFP_QCP_QUEUE_STS_HI 0x000c\n+#define NFP_QCP_QUEUE_STS_HI_WRITEPTR_MASK (0x3ffff)\n+\n+/* Read or Write Pointer of a queue */\n+enum nfp_qcp_ptr {\n+\tNFP_QCP_READ_PTR = 0,\n+\tNFP_QCP_WRITE_PTR\n+};\n+\n+struct nfp_hw {\n+\tuint8_t *ctrl_bar;\n+\tuint8_t *qcp_cfg;\n+\tuint32_t cap;\n+\tuint32_t ctrl; /**< Current values for control */\n+\trte_spinlock_t reconfig_lock;\n+\tstruct rte_ether_addr mac_addr;\n+};\n+\n+static inline uint8_t\n+nn_readb(volatile const void *addr)\n+{\n+\treturn rte_read8(addr);\n+}\n+\n+static inline void\n+nn_writeb(uint8_t val,\n+\t\tvolatile void *addr)\n+{\n+\trte_write8(val, addr);\n+}\n+\n+static inline uint32_t\n+nn_readl(volatile const void *addr)\n+{\n+\treturn rte_read32(addr);\n+}\n+\n+static inline void\n+nn_writel(uint32_t val,\n+\t\tvolatile void *addr)\n+{\n+\trte_write32(val, addr);\n+}\n+\n+static inline uint16_t\n+nn_readw(volatile const void *addr)\n+{\n+\treturn rte_read16(addr);\n+}\n+\n+static inline void\n+nn_writew(uint16_t val,\n+\t\tvolatile void *addr)\n+{\n+\trte_write16(val, addr);\n+}\n+\n+static inline uint64_t\n+nn_readq(volatile void *addr)\n+{\n+\tuint32_t low;\n+\tuint32_t high;\n+\tconst volatile uint32_t *p = addr;\n+\n+\thigh = nn_readl((volatile const void *)(p + 1));\n+\tlow = nn_readl((volatile const void *)p);\n+\n+\treturn low + ((uint64_t)high << 32);\n+}\n+\n+static inline void\n+nn_writeq(uint64_t val,\n+\t\tvolatile void *addr)\n+{\n+\tnn_writel(val >> 32, (volatile char *)addr + 4);\n+\tnn_writel(val, addr);\n+}\n+\n+static inline uint8_t\n+nn_cfg_readb(struct nfp_hw *hw,\n+\t\tuint32_t off)\n+{\n+\treturn nn_readb(hw->ctrl_bar + off);\n+}\n+\n+static inline void\n+nn_cfg_writeb(struct nfp_hw *hw,\n+\t\tuint32_t off,\n+\t\tuint8_t val)\n+{\n+\tnn_writeb(val, hw->ctrl_bar + off);\n+}\n+\n+static inline uint16_t\n+nn_cfg_readw(struct nfp_hw *hw,\n+\t\tuint32_t off)\n+{\n+\treturn rte_le_to_cpu_16(nn_readw(hw->ctrl_bar + off));\n+}\n+\n+static inline void\n+nn_cfg_writew(struct nfp_hw *hw,\n+\t\tuint32_t off,\n+\t\tuint16_t val)\n+{\n+\tnn_writew(rte_cpu_to_le_16(val), hw->ctrl_bar + off);\n+}\n+\n+static inline uint32_t\n+nn_cfg_readl(struct nfp_hw *hw,\n+\t\tuint32_t off)\n+{\n+\treturn rte_le_to_cpu_32(nn_readl(hw->ctrl_bar + off));\n+}\n+\n+static inline void\n+nn_cfg_writel(struct nfp_hw *hw,\n+\t\tuint32_t off,\n+\t\tuint32_t val)\n+{\n+\tnn_writel(rte_cpu_to_le_32(val), hw->ctrl_bar + off);\n+}\n+\n+static inline uint64_t\n+nn_cfg_readq(struct nfp_hw *hw,\n+\t\tuint32_t off)\n+{\n+\treturn rte_le_to_cpu_64(nn_readq(hw->ctrl_bar + off));\n+}\n+\n+static inline void\n+nn_cfg_writeq(struct nfp_hw *hw,\n+\t\tuint32_t off,\n+\t\tuint64_t val)\n+{\n+\tnn_writeq(rte_cpu_to_le_64(val), hw->ctrl_bar + off);\n+}\n+\n+/**\n+ * Add the value to the selected pointer of a queue.\n+ *\n+ * @param queue\n+ * Base address for queue structure\n+ * @param ptr\n+ * Add to the read or write pointer\n+ * @param val\n+ * Value to add to the queue pointer\n+ */\n+static inline void\n+nfp_qcp_ptr_add(uint8_t *queue,\n+\t\tenum nfp_qcp_ptr ptr,\n+\t\tuint32_t val)\n+{\n+\tuint32_t off;\n+\n+\tif (ptr == NFP_QCP_READ_PTR)\n+\t\toff = NFP_QCP_QUEUE_ADD_RPTR;\n+\telse\n+\t\toff = NFP_QCP_QUEUE_ADD_WPTR;\n+\n+\tnn_writel(rte_cpu_to_le_32(val), queue + off);\n+}\n+\n+/**\n+ * Read the current read/write pointer value for a queue.\n+ *\n+ * @param queue\n+ * Base address for queue structure\n+ * @param ptr\n+ * Read or Write pointer\n+ */\n+static inline uint32_t\n+nfp_qcp_read(uint8_t *queue,\n+\t\tenum nfp_qcp_ptr ptr)\n+{\n+\tuint32_t off;\n+\tuint32_t val;\n+\n+\tif (ptr == NFP_QCP_READ_PTR)\n+\t\toff = NFP_QCP_QUEUE_STS_LO;\n+\telse\n+\t\toff = NFP_QCP_QUEUE_STS_HI;\n+\n+\tval = rte_cpu_to_le_32(nn_readl(queue + off));\n+\n+\tif (ptr == NFP_QCP_READ_PTR)\n+\t\treturn val & NFP_QCP_QUEUE_STS_LO_READPTR_MASK;\n+\telse\n+\t\treturn val & NFP_QCP_QUEUE_STS_HI_WRITEPTR_MASK;\n+}\n+\n+__rte_internal\n+int nfp_reconfig_real(struct nfp_hw *hw, uint32_t update);\n+\n+__rte_internal\n+int nfp_reconfig(struct nfp_hw *hw, uint32_t ctrl, uint32_t update);\n+\n+__rte_internal\n+void nfp_read_mac(struct nfp_hw *hw);\n+\n+__rte_internal\n+void nfp_write_mac(struct nfp_hw *hw, uint8_t *mac);\n+\n+#endif/* __NFP_COMMON_H__ */\ndiff --git a/drivers/common/nfp/version.map b/drivers/common/nfp/version.map\nindex 25e48c39d6..56db63f29c 100644\n--- a/drivers/common/nfp/version.map\n+++ b/drivers/common/nfp/version.map\n@@ -3,5 +3,10 @@ INTERNAL {\n \n \tnfp_class_driver_register;\n \n+\tnfp_reconfig;\n+\tnfp_reconfig_real;\n+\tnfp_read_mac;\n+\tnfp_write_mac;\n+\n \tlocal: *;\n };\ndiff --git a/drivers/net/nfp/nfp_ethdev.c b/drivers/net/nfp/nfp_ethdev.c\nindex c6147ef01e..7b4439585b 100644\n--- a/drivers/net/nfp/nfp_ethdev.c\n+++ b/drivers/net/nfp/nfp_ethdev.c\n@@ -599,13 +599,13 @@ nfp_net_init(struct rte_eth_dev *eth_dev)\n \t}\n \n \tnfp_net_pf_read_mac(app_fw_nic, port);\n-\tnfp_net_write_mac(hw, &hw->mac_addr.addr_bytes[0]);\n+\tnfp_write_mac(hw, &hw->mac_addr.addr_bytes[0]);\n \n \tif (rte_is_valid_assigned_ether_addr(&hw->mac_addr) == 0) {\n \t\tPMD_INIT_LOG(INFO, \"Using random mac address for port %d\", port);\n \t\t/* Using random mac addresses for VFs */\n \t\trte_eth_random_addr(&hw->mac_addr.addr_bytes[0]);\n-\t\tnfp_net_write_mac(hw, &hw->mac_addr.addr_bytes[0]);\n+\t\tnfp_write_mac(hw, &hw->mac_addr.addr_bytes[0]);\n \t}\n \n \t/* Copying mac address to DPDK eth_dev struct */\ndiff --git a/drivers/net/nfp/nfp_ethdev_vf.c b/drivers/net/nfp/nfp_ethdev_vf.c\nindex 049728d30c..b9cfb48021 100644\n--- a/drivers/net/nfp/nfp_ethdev_vf.c\n+++ b/drivers/net/nfp/nfp_ethdev_vf.c\n@@ -15,18 +15,6 @@\n #include \"nfp_logs.h\"\n #include \"nfp_net_common.h\"\n \n-static void\n-nfp_netvf_read_mac(struct nfp_hw *hw)\n-{\n-\tuint32_t tmp;\n-\n-\ttmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR));\n-\tmemcpy(&hw->mac_addr.addr_bytes[0], &tmp, 4);\n-\n-\ttmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR + 4));\n-\tmemcpy(&hw->mac_addr.addr_bytes[4], &tmp, 2);\n-}\n-\n static int\n nfp_netvf_start(struct rte_eth_dev *dev)\n {\n@@ -334,12 +322,12 @@ nfp_netvf_init(struct rte_eth_dev *eth_dev)\n \t\tgoto dev_err_ctrl_map;\n \t}\n \n-\tnfp_netvf_read_mac(hw);\n+\tnfp_read_mac(hw);\n \tif (rte_is_valid_assigned_ether_addr(&hw->mac_addr) == 0) {\n \t\tPMD_INIT_LOG(INFO, \"Using random mac address for port %hu\", port);\n \t\t/* Using random mac addresses for VFs */\n \t\trte_eth_random_addr(&hw->mac_addr.addr_bytes[0]);\n-\t\tnfp_net_write_mac(hw, &hw->mac_addr.addr_bytes[0]);\n+\t\tnfp_write_mac(hw, &hw->mac_addr.addr_bytes[0]);\n \t}\n \n \t/* Copying mac address to DPDK eth_dev struct */\ndiff --git a/drivers/net/nfp/nfp_net_common.c b/drivers/net/nfp/nfp_net_common.c\nindex 22222a9773..6d525648eb 100644\n--- a/drivers/net/nfp/nfp_net_common.c\n+++ b/drivers/net/nfp/nfp_net_common.c\n@@ -198,97 +198,6 @@ nfp_net_notify_port_speed(struct nfp_net_hw *hw,\n /* The length of firmware version string */\n #define FW_VER_LEN 32\n \n-static int\n-nfp_reconfig_real(struct nfp_hw *hw,\n-\t\tuint32_t update)\n-{\n-\tuint32_t cnt;\n-\tuint32_t new;\n-\tstruct timespec wait;\n-\n-\tPMD_DRV_LOG(DEBUG, \"Writing to the configuration queue (%p)...\",\n-\t\t\thw->qcp_cfg);\n-\n-\tif (hw->qcp_cfg == NULL) {\n-\t\tPMD_DRV_LOG(ERR, \"Bad configuration queue pointer\");\n-\t\treturn -ENXIO;\n-\t}\n-\n-\tnfp_qcp_ptr_add(hw->qcp_cfg, NFP_QCP_WRITE_PTR, 1);\n-\n-\twait.tv_sec = 0;\n-\twait.tv_nsec = 1000000; /* 1ms */\n-\n-\tPMD_DRV_LOG(DEBUG, \"Polling for update ack...\");\n-\n-\t/* Poll update field, waiting for NFP to ack the config */\n-\tfor (cnt = 0; ; cnt++) {\n-\t\tnew = nn_cfg_readl(hw, NFP_NET_CFG_UPDATE);\n-\t\tif (new == 0)\n-\t\t\tbreak;\n-\n-\t\tif ((new & NFP_NET_CFG_UPDATE_ERR) != 0) {\n-\t\t\tPMD_DRV_LOG(ERR, \"Reconfig error: %#08x\", new);\n-\t\t\treturn -1;\n-\t\t}\n-\n-\t\tif (cnt >= NFP_NET_POLL_TIMEOUT) {\n-\t\t\tPMD_DRV_LOG(ERR, \"Reconfig timeout for %#08x after %u ms\",\n-\t\t\t\t\tupdate, cnt);\n-\t\t\treturn -EIO;\n-\t\t}\n-\n-\t\tnanosleep(&wait, 0); /* Waiting for a 1ms */\n-\t}\n-\n-\tPMD_DRV_LOG(DEBUG, \"Ack DONE\");\n-\treturn 0;\n-}\n-\n-/**\n- * Reconfigure the NIC.\n- *\n- * Write the update word to the BAR and ping the reconfig queue. Then poll\n- * until the firmware has acknowledged the update by zeroing the update word.\n- *\n- * @param hw\n- * Device to reconfigure.\n- * @param ctrl\n- * The value for the ctrl field in the BAR config.\n- * @param update\n- * The value for the update field in the BAR config.\n- *\n- * @return\n- * - (0) if OK to reconfigure the device.\n- * - (-EIO) if I/O err and fail to reconfigure the device.\n- */\n-int\n-nfp_reconfig(struct nfp_hw *hw,\n-\t\tuint32_t ctrl,\n-\t\tuint32_t update)\n-{\n-\tint ret;\n-\n-\trte_spinlock_lock(&hw->reconfig_lock);\n-\n-\tnn_cfg_writel(hw, NFP_NET_CFG_CTRL, ctrl);\n-\tnn_cfg_writel(hw, NFP_NET_CFG_UPDATE, update);\n-\n-\trte_wmb();\n-\n-\tret = nfp_reconfig_real(hw, update);\n-\n-\trte_spinlock_unlock(&hw->reconfig_lock);\n-\n-\tif (ret != 0) {\n-\t\tPMD_DRV_LOG(ERR, \"Error nfp net reconfig: ctrl=%#08x update=%#08x\",\n-\t\t\t\tctrl, update);\n-\t\treturn -EIO;\n-\t}\n-\n-\treturn 0;\n-}\n-\n /**\n * Reconfigure the NIC for the extend ctrl BAR.\n *\n@@ -531,22 +440,6 @@ nfp_net_cfg_queue_setup(struct nfp_net_hw *hw)\n \thw->super.qcp_cfg = hw->tx_bar + NFP_QCP_QUEUE_ADDR_SZ;\n }\n \n-void\n-nfp_net_write_mac(struct nfp_hw *hw,\n-\t\tuint8_t *mac)\n-{\n-\tuint32_t mac0;\n-\tuint16_t mac1;\n-\n-\tmac0 = *(uint32_t *)mac;\n-\tnn_writel(rte_cpu_to_be_32(mac0), hw->ctrl_bar + NFP_NET_CFG_MACADDR);\n-\n-\tmac += 4;\n-\tmac1 = *(uint16_t *)mac;\n-\tnn_writew(rte_cpu_to_be_16(mac1),\n-\t\t\thw->ctrl_bar + NFP_NET_CFG_MACADDR + 6);\n-}\n-\n int\n nfp_net_set_mac_addr(struct rte_eth_dev *dev,\n \t\tstruct rte_ether_addr *mac_addr)\n@@ -565,7 +458,7 @@ nfp_net_set_mac_addr(struct rte_eth_dev *dev,\n \t}\n \n \t/* Writing new MAC to the specific port BAR address */\n-\tnfp_net_write_mac(hw, (uint8_t *)mac_addr);\n+\tnfp_write_mac(hw, (uint8_t *)mac_addr);\n \n \tupdate = NFP_NET_CFG_UPDATE_MACADDR;\n \tctrl = hw->ctrl;\ndiff --git a/drivers/net/nfp/nfp_net_common.h b/drivers/net/nfp/nfp_net_common.h\nindex 02a5ffefd8..0ded35a874 100644\n--- a/drivers/net/nfp/nfp_net_common.h\n+++ b/drivers/net/nfp/nfp_net_common.h\n@@ -8,21 +8,12 @@\n \n #include <bus_pci_driver.h>\n #include <ethdev_driver.h>\n-#include <rte_io.h>\n+#include <nfp_common.h>\n #include <rte_spinlock.h>\n \n #include \"nfp_net_ctrl.h\"\n #include \"nfpcore/nfp_dev.h\"\n \n-/* Macros for accessing the Queue Controller Peripheral 'CSRs' */\n-#define NFP_QCP_QUEUE_OFF(_x) ((_x) * 0x800)\n-#define NFP_QCP_QUEUE_ADD_RPTR 0x0000\n-#define NFP_QCP_QUEUE_ADD_WPTR 0x0004\n-#define NFP_QCP_QUEUE_STS_LO 0x0008\n-#define NFP_QCP_QUEUE_STS_LO_READPTR_MASK (0x3ffff)\n-#define NFP_QCP_QUEUE_STS_HI 0x000c\n-#define NFP_QCP_QUEUE_STS_HI_WRITEPTR_MASK (0x3ffff)\n-\n /* Interrupt definitions */\n #define NFP_NET_IRQ_LSC_IDX 0\n \n@@ -42,8 +33,6 @@\n /* Alignment for dma zones */\n #define NFP_MEMZONE_ALIGN 128\n \n-#define NFP_QCP_QUEUE_ADDR_SZ (0x800)\n-\n /* Number of supported physical ports */\n #define NFP_MAX_PHYPORTS 12\n \n@@ -53,12 +42,6 @@ enum nfp_app_fw_id {\n \tNFP_APP_FW_FLOWER_NIC = 0x3,\n };\n \n-/* Read or Write Pointer of a queue */\n-enum nfp_qcp_ptr {\n-\tNFP_QCP_READ_PTR = 0,\n-\tNFP_QCP_WRITE_PTR\n-};\n-\n enum nfp_net_meta_format {\n \tNFP_NET_METAFORMAT_SINGLE,\n \tNFP_NET_METAFORMAT_CHAINED,\n@@ -112,15 +95,6 @@ struct nfp_app_fw_nic {\n \tuint8_t total_phyports;\n };\n \n-struct nfp_hw {\n-\tuint8_t *ctrl_bar;\n-\tuint8_t *qcp_cfg;\n-\tuint32_t cap;\n-\tuint32_t ctrl; /**< Current values for control */\n-\trte_spinlock_t reconfig_lock;\n-\tstruct rte_ether_addr mac_addr;\n-};\n-\n struct nfp_net_hw {\n \t/** The parent class */\n \tstruct nfp_hw super;\n@@ -183,179 +157,6 @@ struct nfp_net_adapter {\n \tstruct nfp_net_hw hw;\n };\n \n-static inline uint8_t\n-nn_readb(volatile const void *addr)\n-{\n-\treturn rte_read8(addr);\n-}\n-\n-static inline void\n-nn_writeb(uint8_t val,\n-\t\tvolatile void *addr)\n-{\n-\trte_write8(val, addr);\n-}\n-\n-static inline uint32_t\n-nn_readl(volatile const void *addr)\n-{\n-\treturn rte_read32(addr);\n-}\n-\n-static inline void\n-nn_writel(uint32_t val,\n-\t\tvolatile void *addr)\n-{\n-\trte_write32(val, addr);\n-}\n-\n-static inline uint16_t\n-nn_readw(volatile const void *addr)\n-{\n-\treturn rte_read16(addr);\n-}\n-\n-static inline void\n-nn_writew(uint16_t val,\n-\t\tvolatile void *addr)\n-{\n-\trte_write16(val, addr);\n-}\n-\n-static inline uint64_t\n-nn_readq(volatile void *addr)\n-{\n-\tuint32_t low;\n-\tuint32_t high;\n-\tconst volatile uint32_t *p = addr;\n-\n-\thigh = nn_readl((volatile const void *)(p + 1));\n-\tlow = nn_readl((volatile const void *)p);\n-\n-\treturn low + ((uint64_t)high << 32);\n-}\n-\n-static inline void\n-nn_writeq(uint64_t val,\n-\t\tvolatile void *addr)\n-{\n-\tnn_writel(val >> 32, (volatile char *)addr + 4);\n-\tnn_writel(val, addr);\n-}\n-\n-static inline uint8_t\n-nn_cfg_readb(struct nfp_hw *hw,\n-\t\tuint32_t off)\n-{\n-\treturn nn_readb(hw->ctrl_bar + off);\n-}\n-\n-static inline void\n-nn_cfg_writeb(struct nfp_hw *hw,\n-\t\tuint32_t off,\n-\t\tuint8_t val)\n-{\n-\tnn_writeb(val, hw->ctrl_bar + off);\n-}\n-\n-static inline uint16_t\n-nn_cfg_readw(struct nfp_hw *hw,\n-\t\tuint32_t off)\n-{\n-\treturn rte_le_to_cpu_16(nn_readw(hw->ctrl_bar + off));\n-}\n-\n-static inline void\n-nn_cfg_writew(struct nfp_hw *hw,\n-\t\tuint32_t off,\n-\t\tuint16_t val)\n-{\n-\tnn_writew(rte_cpu_to_le_16(val), hw->ctrl_bar + off);\n-}\n-\n-static inline uint32_t\n-nn_cfg_readl(struct nfp_hw *hw,\n-\t\tuint32_t off)\n-{\n-\treturn rte_le_to_cpu_32(nn_readl(hw->ctrl_bar + off));\n-}\n-\n-static inline void\n-nn_cfg_writel(struct nfp_hw *hw,\n-\t\tuint32_t off,\n-\t\tuint32_t val)\n-{\n-\tnn_writel(rte_cpu_to_le_32(val), hw->ctrl_bar + off);\n-}\n-\n-static inline uint64_t\n-nn_cfg_readq(struct nfp_hw *hw,\n-\t\tuint32_t off)\n-{\n-\treturn rte_le_to_cpu_64(nn_readq(hw->ctrl_bar + off));\n-}\n-\n-static inline void\n-nn_cfg_writeq(struct nfp_hw *hw,\n-\t\tuint32_t off,\n-\t\tuint64_t val)\n-{\n-\tnn_writeq(rte_cpu_to_le_64(val), hw->ctrl_bar + off);\n-}\n-\n-/**\n- * Add the value to the selected pointer of a queue.\n- *\n- * @param queue\n- * Base address for queue structure\n- * @param ptr\n- * Add to the read or write pointer\n- * @param val\n- * Value to add to the queue pointer\n- */\n-static inline void\n-nfp_qcp_ptr_add(uint8_t *queue,\n-\t\tenum nfp_qcp_ptr ptr,\n-\t\tuint32_t val)\n-{\n-\tuint32_t off;\n-\n-\tif (ptr == NFP_QCP_READ_PTR)\n-\t\toff = NFP_QCP_QUEUE_ADD_RPTR;\n-\telse\n-\t\toff = NFP_QCP_QUEUE_ADD_WPTR;\n-\n-\tnn_writel(rte_cpu_to_le_32(val), queue + off);\n-}\n-\n-/**\n- * Read the current read/write pointer value for a queue.\n- *\n- * @param queue\n- * Base address for queue structure\n- * @param ptr\n- * Read or Write pointer\n- */\n-static inline uint32_t\n-nfp_qcp_read(uint8_t *queue,\n-\t\tenum nfp_qcp_ptr ptr)\n-{\n-\tuint32_t off;\n-\tuint32_t val;\n-\n-\tif (ptr == NFP_QCP_READ_PTR)\n-\t\toff = NFP_QCP_QUEUE_STS_LO;\n-\telse\n-\t\toff = NFP_QCP_QUEUE_STS_HI;\n-\n-\tval = rte_cpu_to_le_32(nn_readl(queue + off));\n-\n-\tif (ptr == NFP_QCP_READ_PTR)\n-\t\treturn val & NFP_QCP_QUEUE_STS_LO_READPTR_MASK;\n-\telse\n-\t\treturn val & NFP_QCP_QUEUE_STS_HI_WRITEPTR_MASK;\n-}\n-\n static inline uint32_t\n nfp_qcp_queue_offset(const struct nfp_dev_info *dev_info,\n \t\tuint16_t queue)\n@@ -365,7 +166,6 @@ nfp_qcp_queue_offset(const struct nfp_dev_info *dev_info,\n }\n \n /* Prototypes for common NFP functions */\n-int nfp_reconfig(struct nfp_hw *hw, uint32_t ctrl, uint32_t update);\n int nfp_net_ext_reconfig(struct nfp_net_hw *hw, uint32_t ctrl_ext, uint32_t update);\n int nfp_net_mbox_reconfig(struct nfp_net_hw *hw, uint32_t mbox_cmd);\n int nfp_net_configure(struct rte_eth_dev *dev);\n@@ -374,7 +174,6 @@ void nfp_net_log_device_information(const struct nfp_net_hw *hw);\n void nfp_net_enable_queues(struct rte_eth_dev *dev);\n void nfp_net_disable_queues(struct rte_eth_dev *dev);\n void nfp_net_params_setup(struct nfp_net_hw *hw);\n-void nfp_net_write_mac(struct nfp_hw *hw, uint8_t *mac);\n int nfp_net_set_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr);\n int nfp_configure_rx_interrupt(struct rte_eth_dev *dev,\n \t\tstruct rte_intr_handle *intr_handle);\n", "prefixes": [ "14/25" ] }{ "id": 132704, "url": "