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GET /api/patches/132732/?format=api
{ "id": 132732, "url": "http://patchwork.dpdk.org/api/patches/132732/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20231017080928.30454-12-getelson@nvidia.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20231017080928.30454-12-getelson@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20231017080928.30454-12-getelson@nvidia.com", "date": "2023-10-17T08:09:23", "name": "[v3,11/16] net/mlx5: fix modify field expansion for raw DECAP / ENCAP", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "2bed78ca39dccad3bb1476b9b6cd5a261f93b169", "submitter": { "id": 1882, "url": "http://patchwork.dpdk.org/api/people/1882/?format=api", "name": "Gregory Etelson", "email": "getelson@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patchwork.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20231017080928.30454-12-getelson@nvidia.com/mbox/", "series": [ { "id": 29872, "url": "http://patchwork.dpdk.org/api/series/29872/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=29872", "date": "2023-10-17T08:09:12", "name": "net/mlx5: support indirect actions list", "version": 3, "mbox": "http://patchwork.dpdk.org/series/29872/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/132732/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/132732/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 7C25B4318A;\n\tTue, 17 Oct 2023 10:11:37 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 4DB0D427DF;\n\tTue, 17 Oct 2023 10:10:45 +0200 (CEST)", "from NAM11-DM6-obe.outbound.protection.outlook.com\n (mail-dm6nam11on2052.outbound.protection.outlook.com [40.107.223.52])\n by mails.dpdk.org (Postfix) with ESMTP id E3B9040269\n for <dev@dpdk.org>; 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helo=mail.nvidia.com; pr=C", "From": "Gregory Etelson <getelson@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "<getelson@nvidia.com>, =?utf-8?b?wqA=?= <mkashani@nvidia.com>,\n <rasland@nvidia.com>, Suanming Mou <suanmingm@nvidia.com>,\n Matan Azrad <matan@nvidia.com>,\n Viacheslav Ovsiienko <viacheslavo@nvidia.com>, Ori Kam <orika@nvidia.com>", "Subject": "[PATCH v3 11/16] net/mlx5: fix modify field expansion for raw DECAP /\n ENCAP", "Date": "Tue, 17 Oct 2023 11:09:23 +0300", "Message-ID": "<20231017080928.30454-12-getelson@nvidia.com>", "X-Mailer": "git-send-email 2.39.2", "In-Reply-To": "<20231017080928.30454-1-getelson@nvidia.com>", "References": "<20230927191046.405282-1-getelson@nvidia.com>\n <20231017080928.30454-1-getelson@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.35]", "X-ClientProxiedBy": "rnnvmail203.nvidia.com (10.129.68.9) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "CY4PEPF0000E9D8:EE_|SJ1PR12MB6169:EE_", "X-MS-Office365-Filtering-Correlation-Id": "5aaf2d96-7c14-4b13-d53c-08dbcee88be6", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n 8f2BTMdptSbbc+Zf1TxoZWuGVz/H8wwjPLlKSSx28Z6qWbrpc03TMAfwAmOdXLQp8sCzynx0fsbZBKb0xurmW4ZBhQAeX/wFF5jE5t42+pl0rI3mrkGnIZuAxeVaWBmXrWzw0m5ADWWj8iEbIxDfnQCphUh78OMXcfaNzssLo33kzSOVLcWCHCRLjRfZ9IAJ46Baco7BxmJpLVsKLLSxltHxsFTIkYWr13ebb/iyL/olRZQMX3qP6CI2GgyWan8zTMKjPRMh+xGVZNOCmJuE2Xzd+l23LBKIAaOkSy1wFYhoqmv4PUJBLf2bsTqTVbpJYzcsPX4S5KPu8FgTQm7MY1Y3p4JPljZCEX2mEsnYgpIuLpF8jkBrhIvHRVPx+0fqnOR6FCkix0ktL6DVVc0t+OvFbhZlnpwTOYEMR6SpMtHZR5Vnk5TgJ9Y1MUsWIWDLua4QkSJnWJmQYxL6hpSu4a5Q5v+TUS9Yf3yLU/Bq8vXpOr60XoueAF0EFx6Jqnu62aZyzO1zQtzS1j/FgFK2UwJjemL365PKzitsbVYzM18Ro5Z0T8Tlydd1ftG1fG82kRa4d4gplLS41sp5qWrXT654osJtF92wB7kzCG9OiUN7oPI7VBXqgAUwSfzdcbsj0lB7zFQy9UqsA7Ct+CqYXz3thrGxiIadPwLw31NAM4YtXXdABjjdfaZK6kt3B7+nI8+AgLpfBri7IPjknhn3nbDEvmT2fh7dg5Gz1EXlhfKvNalFnXJYNI5T8uVtYcs+", "X-Forefront-Antispam-Report": "CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE;\n SFS:(13230031)(4636009)(136003)(346002)(396003)(376002)(39860400002)(230922051799003)(451199024)(186009)(82310400011)(1800799009)(64100799003)(36840700001)(40470700004)(46966006)(55016003)(40480700001)(40460700003)(7636003)(356005)(36756003)(6666004)(36860700001)(47076005)(83380400001)(82740400003)(26005)(16526019)(6286002)(2906002)(54906003)(7696005)(316002)(6916009)(70206006)(1076003)(70586007)(426003)(336012)(2616005)(107886003)(478600001)(86362001)(41300700001)(8936002)(8676002)(4326008)(5660300002);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "17 Oct 2023 08:10:37.7015 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 5aaf2d96-7c14-4b13-d53c-08dbcee88be6", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CY4PEPF0000E9D8.namprd05.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "SJ1PR12MB6169", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Flow actions in HWS actions template must be arranged according to\npre-defined order.\n\nMLX5 PMD handles RAW_DECAP / RAW_ENCAP actions sequence as a single\nRAW ENCAP or DECAP flow action.\n\nWhen the PMD scanned flow actions to locate position where\nMODIFY_FIELD action could be inserted it processed the\nRAW_DECAP / RAW_ENCAP sequence as 2 separate actions. As the result\nlocation selection was wrong.\n\nThe patch fixes RAW_DECAP / RAW_ENCAP sequence processing for\nMODIFY_FIELD expansion.\n\nFixes: cf7f458 (\"net/mlx5: add indirect QUOTA create/query/modify\")\nSigned-off-by: Gregory Etelson <getelson@nvidia.com>\nAcked-by: Suanming Mou <suanmingm@nvidia.com>\n---\n drivers/net/mlx5/mlx5_flow_hw.c | 36 +++++++++++++++++++++++++++++++--\n 1 file changed, 34 insertions(+), 2 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c\nindex efb2d512b7..7b060442ac 100644\n--- a/drivers/net/mlx5/mlx5_flow_hw.c\n+++ b/drivers/net/mlx5/mlx5_flow_hw.c\n@@ -4283,6 +4283,28 @@ flow_hw_validate_action_raw_encap(struct rte_eth_dev *dev __rte_unused,\n \treturn 0;\n }\n \n+/**\n+ * Process `... / raw_decap / raw_encap / ...` actions sequence.\n+ * The PMD handles the sequence as a single encap or decap reformat action,\n+ * depending on the raw_encap configuration.\n+ *\n+ * The function assumes that the sequence location in actions template list\n+ * complies with relative HWS actions order for the required reformat.\n+ */\n+static uint64_t\n+mlx5_decap_encap_reformat_type(const struct rte_flow_action *actions,\n+\t\t\t uint32_t encap_ind, uint64_t flags)\n+{\n+\tconst struct rte_flow_action_raw_encap *encap = actions[encap_ind].conf;\n+\n+\tif ((flags & MLX5_FLOW_ACTION_DECAP) == 0)\n+\t\treturn MLX5_FLOW_ACTION_ENCAP;\n+\tif (actions[encap_ind - 1].type != RTE_FLOW_ACTION_TYPE_RAW_DECAP)\n+\t\treturn MLX5_FLOW_ACTION_ENCAP;\n+\treturn encap->size >= MLX5_ENCAPSULATION_DECISION_SIZE ?\n+\t MLX5_FLOW_ACTION_ENCAP : MLX5_FLOW_ACTION_DECAP;\n+}\n+\n static inline uint16_t\n flow_hw_template_expand_modify_field(struct rte_flow_action actions[],\n \t\t\t\t struct rte_flow_action masks[],\n@@ -4320,13 +4342,13 @@ flow_hw_template_expand_modify_field(struct rte_flow_action actions[],\n \t */\n \tfor (i = act_num - 2; (int)i >= 0; i--) {\n \t\tenum rte_flow_action_type type = actions[i].type;\n+\t\tuint64_t reformat_type;\n \n \t\tif (type == RTE_FLOW_ACTION_TYPE_INDIRECT)\n \t\t\ttype = masks[i].type;\n \t\tswitch (type) {\n \t\tcase RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:\n \t\tcase RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:\n-\t\tcase RTE_FLOW_ACTION_TYPE_RAW_ENCAP:\n \t\tcase RTE_FLOW_ACTION_TYPE_DROP:\n \t\tcase RTE_FLOW_ACTION_TYPE_SEND_TO_KERNEL:\n \t\tcase RTE_FLOW_ACTION_TYPE_JUMP:\n@@ -4337,10 +4359,20 @@ flow_hw_template_expand_modify_field(struct rte_flow_action actions[],\n \t\tcase RTE_FLOW_ACTION_TYPE_VOID:\n \t\tcase RTE_FLOW_ACTION_TYPE_END:\n \t\t\tbreak;\n+\t\tcase RTE_FLOW_ACTION_TYPE_RAW_ENCAP:\n+\t\t\treformat_type =\n+\t\t\t\tmlx5_decap_encap_reformat_type(actions, i,\n+\t\t\t\t\t\t\t flags);\n+\t\t\tif (reformat_type == MLX5_FLOW_ACTION_DECAP) {\n+\t\t\t\ti++;\n+\t\t\t\tgoto insert;\n+\t\t\t}\n+\t\t\tif (flags & MLX5_FLOW_ACTION_DECAP)\n+\t\t\t\ti--;\n+\t\t\tbreak;\n \t\tdefault:\n \t\t\ti++; /* new MF inserted AFTER actions[i] */\n \t\t\tgoto insert;\n-\t\t\tbreak;\n \t\t}\n \t}\n \ti = 0;\n", "prefixes": [ "v3", "11/16" ] }