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GET /api/patches/133201/?format=api
{ "id": 133201, "url": "http://patchwork.dpdk.org/api/patches/133201/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20231023210707.1344241-7-akozyrev@nvidia.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20231023210707.1344241-7-akozyrev@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20231023210707.1344241-7-akozyrev@nvidia.com", "date": "2023-10-23T21:07:06", "name": "[v2,6/7] net/mlx5/hws: remove csum check from L3 ok check", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "4d8b34b6c030305efc65699e15f08eae1b4b18c5", "submitter": { "id": 1873, "url": "http://patchwork.dpdk.org/api/people/1873/?format=api", "name": "Alexander Kozyrev", "email": "akozyrev@nvidia.com" }, "delegate": { "id": 1, "url": "http://patchwork.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20231023210707.1344241-7-akozyrev@nvidia.com/mbox/", "series": [ { "id": 29958, "url": "http://patchwork.dpdk.org/api/series/29958/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=29958", "date": "2023-10-23T21:07:00", "name": "ptype matching support in mlx5", "version": 2, "mbox": "http://patchwork.dpdk.org/series/29958/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/133201/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/133201/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 09E99431E6;\n\tMon, 23 Oct 2023 23:08:18 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 26C9740DF8;\n\tMon, 23 Oct 2023 23:08:13 +0200 (CEST)", "from NAM04-DM6-obe.outbound.protection.outlook.com\n (mail-dm6nam04on2043.outbound.protection.outlook.com [40.107.102.43])\n by mails.dpdk.org (Postfix) with ESMTP id 19CB0402E7\n for <dev@dpdk.org>; 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helo=mail.nvidia.com; pr=C", "From": "Alexander Kozyrev <akozyrev@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "<orika@nvidia.com>, <matan@nvidia.com>, <michaelba@nvidia.com>,\n <valex@nvidia.com>, <suanmingm@nvidia.com>, <viacheslavo@nvidia.com>", "Subject": "[PATCH v2 6/7] net/mlx5/hws: remove csum check from L3 ok check", "Date": "Tue, 24 Oct 2023 00:07:06 +0300", "Message-ID": "<20231023210707.1344241-7-akozyrev@nvidia.com>", "X-Mailer": "git-send-email 2.18.2", "In-Reply-To": "<20231023210707.1344241-1-akozyrev@nvidia.com>", "References": "<20231009163617.3999365-1-akozyrev@nvidia.com>\n <20231023210707.1344241-1-akozyrev@nvidia.com>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"UTF-8\"", "Content-Transfer-Encoding": "8bit", "X-Originating-IP": "[10.126.230.35]", "X-ClientProxiedBy": "rnnvmail201.nvidia.com (10.129.68.8) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "CY4PEPF0000EDD2:EE_|DS0PR12MB8366:EE_", "X-MS-Office365-Filtering-Correlation-Id": "52cff8e4-51bf-4f40-3877-08dbd40c2828", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n JBzlN/TqBgZWx9QKurH9Zvsb8kvVqkt3Bzjim3oPHkNCvn2vFR85kWD4cUKpXSMnsM7v1BO0InkaU8gvSwC8VAmYa0okWW4KRxpC4rAdhlDCNKRiLv4fregwP31e14Z6pWBpk3aakbaQdZKptNZVXgUgCU2DdF8zaRCygYrbFYvefKJDqb7cvtDGy5w0t2XsnP7wl/M16GNLzcYlNFyEzMclT65wJPToIhleX/KC0LKdrYyz+KBznUZmEQnZtw16JeXTgNqjTh4Jcb6gt/doXfMTtN2O0h1oKo4TYvvDDjAc41SGu0jn7c/jygG70JC6Gwo+IGeqAfwtORx33vjZYLo7V9t3ibgR97ohC5kKMK7sCn9gjXXBoKx79MqFYgnpcezyluGL9bNsxP9UyqJ4kHxnward8RohkOdz5KbBYd9W0v9QANG5IxZJWIrCNTTmg9UsRs5u4KgJdLyXJhbrPri03+ixGXruS4hAinj4mCvzBjABXYFmHdwRtb12hquZ6nygF0otjMHDPiR/oEDf56sAaFfkWDVJFNMJc0BLALAwi0Wa/nmlQcnT4kdQkNumfBU1Y0E4wedMw/u5IC1MQ2LzEDSMe4wBnjZU6vZB+71lG3gEE1VeveqbMFGN1d+WGnJ2TpGJVoLTN1j/DqM1CSIIc5HJXIPefJds/C6bSLQ9VMwxWACKiR4eSYSjCAMsOUGlewiSXnfxhZztNhTBhNn5lJZhMJ6ywyrwGdjVnvMc5joXYEVuzHD+y3U6c9ow", "X-Forefront-Antispam-Report": "CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE;\n SFS:(13230031)(4636009)(346002)(396003)(376002)(39860400002)(136003)(230922051799003)(186009)(64100799003)(451199024)(82310400011)(1800799009)(40470700004)(46966006)(36840700001)(40460700003)(86362001)(2906002)(47076005)(83380400001)(7636003)(41300700001)(36860700001)(36756003)(16526019)(1076003)(5660300002)(26005)(82740400003)(40480700001)(336012)(356005)(2616005)(107886003)(426003)(8936002)(8676002)(478600001)(70206006)(70586007)(54906003)(316002)(4326008)(6916009);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "23 Oct 2023 21:08:08.0384 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 52cff8e4-51bf-4f40-3877-08dbd40c2828", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CY4PEPF0000EDD2.namprd03.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DS0PR12MB8366", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Michael Baum <michaelba@nvidia.com>\n\nThis patch changes the integrity item behavior for HW steering.\n\nOld behavior: the \"ipv4_csum_ok\" checks only IPv4 checksum and \"l3_ok\"\nchecks everything is ok including IPv4 checksum.\n\nNew behavior: the \"l3_ok\" checks everything is ok excluding IPv4\nchecksum.\n\nThis change enables matching \"l3_ok\" in IPv6 packets since for IPv6\npackets \"ipv4_csum_ok\" is always miss.\nFor SW steering the old behavior is kept as same as for L4 ok.\n\nSigned-off-by: Michael Baum <michaelba@nvidia.com>\n---\n doc/guides/nics/mlx5.rst | 19 ++++++++++++-------\n drivers/net/mlx5/hws/mlx5dr_definer.c | 6 ++----\n 2 files changed, 14 insertions(+), 11 deletions(-)", "diff": "diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst\nindex c9e74948cc..5115df12c8 100644\n--- a/doc/guides/nics/mlx5.rst\n+++ b/doc/guides/nics/mlx5.rst\n@@ -663,18 +663,23 @@ Limitations\n \n - Integrity:\n \n- - Integrity offload is enabled starting from **ConnectX-6 Dx**.\n - Verification bits provided by the hardware are ``l3_ok``, ``ipv4_csum_ok``, ``l4_ok``, ``l4_csum_ok``.\n - ``level`` value 0 references outer headers.\n - Negative integrity item verification is not supported.\n- - Multiple integrity items not supported in a single flow rule.\n- - Flow rule items supplied by application must explicitly specify network headers referred by integrity item.\n- For example, if integrity item mask sets ``l4_ok`` or ``l4_csum_ok`` bits, reference to L4 network header,\n- TCP or UDP, must be in the rule pattern as well::\n+ - With SW steering (``dv_flow_en=1``)\n+ - Integrity offload is enabled starting from **ConnectX-6 Dx**.\n+ - Multiple integrity items not supported in a single flow rule.\n+ - Flow rule items supplied by application must explicitly specify network headers referred by integrity item.\n+ For example, if integrity item mask sets ``l4_ok`` or ``l4_csum_ok`` bits, reference to L4 network header,\n+ TCP or UDP, must be in the rule pattern as well::\n \n- flow create 0 ingress pattern integrity level is 0 value mask l3_ok value spec l3_ok / eth / ipv6 / end …\n+ flow create 0 ingress pattern integrity level is 0 value mask l3_ok value spec l3_ok / eth / ipv6 / end …\n \n- flow create 0 ingress pattern integrity level is 0 value mask l4_ok value spec l4_ok / eth / ipv4 proto is udp / end …\n+ flow create 0 ingress pattern integrity level is 0 value mask l4_ok value spec l4_ok / eth / ipv4 proto is udp / end …\n+\n+ - With HW steering (``dv_flow_en=2``)\n+ - The ``l3_ok`` field represents all L3 checks, but nothing about whether IPv4 checksum ok.\n+ - The ``l4_ok`` field represents all L4 checks including L4 checksum ok.\n \n - Connection tracking:\n \ndiff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c\nindex 0e1035c6bd..c752896ca7 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_definer.c\n+++ b/drivers/net/mlx5/hws/mlx5dr_definer.c\n@@ -380,10 +380,8 @@ mlx5dr_definer_integrity_set(struct mlx5dr_definer_fc *fc,\n \tuint32_t ok1_bits = 0;\n \n \tif (v->l3_ok)\n-\t\tok1_bits |= inner ? BIT(MLX5DR_DEFINER_OKS1_SECOND_L3_OK) |\n-\t\t\t\t BIT(MLX5DR_DEFINER_OKS1_SECOND_IPV4_CSUM_OK) :\n-\t\t\t\t BIT(MLX5DR_DEFINER_OKS1_FIRST_L3_OK) |\n-\t\t\t\t BIT(MLX5DR_DEFINER_OKS1_FIRST_IPV4_CSUM_OK);\n+\t\tok1_bits |= inner ? BIT(MLX5DR_DEFINER_OKS1_SECOND_L3_OK) :\n+\t\t\t\t BIT(MLX5DR_DEFINER_OKS1_FIRST_L3_OK);\n \n \tif (v->ipv4_csum_ok)\n \t\tok1_bits |= inner ? BIT(MLX5DR_DEFINER_OKS1_SECOND_IPV4_CSUM_OK) :\n", "prefixes": [ "v2", "6/7" ] }