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GET /api/patches/133202/?format=api
{ "id": 133202, "url": "http://patchwork.dpdk.org/api/patches/133202/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20231023210707.1344241-8-akozyrev@nvidia.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20231023210707.1344241-8-akozyrev@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20231023210707.1344241-8-akozyrev@nvidia.com", "date": "2023-10-23T21:07:07", "name": "[v2,7/7] net/mlx5/hws: fix integrity bits level", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "404d3167c305e0849caeef59850d1870e8cf1faa", "submitter": { "id": 1873, "url": "http://patchwork.dpdk.org/api/people/1873/?format=api", "name": "Alexander Kozyrev", "email": "akozyrev@nvidia.com" }, "delegate": { "id": 1, "url": "http://patchwork.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20231023210707.1344241-8-akozyrev@nvidia.com/mbox/", "series": [ { "id": 29958, "url": "http://patchwork.dpdk.org/api/series/29958/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=29958", "date": "2023-10-23T21:07:00", "name": "ptype matching support in mlx5", "version": 2, "mbox": "http://patchwork.dpdk.org/series/29958/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/133202/comments/", "check": "fail", "checks": "http://patchwork.dpdk.org/api/patches/133202/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 8FB9D431E6;\n\tMon, 23 Oct 2023 23:08:25 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 7BD8340698;\n\tMon, 23 Oct 2023 23:08:25 +0200 (CEST)", "from NAM02-DM3-obe.outbound.protection.outlook.com\n (mail-dm3nam02on2064.outbound.protection.outlook.com [40.107.95.64])\n by mails.dpdk.org (Postfix) with ESMTP id 90DAD402E1\n for <dev@dpdk.org>; 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helo=mail.nvidia.com; pr=C", "From": "Alexander Kozyrev <akozyrev@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "<orika@nvidia.com>, <matan@nvidia.com>, <michaelba@nvidia.com>,\n <valex@nvidia.com>, <suanmingm@nvidia.com>, <viacheslavo@nvidia.com>", "Subject": "[PATCH v2 7/7] net/mlx5/hws: fix integrity bits level", "Date": "Tue, 24 Oct 2023 00:07:07 +0300", "Message-ID": "<20231023210707.1344241-8-akozyrev@nvidia.com>", "X-Mailer": "git-send-email 2.18.2", "In-Reply-To": "<20231023210707.1344241-1-akozyrev@nvidia.com>", "References": "<20231009163617.3999365-1-akozyrev@nvidia.com>\n <20231023210707.1344241-1-akozyrev@nvidia.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.35]", "X-ClientProxiedBy": "rnnvmail201.nvidia.com (10.129.68.8) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "SN1PEPF0002BA4B:EE_|MN0PR12MB6056:EE_", "X-MS-Office365-Filtering-Correlation-Id": "f53729cd-b256-4ac4-fa0b-08dbd40c2e92", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n wPUqg+kcnkMLvvpdxWBKKTpdSqq2uKa6O/LrrQ20dZoavWaAc2VJc8Uh6oItGpUtQq/adP5LKUHp0BqirnSaITDjjhWRsQY30wk43vKCifha1mpjSjb1n8BZxCpUoO0DfiszCN/3PntxE0iWistcDjcdGGNbwLpbFDYv03ck7s9xJlsYVGeqbJNucU+1nkJIGT6esJ4aVx2dHHm90ou5uXrwXSoj9NFhncSmyFMqFtKrmoqTmTmn+TFu6TweJeo2Dz6AwcpKihRmVcUuufbSsDvpWff+VsYiE8GtySEp0Q/PclrTAvyIypEsJFIaSUSTXbm63qusAgnLPjPSLMcBtv98Zdms8Cvdx6Qnw+iPIMUflFiTd42F+PsPqCLbXFhG/YU2IuP4i5fYdtuIkByClzeWyztODsrgLl0Bgzh2bxvQ1M+HONydjGzxSkzTQAA7W2AgOlwkIvV/7I6qPhOO9OnyHWLwIliIQcg4TRWF/nDlXkBiPXxqhNpnIedSDlLHTUcAOehrC+3y24JHtg+pto+0QC0AcBogAW+Sja0+mc6glq9L4LdGyhD5yT66vmJBHCTBlWEw8p0fEezxuY9GW663n66n3nF5D5T0iRZeWkHzAdMg87lhu3qVBypVvZ553j0Doq9JXVEyq/8mga0935403GA+uFjtPArQcQuPAbGTQKvPn1LM6HkVEdfJdt/igaAMOo6oBqGvG7hg5U22aZoCWlzYJ4kEPCCBLUwV9d0HKFWjQSpjV1haR5T8qQVI", "X-Forefront-Antispam-Report": "CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE;\n SFS:(13230031)(4636009)(346002)(39860400002)(396003)(376002)(136003)(230922051799003)(186009)(451199024)(1800799009)(64100799003)(82310400011)(40470700004)(46966006)(36840700001)(40460700003)(8676002)(86362001)(6916009)(36756003)(41300700001)(4326008)(2906002)(1076003)(7636003)(47076005)(40480700001)(356005)(16526019)(5660300002)(26005)(2616005)(82740400003)(36860700001)(336012)(83380400001)(107886003)(426003)(70206006)(478600001)(8936002)(70586007)(54906003)(316002);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "23 Oct 2023 21:08:18.7731 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n f53729cd-b256-4ac4-fa0b-08dbd40c2e92", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n SN1PEPF0002BA4B.namprd03.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "MN0PR12MB6056", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "The level field in the integrity item is not taken into account\nin the current implementation of hardware steering.\nUse this value instead of trying to find out the encapsulation\nlevel according to the protocol items involved.\n\nFixes: c55c2bf35333 (\"net/mlx5/hws: add definer layer\")\n\nSigned-off-by: Alexander Kozyrev <akozyrev@nvidia.com>\n---\n drivers/net/mlx5/hws/mlx5dr_definer.c | 6 ++----\n 1 file changed, 2 insertions(+), 4 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c\nindex c752896ca7..f1f9235956 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_definer.c\n+++ b/drivers/net/mlx5/hws/mlx5dr_definer.c\n@@ -1905,7 +1905,6 @@ mlx5dr_definer_conv_item_integrity(struct mlx5dr_definer_conv_data *cd,\n {\n \tconst struct rte_flow_item_integrity *m = item->mask;\n \tstruct mlx5dr_definer_fc *fc;\n-\tbool inner = cd->tunnel;\n \n \tif (!m)\n \t\treturn 0;\n@@ -1916,7 +1915,7 @@ mlx5dr_definer_conv_item_integrity(struct mlx5dr_definer_conv_data *cd,\n \t}\n \n \tif (m->l3_ok || m->ipv4_csum_ok || m->l4_ok || m->l4_csum_ok) {\n-\t\tfc = &cd->fc[DR_CALC_FNAME(INTEGRITY, inner)];\n+\t\tfc = &cd->fc[DR_CALC_FNAME(INTEGRITY, m->level)];\n \t\tfc->item_idx = item_idx;\n \t\tfc->tag_set = &mlx5dr_definer_integrity_set;\n \t\tDR_CALC_SET_HDR(fc, oks1, oks1_bits);\n@@ -2471,8 +2470,7 @@ mlx5dr_definer_conv_items_to_hl(struct mlx5dr_context *ctx,\n \t\t\tbreak;\n \t\tcase RTE_FLOW_ITEM_TYPE_INTEGRITY:\n \t\t\tret = mlx5dr_definer_conv_item_integrity(&cd, items, i);\n-\t\t\titem_flags |= cd.tunnel ? MLX5_FLOW_ITEM_INNER_INTEGRITY :\n-\t\t\t\t\t\t MLX5_FLOW_ITEM_OUTER_INTEGRITY;\n+\t\t\titem_flags |= MLX5_FLOW_ITEM_INTEGRITY;\n \t\t\tbreak;\n \t\tcase RTE_FLOW_ITEM_TYPE_CONNTRACK:\n \t\t\tret = mlx5dr_definer_conv_item_conntrack(&cd, items, i);\n", "prefixes": [ "v2", "7/7" ] }