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GET /api/patches/133270/?format=api
{ "id": 133270, "url": "http://patchwork.dpdk.org/api/patches/133270/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20231024175132.1435553-4-akozyrev@nvidia.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20231024175132.1435553-4-akozyrev@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20231024175132.1435553-4-akozyrev@nvidia.com", "date": "2023-10-24T17:51:28", "name": "[v3,3/7] net/mlx5/hws: add support for fragmented ptype match", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "87c701ae52b650820a25f631c3e69bd75e840aea", "submitter": { "id": 1873, "url": "http://patchwork.dpdk.org/api/people/1873/?format=api", "name": "Alexander Kozyrev", "email": "akozyrev@nvidia.com" }, "delegate": { "id": 1, "url": "http://patchwork.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20231024175132.1435553-4-akozyrev@nvidia.com/mbox/", "series": [ { "id": 29969, "url": "http://patchwork.dpdk.org/api/series/29969/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=29969", "date": "2023-10-24T17:51:25", "name": "ptype matching support in mlx5", "version": 3, "mbox": "http://patchwork.dpdk.org/series/29969/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/133270/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/133270/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 54BA94316B;\n\tTue, 24 Oct 2023 19:52:34 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id A350940ED3;\n\tTue, 24 Oct 2023 19:52:23 +0200 (CEST)", "from NAM10-BN7-obe.outbound.protection.outlook.com\n (mail-bn7nam10on2041.outbound.protection.outlook.com [40.107.92.41])\n by mails.dpdk.org (Postfix) with ESMTP id 9FD1440ED3\n for <dev@dpdk.org>; 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helo=mail.nvidia.com; pr=C", "From": "Alexander Kozyrev <akozyrev@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "<orika@nvidia.com>, <matan@nvidia.com>, <michaelba@nvidia.com>,\n <valex@nvidia.com>, <suanmingm@nvidia.com>, <viacheslavo@nvidia.com>", "Subject": "[PATCH v3 3/7] net/mlx5/hws: add support for fragmented ptype match", "Date": "Tue, 24 Oct 2023 20:51:28 +0300", "Message-ID": "<20231024175132.1435553-4-akozyrev@nvidia.com>", "X-Mailer": "git-send-email 2.18.2", "In-Reply-To": "<20231024175132.1435553-1-akozyrev@nvidia.com>", "References": "<20230828182251.3917624-1-akozyrev@nvidia.com>\n <20231024175132.1435553-1-akozyrev@nvidia.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.35]", "X-ClientProxiedBy": "rnnvmail201.nvidia.com (10.129.68.8) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "DS1PEPF00017098:EE_|PH8PR12MB6964:EE_", "X-MS-Office365-Filtering-Correlation-Id": "4b11230a-b89c-4466-21bb-08dbd4b9f890", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n 5aVW8+8JB6bajsdmOAPfquNu+jmRD4+4kgw4c86v43HbB17sMem/ONyjRrnF1i9VIQeXR0cJOuTHuPKsAzkjCfP5CwJOGLV29NwWW2QqPinyUPnd3By/NscXnU0Mr/orkeBtWKO8W/tjl1q7n9S6sK1FCvgXF+2p2eja2ZaEZv3H7+IjpKU/7N74KJGRFuLIX8tHWGOU9XI4YEiqDpZGT6lrT9PiHu7uok9jlXycPqIkGOtkWyO/Svyvxi5be1MYuNPKuwrf9LAuoNeZo3HS7bUm8D6wYf0wKRFUsfHKli12LAuUOaQy5kpqUB8b1XmtzNm1d8PSQmaKYSvgfod0RWwNJygH9E0gC08Nhie0QBfDlwMObJlOTmoPotkxRRRZbrGEdYpomee+Wjlyd9OVdh6yWLH8XibKP0DLRE2jS3zEatwpUZEixpSIZZZaHoKpYOnXKtvIj3zcXeWCbLhU9XpRVdhLfsz0uxY3kkxD2wn018I6ZtHgLO97QaL9QO7Kl9WTofJDYhOjssUCdYEp3ROK4k7p2gIdfX0pOGdHJZHYEzUM4mtu8v+rrR3v01gcv95qNl4xR3H/+rgr89f+sEPkjMGlFVjh73l3yKbuQ65Qn4QFqnVdkheDf6XV8OKl26xUJLs1VinBwrIZRXixRUeZ2KnA/EJFgziOAYhafnqq/oP+pSW9Ne+rhaOVWTXDShiylXo3hwK+gG4kwcI9yuch4wD64nBvmPD8F2Fei8Ymc9tHDQkeKL885ojOUhJDITkjHgzFCze2IKr+O/86Nw==", "X-Forefront-Antispam-Report": "CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE;\n SFS:(13230031)(4636009)(396003)(136003)(346002)(376002)(39860400002)(230922051799003)(82310400011)(451199024)(1800799009)(186009)(64100799003)(36840700001)(40470700004)(46966006)(40460700003)(2906002)(316002)(6916009)(86362001)(36860700001)(2616005)(70586007)(7636003)(356005)(6666004)(70206006)(83380400001)(82740400003)(478600001)(426003)(40480700001)(4326008)(336012)(16526019)(1076003)(26005)(5660300002)(107886003)(47076005)(66574015)(36756003)(41300700001)(8676002)(8936002)(54906003)(309714004);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "24 Oct 2023 17:52:20.5728 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 4b11230a-b89c-4466-21bb-08dbd4b9f890", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DS1PEPF00017098.namprd05.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "PH8PR12MB6964", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Expand packet type matching with support of the\nFragmented IP (Internet Protocol) packet type.\n\nSigned-off-by: Alexander Kozyrev <akozyrev@nvidia.com>\n---\n drivers/net/mlx5/hws/mlx5dr_definer.c | 54 ++++++++++++++++++++++-----\n drivers/net/mlx5/hws/mlx5dr_definer.h | 2 +\n 2 files changed, 46 insertions(+), 10 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c\nindex 8d846984e7..0e1035c6bd 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_definer.c\n+++ b/drivers/net/mlx5/hws/mlx5dr_definer.c\n@@ -357,6 +357,19 @@ mlx5dr_definer_ptype_tunnel_set(struct mlx5dr_definer_fc *fc,\n \tDR_SET(tag, tun_type, fc->byte_off, fc->bit_off, fc->bit_mask);\n }\n \n+static void\n+mlx5dr_definer_ptype_frag_set(struct mlx5dr_definer_fc *fc,\n+\t\t\t const void *item_spec,\n+\t\t\t uint8_t *tag)\n+{\n+\tbool inner = (fc->fname == MLX5DR_DEFINER_FNAME_PTYPE_FRAG_I);\n+\tconst struct rte_flow_item_ptype *v = item_spec;\n+\tuint32_t packet_type = v->packet_type &\n+\t\t(inner ? RTE_PTYPE_INNER_L4_FRAG : RTE_PTYPE_L4_FRAG);\n+\n+\tDR_SET(tag, !!packet_type, fc->byte_off, fc->bit_off, fc->bit_mask);\n+}\n+\n static void\n mlx5dr_definer_integrity_set(struct mlx5dr_definer_fc *fc,\n \t\t\t const void *item_spec,\n@@ -1840,19 +1853,40 @@ mlx5dr_definer_conv_item_ptype(struct mlx5dr_definer_conv_data *cd,\n \t}\n \n \tif (m->packet_type & RTE_PTYPE_L4_MASK) {\n-\t\tfc = &cd->fc[DR_CALC_FNAME(PTYPE_L4, false)];\n-\t\tfc->item_idx = item_idx;\n-\t\tfc->tag_set = &mlx5dr_definer_ptype_l4_set;\n-\t\tfc->tag_mask_set = &mlx5dr_definer_ones_set;\n-\t\tDR_CALC_SET(fc, eth_l2, l4_type, false);\n+\t\t/*\n+\t\t * Fragmented IP (Internet Protocol) packet type.\n+\t\t * Cannot be combined with Layer 4 Types (TCP/UDP).\n+\t\t * The exact value must be specified in the mask.\n+\t\t */\n+\t\tif (m->packet_type == RTE_PTYPE_L4_FRAG) {\n+\t\t\tfc = &cd->fc[DR_CALC_FNAME(PTYPE_FRAG, false)];\n+\t\t\tfc->item_idx = item_idx;\n+\t\t\tfc->tag_set = &mlx5dr_definer_ptype_frag_set;\n+\t\t\tfc->tag_mask_set = &mlx5dr_definer_ones_set;\n+\t\t\tDR_CALC_SET(fc, eth_l2, ip_fragmented, false);\n+\t\t} else {\n+\t\t\tfc = &cd->fc[DR_CALC_FNAME(PTYPE_L4, false)];\n+\t\t\tfc->item_idx = item_idx;\n+\t\t\tfc->tag_set = &mlx5dr_definer_ptype_l4_set;\n+\t\t\tfc->tag_mask_set = &mlx5dr_definer_ones_set;\n+\t\t\tDR_CALC_SET(fc, eth_l2, l4_type, false);\n+\t\t}\n \t}\n \n \tif (m->packet_type & RTE_PTYPE_INNER_L4_MASK) {\n-\t\tfc = &cd->fc[DR_CALC_FNAME(PTYPE_L4, true)];\n-\t\tfc->item_idx = item_idx;\n-\t\tfc->tag_set = &mlx5dr_definer_ptype_l4_set;\n-\t\tfc->tag_mask_set = &mlx5dr_definer_ones_set;\n-\t\tDR_CALC_SET(fc, eth_l2, l4_type, true);\n+\t\tif (m->packet_type == RTE_PTYPE_INNER_L4_FRAG) {\n+\t\t\tfc = &cd->fc[DR_CALC_FNAME(PTYPE_FRAG, true)];\n+\t\t\tfc->item_idx = item_idx;\n+\t\t\tfc->tag_set = &mlx5dr_definer_ptype_frag_set;\n+\t\t\tfc->tag_mask_set = &mlx5dr_definer_ones_set;\n+\t\t\tDR_CALC_SET(fc, eth_l2, ip_fragmented, true);\n+\t\t} else {\n+\t\t\tfc = &cd->fc[DR_CALC_FNAME(PTYPE_L4, true)];\n+\t\t\tfc->item_idx = item_idx;\n+\t\t\tfc->tag_set = &mlx5dr_definer_ptype_l4_set;\n+\t\t\tfc->tag_mask_set = &mlx5dr_definer_ones_set;\n+\t\t\tDR_CALC_SET(fc, eth_l2, l4_type, true);\n+\t\t}\n \t}\n \n \tif (m->packet_type & RTE_PTYPE_TUNNEL_MASK) {\ndiff --git a/drivers/net/mlx5/hws/mlx5dr_definer.h b/drivers/net/mlx5/hws/mlx5dr_definer.h\nindex ea07f55d52..791154a7dc 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_definer.h\n+++ b/drivers/net/mlx5/hws/mlx5dr_definer.h\n@@ -148,6 +148,8 @@ enum mlx5dr_definer_fname {\n \tMLX5DR_DEFINER_FNAME_PTYPE_L4_O,\n \tMLX5DR_DEFINER_FNAME_PTYPE_L4_I,\n \tMLX5DR_DEFINER_FNAME_PTYPE_TUNNEL,\n+\tMLX5DR_DEFINER_FNAME_PTYPE_FRAG_O,\n+\tMLX5DR_DEFINER_FNAME_PTYPE_FRAG_I,\n \tMLX5DR_DEFINER_FNAME_MAX,\n };\n \n", "prefixes": [ "v3", "3/7" ] }