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GET /api/patches/133578/?format=api
{ "id": 133578, "url": "http://patchwork.dpdk.org/api/patches/133578/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20231029163202.216450-5-getelson@nvidia.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20231029163202.216450-5-getelson@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20231029163202.216450-5-getelson@nvidia.com", "date": "2023-10-29T16:31:37", "name": "[05/30] net/mlx5: separate port REG_C registers usage", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "cb9a7add904d42e4090f720ffa201362ab55a768", "submitter": { "id": 1882, "url": "http://patchwork.dpdk.org/api/people/1882/?format=api", "name": "Gregory Etelson", "email": "getelson@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patchwork.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20231029163202.216450-5-getelson@nvidia.com/mbox/", "series": [ { "id": 30049, "url": "http://patchwork.dpdk.org/api/series/30049/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=30049", "date": "2023-10-29T16:31:33", "name": "[01/30] net/mlx5/hws: Definer, add mlx5dr context to definer_conv_data", "version": 1, "mbox": "http://patchwork.dpdk.org/series/30049/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/133578/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/133578/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 6564543238;\n\tSun, 29 Oct 2023 17:33:01 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id E53F340DCD;\n\tSun, 29 Oct 2023 17:32:55 +0100 (CET)", "from NAM11-BN8-obe.outbound.protection.outlook.com\n (mail-bn8nam11on2041.outbound.protection.outlook.com [40.107.236.41])\n by mails.dpdk.org (Postfix) with ESMTP id E912A40A7D\n for <dev@dpdk.org>; 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helo=mail.nvidia.com; pr=C", "From": "Gregory Etelson <getelson@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "<getelson@nvidia.com>, <mkashani@nvidia.com>, <rasland@nvidia.com>, \"Ori\n Kam\" <orika@nvidia.com>, Matan Azrad <matan@nvidia.com>, Viacheslav Ovsiienko\n <viacheslavo@nvidia.com>, Suanming Mou <suanmingm@nvidia.com>", "Subject": "[PATCH 05/30] net/mlx5: separate port REG_C registers usage", "Date": "Sun, 29 Oct 2023 18:31:37 +0200", "Message-ID": "<20231029163202.216450-5-getelson@nvidia.com>", "X-Mailer": "git-send-email 2.39.2", "In-Reply-To": "<20231029163202.216450-1-getelson@nvidia.com>", "References": "<20231029163202.216450-1-getelson@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.231.35]", "X-ClientProxiedBy": "rnnvmail203.nvidia.com (10.129.68.9) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "CO1PEPF000044F3:EE_|BL1PR12MB5207:EE_", "X-MS-Office365-Filtering-Correlation-Id": "c886c7f4-6ee4-4661-0660-08dbd89cb198", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n S2ksEo7XjBqMmJLQnFLMqaOLrWP+CtfkI39/9wymTxHD0FvBl/Ql8Joz8xlSyogHoAcbAN6JeXC2VM/g9waldzThL4XBeMzInYdWuu0VuSV1XjgqJhK9952jE7ICrSXRX96HYDe/6hp86Wwy0DDENuqJT7gdJoi7xujR+xtD9be7QAoPZeC+KilDFn3qu5zLbY7sUbpSVDLjYsO3l7UYksGOOCdbtrrOCoMHooEalmIs/MxURNzL8r18AE5VlPeHcbXQ2PE07AChW7v9EWEu8SO6IQui2aIKUWJnxA3f0aSXhc42tzvLp7b44L14u4Gop9k54aw+hUwclwY3ojXtEPUp6PeWt15K24CPFQgT4i+5SqWFSJJw4CUDWIanVLDTJjj+eGlYNpD7qYJ24cVjPGNm5bGte3qTFhyUqT3DJ07xiKP++/CeHtdH4JOWMbYHg4rU3q+6t2faeOWoBq8DbzFE+ZfWCSlFQVsJXUvP9amfdPRK00vrMpX77vAADMy9yracnX+B67SJCKChTRtw/gDk+fsa1ZDa3XMZzxB6V5HdluknN6bdcsYOQ+kwjFYsSXiivOt9SatOryqAD7vLTRfA3ZqNTDa6G++FZtONOdzRJtZ4uZZfrler4bDvAfCp2gj2PhwkLHlrJucg3lLEuxo3v2Rb1EB76XegOE6IEQQ7qT6YnSYFMmP1g6qnfb+cO7ivx5tfASCfMfB28SqslWbaly3klsMXbgmnUvhQzK4Knis0+BwiTM/Y8Mh1p6EvtdvXApPsP8te19ohPFMSdzY1FUm2xu9XABKvn+KQXMQ=", "X-Forefront-Antispam-Report": "CIP:216.228.117.160; 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Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CO1PEPF000044F3.namprd05.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BL1PR12MB5207", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Current implementation stored REG_C registers available for HWS tags\nin PMD global array. As the result, PMD could not work properly with\ndifferent port types that allocate REG_C registers differently.\n\nThe patch stores registers available to a port in the port\nshared context. Register values will be assigned according to the port\ncapabilities.\n\nSigned-off-by: Gregory Etelson <getelson@nvidia.com>\nAcked-by: Ori Kam <orika@nvidia.com>\n---\n drivers/common/mlx5/mlx5_prm.h | 12 +++\n drivers/net/mlx5/linux/mlx5_os.c | 16 ++--\n drivers/net/mlx5/mlx5.c | 4 -\n drivers/net/mlx5/mlx5.h | 11 ++-\n drivers/net/mlx5/mlx5_flow.c | 29 ++-----\n drivers/net/mlx5/mlx5_flow.h | 25 ++----\n drivers/net/mlx5/mlx5_flow_dv.c | 13 +--\n drivers/net/mlx5/mlx5_flow_hw.c | 129 ++++-------------------------\n drivers/net/mlx5/mlx5_flow_meter.c | 14 ++--\n 9 files changed, 78 insertions(+), 175 deletions(-)", "diff": "diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h\nindex bced5a59dd..e13ca3cd22 100644\n--- a/drivers/common/mlx5/mlx5_prm.h\n+++ b/drivers/common/mlx5/mlx5_prm.h\n@@ -864,6 +864,18 @@ enum modify_reg {\n \tREG_C_11,\n };\n \n+static __rte_always_inline uint8_t\n+mlx5_regc_index(enum modify_reg regc_val)\n+{\n+\treturn (uint8_t)(regc_val - REG_C_0);\n+}\n+\n+static __rte_always_inline enum modify_reg\n+mlx5_regc_value(uint8_t regc_ix)\n+{\n+\treturn REG_C_0 + regc_ix;\n+}\n+\n /* Modification sub command. */\n struct mlx5_modification_cmd {\n \tunion {\ndiff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c\nindex d5ef695e6d..96d32d11d8 100644\n--- a/drivers/net/mlx5/linux/mlx5_os.c\n+++ b/drivers/net/mlx5/linux/mlx5_os.c\n@@ -1328,14 +1328,14 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \t\t\t\t * Prefer REG_C_3 if it is available.\n \t\t\t\t */\n \t\t\t\tif (reg_c_mask & (1 << (REG_C_3 - REG_C_0)))\n-\t\t\t\t\tpriv->mtr_color_reg = REG_C_3;\n+\t\t\t\t\tsh->registers.mtr_color_reg = REG_C_3;\n \t\t\t\telse\n-\t\t\t\t\tpriv->mtr_color_reg = ffs(reg_c_mask)\n-\t\t\t\t\t\t\t - 1 + REG_C_0;\n+\t\t\t\t\tsh->registers.mtr_color_reg =\n+\t\t\t\t\t\tffs(reg_c_mask) - 1 + REG_C_0;\n \t\t\t\tpriv->mtr_en = 1;\n \t\t\t\tpriv->mtr_reg_share = hca_attr->qos.flow_meter;\n \t\t\t\tDRV_LOG(DEBUG, \"The REG_C meter uses is %d\",\n-\t\t\t\t\tpriv->mtr_color_reg);\n+\t\t\t\t\tsh->registers.mtr_color_reg);\n \t\t\t}\n \t\t}\n \t\tif (hca_attr->qos.sup && hca_attr->qos.flow_meter_aso_sup) {\n@@ -1360,7 +1360,7 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \t\t\tsh->tunnel_header_2_3 = 1;\n #endif\n #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO\n-\t\tif (hca_attr->flow_hit_aso && priv->mtr_color_reg == REG_C_3) {\n+\t\tif (hca_attr->flow_hit_aso && sh->registers.mtr_color_reg == REG_C_3) {\n \t\t\tsh->flow_hit_aso_en = 1;\n \t\t\terr = mlx5_flow_aso_age_mng_init(sh);\n \t\t\tif (err) {\n@@ -1374,7 +1374,7 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n defined (HAVE_MLX5_DR_ACTION_ASO_CT)\n \t\t/* HWS create CT ASO SQ based on HWS configure queue number. */\n \t\tif (sh->config.dv_flow_en != 2 &&\n-\t\t hca_attr->ct_offload && priv->mtr_color_reg == REG_C_3) {\n+\t\t hca_attr->ct_offload && sh->registers.mtr_color_reg == REG_C_3) {\n \t\t\terr = mlx5_flow_aso_ct_mng_init(sh);\n \t\t\tif (err) {\n \t\t\t\terr = -err;\n@@ -1618,8 +1618,8 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \t\t\t\tgoto error;\n \t\t}\n \t\t/* Only HWS requires this information. */\n-\t\tflow_hw_init_tags_set(eth_dev);\n-\t\tflow_hw_init_flow_metadata_config(eth_dev);\n+\t\tif (sh->refcnt == 1)\n+\t\t\tflow_hw_init_tags_set(eth_dev);\n \t\tif (priv->sh->config.dv_esw_en &&\n \t\t flow_hw_create_vport_action(eth_dev)) {\n \t\t\tDRV_LOG(ERR, \"port %u failed to create vport action\",\ndiff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c\nindex 08b7b03365..c13ce2c13c 100644\n--- a/drivers/net/mlx5/mlx5.c\n+++ b/drivers/net/mlx5/mlx5.c\n@@ -2173,10 +2173,6 @@ mlx5_dev_close(struct rte_eth_dev *dev)\n \tflow_hw_destroy_vport_action(dev);\n \tflow_hw_resource_release(dev);\n \tflow_hw_clear_port_info(dev);\n-\tif (priv->sh->config.dv_flow_en == 2) {\n-\t\tflow_hw_clear_flow_metadata_config();\n-\t\tflow_hw_clear_tags_set(dev);\n-\t}\n #endif\n \tif (priv->rxq_privs != NULL) {\n \t\t/* XXX race condition if mlx5_rx_burst() is still running. */\ndiff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex f3b872f59c..01cb21fc93 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -1373,6 +1373,14 @@ struct mlx5_hws_cnt_svc_mng {\n \tstruct mlx5_hws_aso_mng aso_mng __rte_cache_aligned;\n };\n \n+#define MLX5_FLOW_HW_TAGS_MAX 8\n+\n+struct mlx5_dev_registers {\n+\tenum modify_reg mlx5_flow_hw_aso_tag;\n+\tenum modify_reg mtr_color_reg; /* Meter color match REG_C. */\n+\tenum modify_reg hw_avl_tags[MLX5_FLOW_HW_TAGS_MAX];\n+};\n+\n /*\n * Shared Infiniband device context for Master/Representors\n * which belong to same IB device with multiple IB ports.\n@@ -1393,7 +1401,6 @@ struct mlx5_dev_ctx_shared {\n \tuint32_t drop_action_check_flag:1; /* Check Flag for drop action. */\n \tuint32_t flow_priority_check_flag:1; /* Check Flag for flow priority. */\n \tuint32_t metadata_regc_check_flag:1; /* Check Flag for metadata REGC. */\n-\tuint32_t hws_tags:1; /* Check if tags info for HWS initialized. */\n \tuint32_t shared_mark_enabled:1;\n \t/* If mark action is enabled on Rxqs (shared E-Switch domain). */\n \tuint32_t lag_rx_port_affinity_en:1;\n@@ -1482,6 +1489,7 @@ struct mlx5_dev_ctx_shared {\n \tuint32_t host_shaper_rate:8;\n \tuint32_t lwm_triggered:1;\n \tstruct mlx5_hws_cnt_svc_mng *cnt_svc;\n+\tstruct mlx5_dev_registers registers;\n \tstruct mlx5_dev_shared_port port[]; /* per device port data array. */\n };\n \n@@ -1811,7 +1819,6 @@ struct mlx5_priv {\n \t/* Hash table of Rx metadata register copy table. */\n \tstruct mlx5_mtr_config mtr_config; /* Meter configuration */\n \tuint8_t mtr_sfx_reg; /* Meter prefix-suffix flow match REG_C. */\n-\tuint8_t mtr_color_reg; /* Meter color match REG_C. */\n \tstruct mlx5_legacy_flow_meters flow_meters; /* MTR list. */\n \tstruct mlx5_l3t_tbl *mtr_profile_tbl; /* Meter index lookup table. */\n \tstruct mlx5_flow_meter_profile *mtr_profile_arr; /* Profile array. */\ndiff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c\nindex 45a67607ed..3ddc3ba772 100644\n--- a/drivers/net/mlx5/mlx5_flow.c\n+++ b/drivers/net/mlx5/mlx5_flow.c\n@@ -39,18 +39,6 @@\n */\n struct flow_hw_port_info mlx5_flow_hw_port_infos[RTE_MAX_ETHPORTS];\n \n-/*\n- * A global structure to save the available REG_C_x for tags usage.\n- * The Meter color REG (ASO) and the last available one will be reserved\n- * for PMD internal usage.\n- * Since there is no \"port\" concept in the driver, it is assumed that the\n- * available tags set will be the minimum intersection.\n- * 3 - in FDB mode / 5 - in legacy mode\n- */\n-uint32_t mlx5_flow_hw_avl_tags_init_cnt;\n-enum modify_reg mlx5_flow_hw_avl_tags[MLX5_FLOW_HW_TAGS_MAX] = {REG_NON};\n-enum modify_reg mlx5_flow_hw_aso_tag;\n-\n struct tunnel_default_miss_ctx {\n \tuint16_t *queue;\n \t__extension__\n@@ -1320,6 +1308,7 @@ mlx5_flow_get_reg_id(struct rte_eth_dev *dev,\n {\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n \tstruct mlx5_sh_config *config = &priv->sh->config;\n+\tstruct mlx5_dev_registers *reg = &priv->sh->registers;\n \tenum modify_reg start_reg;\n \tbool skip_mtr_reg = false;\n \n@@ -1375,23 +1364,23 @@ mlx5_flow_get_reg_id(struct rte_eth_dev *dev,\n \t\t * should use the meter color register for match.\n \t\t */\n \t\tif (priv->mtr_reg_share)\n-\t\t\treturn priv->mtr_color_reg;\n+\t\t\treturn reg->mtr_color_reg;\n \t\telse\n-\t\t\treturn priv->mtr_color_reg != REG_C_2 ? REG_C_2 :\n+\t\t\treturn reg->mtr_color_reg != REG_C_2 ? REG_C_2 :\n \t\t\t REG_C_3;\n \tcase MLX5_MTR_COLOR:\n \tcase MLX5_ASO_FLOW_HIT:\n \tcase MLX5_ASO_CONNTRACK:\n \tcase MLX5_SAMPLE_ID:\n \t\t/* All features use the same REG_C. */\n-\t\tMLX5_ASSERT(priv->mtr_color_reg != REG_NON);\n-\t\treturn priv->mtr_color_reg;\n+\t\tMLX5_ASSERT(reg->mtr_color_reg != REG_NON);\n+\t\treturn reg->mtr_color_reg;\n \tcase MLX5_COPY_MARK:\n \t\t/*\n \t\t * Metadata COPY_MARK register using is in meter suffix sub\n \t\t * flow while with meter. It's safe to share the same register.\n \t\t */\n-\t\treturn priv->mtr_color_reg != REG_C_2 ? REG_C_2 : REG_C_3;\n+\t\treturn reg->mtr_color_reg != REG_C_2 ? REG_C_2 : REG_C_3;\n \tcase MLX5_APP_TAG:\n \t\t/*\n \t\t * If meter is enable, it will engage the register for color\n@@ -1400,7 +1389,7 @@ mlx5_flow_get_reg_id(struct rte_eth_dev *dev,\n \t\t * match.\n \t\t * If meter is disable, free to use all available registers.\n \t\t */\n-\t\tstart_reg = priv->mtr_color_reg != REG_C_2 ? REG_C_2 :\n+\t\tstart_reg = reg->mtr_color_reg != REG_C_2 ? REG_C_2 :\n \t\t\t (priv->mtr_reg_share ? REG_C_3 : REG_C_4);\n \t\tskip_mtr_reg = !!(priv->mtr_en && start_reg == REG_C_2);\n \t\tif (id > (uint32_t)(REG_C_7 - start_reg))\n@@ -1418,7 +1407,7 @@ mlx5_flow_get_reg_id(struct rte_eth_dev *dev,\n \t\t * color register.\n \t\t */\n \t\tif (skip_mtr_reg && priv->sh->flow_mreg_c\n-\t\t [id + start_reg - REG_C_0] >= priv->mtr_color_reg) {\n+\t\t [id + start_reg - REG_C_0] >= reg->mtr_color_reg) {\n \t\t\tif (id >= (uint32_t)(REG_C_7 - start_reg))\n \t\t\t\treturn rte_flow_error_set(error, EINVAL,\n \t\t\t\t\t\t RTE_FLOW_ERROR_TYPE_ITEM,\n@@ -6491,7 +6480,7 @@ flow_sample_split_prep(struct rte_eth_dev *dev,\n \t\t * metadata regC is REG_NON, back to use application tag\n \t\t * index 0.\n \t\t */\n-\t\tif (unlikely(priv->mtr_color_reg == REG_NON))\n+\t\tif (unlikely(priv->sh->registers.mtr_color_reg == REG_NON))\n \t\t\tret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, 0, error);\n \t\telse\n \t\t\tret = mlx5_flow_get_reg_id(dev, MLX5_SAMPLE_ID, 0, error);\ndiff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h\nindex 9344b5178a..011db1fb75 100644\n--- a/drivers/net/mlx5/mlx5_flow.h\n+++ b/drivers/net/mlx5/mlx5_flow.h\n@@ -1618,11 +1618,6 @@ struct flow_hw_port_info {\n \n extern struct flow_hw_port_info mlx5_flow_hw_port_infos[RTE_MAX_ETHPORTS];\n \n-#define MLX5_FLOW_HW_TAGS_MAX 8\n-extern uint32_t mlx5_flow_hw_avl_tags_init_cnt;\n-extern enum modify_reg mlx5_flow_hw_avl_tags[];\n-extern enum modify_reg mlx5_flow_hw_aso_tag;\n-\n /*\n * Get metadata match tag and mask for given rte_eth_dev port.\n * Used in HWS rule creation.\n@@ -1664,13 +1659,6 @@ flow_hw_get_wire_port(struct ibv_context *ibctx)\n }\n #endif\n \n-extern uint32_t mlx5_flow_hw_flow_metadata_config_refcnt;\n-extern uint8_t mlx5_flow_hw_flow_metadata_esw_en;\n-extern uint8_t mlx5_flow_hw_flow_metadata_xmeta_en;\n-\n-void flow_hw_init_flow_metadata_config(struct rte_eth_dev *dev);\n-void flow_hw_clear_flow_metadata_config(void);\n-\n /*\n * Convert metadata or tag to the actual register.\n * META: Can only be used to match in the FDB in this stage, fixed C_1.\n@@ -1681,12 +1669,14 @@ static __rte_always_inline int\n flow_hw_get_reg_id(struct rte_eth_dev *dev,\n \t\t enum rte_flow_item_type type, uint32_t id)\n {\n-\tRTE_SET_USED(dev);\n+\tstruct mlx5_dev_ctx_shared *sh = MLX5_SH(dev);\n+\tstruct mlx5_dev_registers *reg = &sh->registers;\n+\n \tswitch (type) {\n \tcase RTE_FLOW_ITEM_TYPE_META:\n #ifdef HAVE_MLX5_HWS_SUPPORT\n-\t\tif (mlx5_flow_hw_flow_metadata_esw_en &&\n-\t\t mlx5_flow_hw_flow_metadata_xmeta_en == MLX5_XMETA_MODE_META32_HWS) {\n+\t\tif (sh->config.dv_esw_en &&\n+\t\t sh->config.dv_xmeta_en == MLX5_XMETA_MODE_META32_HWS) {\n \t\t\treturn REG_C_1;\n \t\t}\n #endif\n@@ -1702,12 +1692,12 @@ flow_hw_get_reg_id(struct rte_eth_dev *dev,\n \t\treturn REG_A;\n \tcase RTE_FLOW_ITEM_TYPE_CONNTRACK:\n \tcase RTE_FLOW_ITEM_TYPE_METER_COLOR:\n-\t\treturn mlx5_flow_hw_aso_tag;\n+\t\treturn reg->mlx5_flow_hw_aso_tag;\n \tcase RTE_FLOW_ITEM_TYPE_TAG:\n \t\tif (id == MLX5_LINEAR_HASH_TAG_INDEX)\n \t\t\treturn REG_C_3;\n \t\tMLX5_ASSERT(id < MLX5_FLOW_HW_TAGS_MAX);\n-\t\treturn mlx5_flow_hw_avl_tags[id];\n+\t\treturn reg->hw_avl_tags[id];\n \tdefault:\n \t\treturn REG_NON;\n \t}\n@@ -1740,7 +1730,6 @@ void flow_hw_set_port_info(struct rte_eth_dev *dev);\n void flow_hw_clear_port_info(struct rte_eth_dev *dev);\n \n void flow_hw_init_tags_set(struct rte_eth_dev *dev);\n-void flow_hw_clear_tags_set(struct rte_eth_dev *dev);\n \n int flow_hw_create_vport_action(struct rte_eth_dev *dev);\n void flow_hw_destroy_vport_action(struct rte_eth_dev *dev);\ndiff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c\nindex 05a374493d..024023abb5 100644\n--- a/drivers/net/mlx5/mlx5_flow_dv.c\n+++ b/drivers/net/mlx5/mlx5_flow_dv.c\n@@ -1919,7 +1919,8 @@ mlx5_flow_field_id_to_modify_info\n \t\t\toff_be = (tag_index == MLX5_LINEAR_HASH_TAG_INDEX) ?\n \t\t\t\t 16 - (data->offset + width) + 16 : data->offset;\n \t\t\tif (priv->sh->config.dv_flow_en == 2)\n-\t\t\t\treg = flow_hw_get_reg_id(dev, RTE_FLOW_ITEM_TYPE_TAG,\n+\t\t\t\treg = flow_hw_get_reg_id(dev,\n+\t\t\t\t\t\t\t RTE_FLOW_ITEM_TYPE_TAG,\n \t\t\t\t\t\t\t data->level);\n \t\t\telse\n \t\t\t\treg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG,\n@@ -2025,7 +2026,7 @@ mlx5_flow_field_id_to_modify_info\n \n \t\t\tif (priv->sh->config.dv_flow_en == 2)\n \t\t\t\treg = flow_hw_get_reg_id\n-\t\t\t\t\t(dev, RTE_FLOW_ITEM_TYPE_METER_COLOR, 0);\n+\t\t\t\t(dev, RTE_FLOW_ITEM_TYPE_METER_COLOR, 0);\n \t\t\telse\n \t\t\t\treg = mlx5_flow_get_reg_id(dev, MLX5_MTR_COLOR,\n \t\t\t\t\t\t 0, error);\n@@ -3922,7 +3923,7 @@ flow_dv_validate_item_meter_color(struct rte_eth_dev *dev,\n \t};\n \tint ret;\n \n-\tif (priv->mtr_color_reg == REG_NON)\n+\tif (priv->sh->registers.mtr_color_reg == REG_NON)\n \t\treturn rte_flow_error_set(error, ENOTSUP,\n \t\t\t\t\t RTE_FLOW_ERROR_TYPE_ITEM, item,\n \t\t\t\t\t \"meter color register\"\n@@ -8373,7 +8374,8 @@ flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,\n \t\t\tif (ret < 0)\n \t\t\t\treturn ret;\n \t\t\tif ((action_flags & MLX5_FLOW_ACTION_SET_TAG) &&\n-\t\t\t tag_id == 0 && priv->mtr_color_reg == REG_NON)\n+\t\t\t tag_id == 0 &&\n+\t\t\t priv->sh->registers.mtr_color_reg == REG_NON)\n \t\t\t\treturn rte_flow_error_set(error, EINVAL,\n \t\t\t\t\tRTE_FLOW_ERROR_TYPE_ACTION, NULL,\n \t\t\t\t\t\"sample after tag action causes metadata tag index 0 corruption\");\n@@ -11057,7 +11059,8 @@ flow_dv_translate_item_meter_color(struct rte_eth_dev *dev, void *key,\n \tif (!!(key_type & MLX5_SET_MATCHER_SW))\n \t\treg = mlx5_flow_get_reg_id(dev, MLX5_MTR_COLOR, 0, NULL);\n \telse\n-\t\treg = flow_hw_get_reg_id(dev, RTE_FLOW_ITEM_TYPE_METER_COLOR, 0);\n+\t\treg = flow_hw_get_reg_id(dev,\n+\t\t\t\t\t RTE_FLOW_ITEM_TYPE_METER_COLOR, 0);\n \tif (reg == REG_NON)\n \t\treturn;\n \tflow_dv_match_meta_reg(key, (enum modify_reg)reg, value, mask);\ndiff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c\nindex d3f065e9c1..22cf412035 100644\n--- a/drivers/net/mlx5/mlx5_flow_hw.c\n+++ b/drivers/net/mlx5/mlx5_flow_hw.c\n@@ -5654,7 +5654,9 @@ flow_hw_pattern_validate(struct rte_eth_dev *dev,\n \t\t\tbreak;\n \t\tcase RTE_FLOW_ITEM_TYPE_METER_COLOR:\n \t\t{\n-\t\t\tint reg = flow_hw_get_reg_id(dev, RTE_FLOW_ITEM_TYPE_METER_COLOR, 0);\n+\t\t\tint reg = flow_hw_get_reg_id(dev,\n+\t\t\t\t\t\t RTE_FLOW_ITEM_TYPE_METER_COLOR,\n+\t\t\t\t\t\t 0);\n \t\t\tif (reg == REG_NON)\n \t\t\t\treturn rte_flow_error_set(error, EINVAL,\n \t\t\t\t\t\t\t RTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n@@ -8456,126 +8458,29 @@ flow_hw_clear_port_info(struct rte_eth_dev *dev)\n */\n void flow_hw_init_tags_set(struct rte_eth_dev *dev)\n {\n-\tstruct mlx5_priv *priv = dev->data->dev_private;\n-\tuint32_t meta_mode = priv->sh->config.dv_xmeta_en;\n-\tuint8_t masks = (uint8_t)priv->sh->cdev->config.hca_attr.set_reg_c;\n-\tuint32_t i, j;\n-\tuint8_t reg_off;\n+\tstruct mlx5_dev_ctx_shared *sh = MLX5_SH(dev);\n+\tstruct mlx5_dev_registers *reg = &sh->registers;\n+\tuint32_t meta_mode = sh->config.dv_xmeta_en;\n+\tuint8_t masks = (uint8_t)sh->cdev->config.hca_attr.set_reg_c;\n \tuint8_t unset = 0;\n-\tuint8_t common_masks = 0;\n+\tuint32_t i, j;\n \n \t/*\n \t * The CAPA is global for common device but only used in net.\n \t * It is shared per eswitch domain.\n \t */\n-\tif (!!priv->sh->hws_tags)\n-\t\treturn;\n-\tunset |= 1 << (priv->mtr_color_reg - REG_C_0);\n-\tunset |= 1 << (REG_C_6 - REG_C_0);\n-\tif (priv->sh->config.dv_esw_en)\n-\t\tunset |= 1 << (REG_C_0 - REG_C_0);\n+\tunset |= 1 << mlx5_regc_index(reg->mtr_color_reg);\n+\tunset |= 1 << mlx5_regc_index(REG_C_6);\n+\tif (sh->config.dv_esw_en)\n+\t\tunset |= 1 << mlx5_regc_index(REG_C_0);\n \tif (meta_mode == MLX5_XMETA_MODE_META32_HWS)\n-\t\tunset |= 1 << (REG_C_1 - REG_C_0);\n+\t\tunset |= 1 << mlx5_regc_index(REG_C_1);\n \tmasks &= ~unset;\n-\t/*\n-\t * If available tag registers were previously calculated,\n-\t * calculate a bitmask with an intersection of sets of:\n-\t * - registers supported by current port,\n-\t * - previously calculated available tag registers.\n-\t */\n-\tif (mlx5_flow_hw_avl_tags_init_cnt) {\n-\t\tMLX5_ASSERT(mlx5_flow_hw_aso_tag == priv->mtr_color_reg);\n-\t\tfor (i = 0; i < MLX5_FLOW_HW_TAGS_MAX; i++) {\n-\t\t\tif (mlx5_flow_hw_avl_tags[i] == REG_NON)\n-\t\t\t\tcontinue;\n-\t\t\treg_off = mlx5_flow_hw_avl_tags[i] - REG_C_0;\n-\t\t\tif ((1 << reg_off) & masks)\n-\t\t\t\tcommon_masks |= (1 << reg_off);\n-\t\t}\n-\t\tif (common_masks != masks)\n-\t\t\tmasks = common_masks;\n-\t\telse\n-\t\t\tgoto after_avl_tags;\n+\tfor (i = 0, j = 0; i < MLX5_FLOW_HW_TAGS_MAX; i++) {\n+\t\tif (!!((1 << i) & masks))\n+\t\t\treg->hw_avl_tags[j++] = mlx5_regc_value(i);\n \t}\n-\tj = 0;\n-\tfor (i = 0; i < MLX5_FLOW_HW_TAGS_MAX; i++) {\n-\t\tif ((1 << i) & masks)\n-\t\t\tmlx5_flow_hw_avl_tags[j++] = (enum modify_reg)(i + (uint32_t)REG_C_0);\n-\t}\n-\t/* Clear the rest of unusable tag indexes. */\n-\tfor (; j < MLX5_FLOW_HW_TAGS_MAX; j++)\n-\t\tmlx5_flow_hw_avl_tags[j] = REG_NON;\n-after_avl_tags:\n-\tpriv->sh->hws_tags = 1;\n-\tmlx5_flow_hw_aso_tag = (enum modify_reg)priv->mtr_color_reg;\n-\tmlx5_flow_hw_avl_tags_init_cnt++;\n-}\n-\n-/*\n- * Reset the available tag registers information to NONE.\n- *\n- * @param[in] dev\n- * Pointer to the rte_eth_dev structure.\n- */\n-void flow_hw_clear_tags_set(struct rte_eth_dev *dev)\n-{\n-\tstruct mlx5_priv *priv = dev->data->dev_private;\n-\n-\tif (!priv->sh->hws_tags)\n-\t\treturn;\n-\tpriv->sh->hws_tags = 0;\n-\tmlx5_flow_hw_avl_tags_init_cnt--;\n-\tif (!mlx5_flow_hw_avl_tags_init_cnt)\n-\t\tmemset(mlx5_flow_hw_avl_tags, REG_NON,\n-\t\t sizeof(enum modify_reg) * MLX5_FLOW_HW_TAGS_MAX);\n-}\n-\n-uint32_t mlx5_flow_hw_flow_metadata_config_refcnt;\n-uint8_t mlx5_flow_hw_flow_metadata_esw_en;\n-uint8_t mlx5_flow_hw_flow_metadata_xmeta_en;\n-\n-/**\n- * Initializes static configuration of META flow items.\n- *\n- * As a temporary workaround, META flow item is translated to a register,\n- * based on statically saved dv_esw_en and dv_xmeta_en device arguments.\n- * It is a workaround for flow_hw_get_reg_id() where port specific information\n- * is not available at runtime.\n- *\n- * Values of dv_esw_en and dv_xmeta_en device arguments are taken from the first opened port.\n- * This means that each mlx5 port will use the same configuration for translation\n- * of META flow items.\n- *\n- * @param[in] dev\n- * Pointer to Ethernet device.\n- */\n-void\n-flow_hw_init_flow_metadata_config(struct rte_eth_dev *dev)\n-{\n-\tuint32_t refcnt;\n-\n-\trefcnt = __atomic_fetch_add(&mlx5_flow_hw_flow_metadata_config_refcnt, 1,\n-\t\t\t\t __ATOMIC_RELAXED);\n-\tif (refcnt > 0)\n-\t\treturn;\n-\tmlx5_flow_hw_flow_metadata_esw_en = MLX5_SH(dev)->config.dv_esw_en;\n-\tmlx5_flow_hw_flow_metadata_xmeta_en = MLX5_SH(dev)->config.dv_xmeta_en;\n-}\n-\n-/**\n- * Clears statically stored configuration related to META flow items.\n- */\n-void\n-flow_hw_clear_flow_metadata_config(void)\n-{\n-\tuint32_t refcnt;\n-\n-\trefcnt = __atomic_fetch_sub(&mlx5_flow_hw_flow_metadata_config_refcnt, 1,\n-\t\t\t\t __ATOMIC_RELAXED) - 1;\n-\tif (refcnt > 0)\n-\t\treturn;\n-\tmlx5_flow_hw_flow_metadata_esw_en = 0;\n-\tmlx5_flow_hw_flow_metadata_xmeta_en = 0;\n+\treg->mlx5_flow_hw_aso_tag = reg->mtr_color_reg;\n }\n \n static int\ndiff --git a/drivers/net/mlx5/mlx5_flow_meter.c b/drivers/net/mlx5/mlx5_flow_meter.c\nindex 14a435d157..eb88dfe39c 100644\n--- a/drivers/net/mlx5/mlx5_flow_meter.c\n+++ b/drivers/net/mlx5/mlx5_flow_meter.c\n@@ -67,7 +67,7 @@ mlx5_flow_meter_action_create(struct mlx5_priv *priv,\n \tval = (ebs_eir >> ASO_DSEG_EBS_MAN_OFFSET) & ASO_DSEG_MAN_MASK;\n \tMLX5_SET(flow_meter_parameters, fmp, ebs_mantissa, val);\n \tmtr_init.next_table = def_policy->sub_policy.tbl_rsc->obj;\n-\tmtr_init.reg_c_index = priv->mtr_color_reg - REG_C_0;\n+\tmtr_init.reg_c_index = priv->sh->registers.mtr_color_reg - REG_C_0;\n \tmtr_init.flow_meter_parameter = fmp;\n \tmtr_init.flow_meter_parameter_sz =\n \t\tMLX5_ST_SZ_BYTES(flow_meter_parameters);\n@@ -1597,6 +1597,7 @@ mlx5_flow_meter_action_modify(struct mlx5_priv *priv,\n \t\tuint64_t modify_bits, uint32_t active_state, uint32_t is_enable)\n {\n #ifdef HAVE_MLX5_DR_CREATE_ACTION_FLOW_METER\n+\tstruct mlx5_dev_ctx_shared *sh = priv->sh;\n \tuint32_t in[MLX5_ST_SZ_DW(flow_meter_parameters)] = { 0 };\n \tuint32_t *attr;\n \tstruct mlx5dv_dr_flow_meter_attr mod_attr = { 0 };\n@@ -1604,19 +1605,20 @@ mlx5_flow_meter_action_modify(struct mlx5_priv *priv,\n \tstruct mlx5_aso_mtr *aso_mtr = NULL;\n \tuint32_t cbs_cir, ebs_eir, val;\n \n-\tif (priv->sh->meter_aso_en) {\n+\tif (sh->meter_aso_en) {\n \t\tfm->is_enable = !!is_enable;\n \t\taso_mtr = container_of(fm, struct mlx5_aso_mtr, fm);\n-\t\tret = mlx5_aso_meter_update_by_wqe(priv->sh, MLX5_HW_INV_QUEUE,\n-\t\t\t\t\t\t aso_mtr, &priv->mtr_bulk, NULL, true);\n+\t\tret = mlx5_aso_meter_update_by_wqe(sh, MLX5_HW_INV_QUEUE,\n+\t\t\t\t\t\t aso_mtr, &priv->mtr_bulk,\n+\t\t\t\t\t\t NULL, true);\n \t\tif (ret)\n \t\t\treturn ret;\n-\t\tret = mlx5_aso_mtr_wait(priv->sh, MLX5_HW_INV_QUEUE, aso_mtr);\n+\t\tret = mlx5_aso_mtr_wait(sh, MLX5_HW_INV_QUEUE, aso_mtr);\n \t\tif (ret)\n \t\t\treturn ret;\n \t} else {\n \t\t/* Fill command parameters. */\n-\t\tmod_attr.reg_c_index = priv->mtr_color_reg - REG_C_0;\n+\t\tmod_attr.reg_c_index = sh->registers.mtr_color_reg - REG_C_0;\n \t\tmod_attr.flow_meter_parameter = in;\n \t\tmod_attr.flow_meter_parameter_sz =\n \t\t\t\tMLX5_ST_SZ_BYTES(flow_meter_parameters);\n", "prefixes": [ "05/30" ] }