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GET /api/patches/133579/?format=api
{ "id": 133579, "url": "http://patchwork.dpdk.org/api/patches/133579/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20231029163202.216450-6-getelson@nvidia.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20231029163202.216450-6-getelson@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20231029163202.216450-6-getelson@nvidia.com", "date": "2023-10-29T16:31:38", "name": "[06/30] net/mlx5: merge REG_C aliases", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "f2111d615ccbaebd9349ff3d9ca1359068c687b8", "submitter": { "id": 1882, "url": "http://patchwork.dpdk.org/api/people/1882/?format=api", "name": "Gregory Etelson", "email": "getelson@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patchwork.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20231029163202.216450-6-getelson@nvidia.com/mbox/", "series": [ { "id": 30049, "url": "http://patchwork.dpdk.org/api/series/30049/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=30049", "date": "2023-10-29T16:31:33", "name": "[01/30] net/mlx5/hws: Definer, add mlx5dr context to definer_conv_data", "version": 1, "mbox": "http://patchwork.dpdk.org/series/30049/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/133579/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/133579/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 58E1443238;\n\tSun, 29 Oct 2023 17:33:11 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 51BEE40E25;\n\tSun, 29 Oct 2023 17:32:58 +0100 (CET)", "from NAM10-DM6-obe.outbound.protection.outlook.com\n (mail-dm6nam10on2079.outbound.protection.outlook.com [40.107.93.79])\n by mails.dpdk.org (Postfix) with ESMTP id 76F1140A7D\n for <dev@dpdk.org>; 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helo=mail.nvidia.com; pr=C", "From": "Gregory Etelson <getelson@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "<getelson@nvidia.com>, <mkashani@nvidia.com>, <rasland@nvidia.com>, \"Ori\n Kam\" <orika@nvidia.com>, Matan Azrad <matan@nvidia.com>, Viacheslav Ovsiienko\n <viacheslavo@nvidia.com>, Suanming Mou <suanmingm@nvidia.com>", "Subject": "[PATCH 06/30] net/mlx5: merge REG_C aliases", "Date": "Sun, 29 Oct 2023 18:31:38 +0200", "Message-ID": "<20231029163202.216450-6-getelson@nvidia.com>", "X-Mailer": "git-send-email 2.39.2", "In-Reply-To": "<20231029163202.216450-1-getelson@nvidia.com>", "References": "<20231029163202.216450-1-getelson@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.231.35]", "X-ClientProxiedBy": "rnnvmail203.nvidia.com (10.129.68.9) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "BL02EPF0001A0FB:EE_|IA1PR12MB8466:EE_", "X-MS-Office365-Filtering-Correlation-Id": "71311350-c685-4017-94d1-08dbd89cb327", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n aV1FL1jDNgUIfICvp96Je7h2wBE6i4SJINflwHkoaVINKUcERfIZl6TezTBlt+yJ02SDC5a6t18QQnC639EKkBG5lnN9qee3EwKAFNcWvVs0NgZyzBK3zkEL06mhknat9ogy4QvMK0BZqdJKtbu8oKgmcFIsNKkm6n2w5umsLvaC/5mz5evdSkgimLCa4UCoEMZFG2xYbibqCM7lML0y1T5hOCI2bJLNO5d75fAUuOAD+sNBtwWBBjuEdndGeILhIaquXhnIhOsxyzOv2NxBNvDsssFmRICZKThgz+Al0cnOOHjcBKibFbICq6IGOTf1lDGPUBzrFdI7qkBuVaGcQBGXTbqKjzNYnhEHTy2KaseQ0Sl6kdFcYrNqxYYqBoO2GWO7OXza7+8gJfY7cgWretcQxQnsuuZQyS6W93TEYJewQtXdPQljtXwa8MRcbXRyLwAFerJfCyauaW43dZkrBawjfe+/0oH8gitLcLLcHnBwUFKG/U0NOO/uMrg0CGumR/xZ70Ujpxup1v1IBs40ij33V8xYLuKqlIueTOMWGlcUeuos/mccg5FzobecolV+QBlh1akxab4a6eJ4zvVM2FtaDIDIq2YPj75O0lBtWg52HRMnzfb6lNnr7bcZ27VILelbpGe2VQ0hDYpXxosLYYxt2DoHIPI1nfmQ13IEmcmBa3gD9JGJUlYXFa7VWXXO1QpYxKHeIhH0oUxXaJTMFGjSqa8TmsfWBQihAIzrEpvG8PunaorTvvbgkgHSwYEP", "X-Forefront-Antispam-Report": "CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE;\n SFS:(13230031)(4636009)(346002)(39860400002)(136003)(396003)(376002)(230922051799003)(82310400011)(1800799009)(186009)(451199024)(64100799003)(46966006)(40470700004)(36840700001)(40460700003)(54906003)(478600001)(7696005)(83380400001)(107886003)(2616005)(6916009)(5660300002)(41300700001)(6286002)(26005)(70586007)(16526019)(426003)(2906002)(1076003)(70206006)(316002)(8936002)(4326008)(8676002)(36756003)(86362001)(36860700001)(356005)(82740400003)(47076005)(7636003)(336012)(40480700001)(55016003);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "29 Oct 2023 16:32:53.3239 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 71311350-c685-4017-94d1-08dbd89cb327", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BL02EPF0001A0FB.namprd03.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "IA1PR12MB8466", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Merge `mtr_color_reg` and `mlx5_flow_hw_aso_tag`\ninto `aso_reg`\n\nSigned-off-by: Gregory Etelson <getelson@nvidia.com>\nAcked-by: Ori Kam <orika@nvidia.com>\n---\n drivers/net/mlx5/linux/mlx5_os.c | 10 +++++-----\n drivers/net/mlx5/mlx5.h | 3 +--\n drivers/net/mlx5/mlx5_flow.c | 16 ++++++++--------\n drivers/net/mlx5/mlx5_flow.h | 3 +--\n drivers/net/mlx5/mlx5_flow_dv.c | 7 ++++---\n drivers/net/mlx5/mlx5_flow_hw.c | 3 +--\n drivers/net/mlx5/mlx5_flow_meter.c | 4 ++--\n 7 files changed, 22 insertions(+), 24 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c\nindex 96d32d11d8..ed273e14cf 100644\n--- a/drivers/net/mlx5/linux/mlx5_os.c\n+++ b/drivers/net/mlx5/linux/mlx5_os.c\n@@ -1328,14 +1328,14 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \t\t\t\t * Prefer REG_C_3 if it is available.\n \t\t\t\t */\n \t\t\t\tif (reg_c_mask & (1 << (REG_C_3 - REG_C_0)))\n-\t\t\t\t\tsh->registers.mtr_color_reg = REG_C_3;\n+\t\t\t\t\tsh->registers.aso_reg = REG_C_3;\n \t\t\t\telse\n-\t\t\t\t\tsh->registers.mtr_color_reg =\n+\t\t\t\t\tsh->registers.aso_reg =\n \t\t\t\t\t\tffs(reg_c_mask) - 1 + REG_C_0;\n \t\t\t\tpriv->mtr_en = 1;\n \t\t\t\tpriv->mtr_reg_share = hca_attr->qos.flow_meter;\n \t\t\t\tDRV_LOG(DEBUG, \"The REG_C meter uses is %d\",\n-\t\t\t\t\tsh->registers.mtr_color_reg);\n+\t\t\t\t\tsh->registers.aso_reg);\n \t\t\t}\n \t\t}\n \t\tif (hca_attr->qos.sup && hca_attr->qos.flow_meter_aso_sup) {\n@@ -1360,7 +1360,7 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \t\t\tsh->tunnel_header_2_3 = 1;\n #endif\n #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO\n-\t\tif (hca_attr->flow_hit_aso && sh->registers.mtr_color_reg == REG_C_3) {\n+\t\tif (hca_attr->flow_hit_aso && sh->registers.aso_reg == REG_C_3) {\n \t\t\tsh->flow_hit_aso_en = 1;\n \t\t\terr = mlx5_flow_aso_age_mng_init(sh);\n \t\t\tif (err) {\n@@ -1374,7 +1374,7 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n defined (HAVE_MLX5_DR_ACTION_ASO_CT)\n \t\t/* HWS create CT ASO SQ based on HWS configure queue number. */\n \t\tif (sh->config.dv_flow_en != 2 &&\n-\t\t hca_attr->ct_offload && sh->registers.mtr_color_reg == REG_C_3) {\n+\t\t hca_attr->ct_offload && sh->registers.aso_reg == REG_C_3) {\n \t\t\terr = mlx5_flow_aso_ct_mng_init(sh);\n \t\t\tif (err) {\n \t\t\t\terr = -err;\ndiff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex 01cb21fc93..99a2ad88ed 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -1376,8 +1376,7 @@ struct mlx5_hws_cnt_svc_mng {\n #define MLX5_FLOW_HW_TAGS_MAX 8\n \n struct mlx5_dev_registers {\n-\tenum modify_reg mlx5_flow_hw_aso_tag;\n-\tenum modify_reg mtr_color_reg; /* Meter color match REG_C. */\n+\tenum modify_reg aso_reg;\n \tenum modify_reg hw_avl_tags[MLX5_FLOW_HW_TAGS_MAX];\n };\n \ndiff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c\nindex 3ddc3ba772..ad9a2f2273 100644\n--- a/drivers/net/mlx5/mlx5_flow.c\n+++ b/drivers/net/mlx5/mlx5_flow.c\n@@ -1364,23 +1364,23 @@ mlx5_flow_get_reg_id(struct rte_eth_dev *dev,\n \t\t * should use the meter color register for match.\n \t\t */\n \t\tif (priv->mtr_reg_share)\n-\t\t\treturn reg->mtr_color_reg;\n+\t\t\treturn reg->aso_reg;\n \t\telse\n-\t\t\treturn reg->mtr_color_reg != REG_C_2 ? REG_C_2 :\n+\t\t\treturn reg->aso_reg != REG_C_2 ? REG_C_2 :\n \t\t\t REG_C_3;\n \tcase MLX5_MTR_COLOR:\n \tcase MLX5_ASO_FLOW_HIT:\n \tcase MLX5_ASO_CONNTRACK:\n \tcase MLX5_SAMPLE_ID:\n \t\t/* All features use the same REG_C. */\n-\t\tMLX5_ASSERT(reg->mtr_color_reg != REG_NON);\n-\t\treturn reg->mtr_color_reg;\n+\t\tMLX5_ASSERT(reg->aso_reg != REG_NON);\n+\t\treturn reg->aso_reg;\n \tcase MLX5_COPY_MARK:\n \t\t/*\n \t\t * Metadata COPY_MARK register using is in meter suffix sub\n \t\t * flow while with meter. It's safe to share the same register.\n \t\t */\n-\t\treturn reg->mtr_color_reg != REG_C_2 ? REG_C_2 : REG_C_3;\n+\t\treturn reg->aso_reg != REG_C_2 ? REG_C_2 : REG_C_3;\n \tcase MLX5_APP_TAG:\n \t\t/*\n \t\t * If meter is enable, it will engage the register for color\n@@ -1389,7 +1389,7 @@ mlx5_flow_get_reg_id(struct rte_eth_dev *dev,\n \t\t * match.\n \t\t * If meter is disable, free to use all available registers.\n \t\t */\n-\t\tstart_reg = reg->mtr_color_reg != REG_C_2 ? REG_C_2 :\n+\t\tstart_reg = reg->aso_reg != REG_C_2 ? REG_C_2 :\n \t\t\t (priv->mtr_reg_share ? REG_C_3 : REG_C_4);\n \t\tskip_mtr_reg = !!(priv->mtr_en && start_reg == REG_C_2);\n \t\tif (id > (uint32_t)(REG_C_7 - start_reg))\n@@ -1407,7 +1407,7 @@ mlx5_flow_get_reg_id(struct rte_eth_dev *dev,\n \t\t * color register.\n \t\t */\n \t\tif (skip_mtr_reg && priv->sh->flow_mreg_c\n-\t\t [id + start_reg - REG_C_0] >= reg->mtr_color_reg) {\n+\t\t [id + start_reg - REG_C_0] >= reg->aso_reg) {\n \t\t\tif (id >= (uint32_t)(REG_C_7 - start_reg))\n \t\t\t\treturn rte_flow_error_set(error, EINVAL,\n \t\t\t\t\t\t RTE_FLOW_ERROR_TYPE_ITEM,\n@@ -6480,7 +6480,7 @@ flow_sample_split_prep(struct rte_eth_dev *dev,\n \t\t * metadata regC is REG_NON, back to use application tag\n \t\t * index 0.\n \t\t */\n-\t\tif (unlikely(priv->sh->registers.mtr_color_reg == REG_NON))\n+\t\tif (unlikely(priv->sh->registers.aso_reg == REG_NON))\n \t\t\tret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, 0, error);\n \t\telse\n \t\t\tret = mlx5_flow_get_reg_id(dev, MLX5_SAMPLE_ID, 0, error);\ndiff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h\nindex 011db1fb75..250d9eb1fc 100644\n--- a/drivers/net/mlx5/mlx5_flow.h\n+++ b/drivers/net/mlx5/mlx5_flow.h\n@@ -1663,7 +1663,6 @@ flow_hw_get_wire_port(struct ibv_context *ibctx)\n * Convert metadata or tag to the actual register.\n * META: Can only be used to match in the FDB in this stage, fixed C_1.\n * TAG: C_x expect meter color reg and the reserved ones.\n- * TODO: Per port / device, FDB or NIC for Meta matching.\n */\n static __rte_always_inline int\n flow_hw_get_reg_id(struct rte_eth_dev *dev,\n@@ -1692,7 +1691,7 @@ flow_hw_get_reg_id(struct rte_eth_dev *dev,\n \t\treturn REG_A;\n \tcase RTE_FLOW_ITEM_TYPE_CONNTRACK:\n \tcase RTE_FLOW_ITEM_TYPE_METER_COLOR:\n-\t\treturn reg->mlx5_flow_hw_aso_tag;\n+\t\treturn reg->aso_reg;\n \tcase RTE_FLOW_ITEM_TYPE_TAG:\n \t\tif (id == MLX5_LINEAR_HASH_TAG_INDEX)\n \t\t\treturn REG_C_3;\ndiff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c\nindex 024023abb5..9268a07c84 100644\n--- a/drivers/net/mlx5/mlx5_flow_dv.c\n+++ b/drivers/net/mlx5/mlx5_flow_dv.c\n@@ -2026,7 +2026,8 @@ mlx5_flow_field_id_to_modify_info\n \n \t\t\tif (priv->sh->config.dv_flow_en == 2)\n \t\t\t\treg = flow_hw_get_reg_id\n-\t\t\t\t(dev, RTE_FLOW_ITEM_TYPE_METER_COLOR, 0);\n+\t\t\t\t\t(dev,\n+\t\t\t\t\t RTE_FLOW_ITEM_TYPE_METER_COLOR, 0);\n \t\t\telse\n \t\t\t\treg = mlx5_flow_get_reg_id(dev, MLX5_MTR_COLOR,\n \t\t\t\t\t\t 0, error);\n@@ -3923,7 +3924,7 @@ flow_dv_validate_item_meter_color(struct rte_eth_dev *dev,\n \t};\n \tint ret;\n \n-\tif (priv->sh->registers.mtr_color_reg == REG_NON)\n+\tif (priv->sh->registers.aso_reg == REG_NON)\n \t\treturn rte_flow_error_set(error, ENOTSUP,\n \t\t\t\t\t RTE_FLOW_ERROR_TYPE_ITEM, item,\n \t\t\t\t\t \"meter color register\"\n@@ -8375,7 +8376,7 @@ flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,\n \t\t\t\treturn ret;\n \t\t\tif ((action_flags & MLX5_FLOW_ACTION_SET_TAG) &&\n \t\t\t tag_id == 0 &&\n-\t\t\t priv->sh->registers.mtr_color_reg == REG_NON)\n+\t\t\t priv->sh->registers.aso_reg == REG_NON)\n \t\t\t\treturn rte_flow_error_set(error, EINVAL,\n \t\t\t\t\tRTE_FLOW_ERROR_TYPE_ACTION, NULL,\n \t\t\t\t\t\"sample after tag action causes metadata tag index 0 corruption\");\ndiff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c\nindex 22cf412035..c48c2eec39 100644\n--- a/drivers/net/mlx5/mlx5_flow_hw.c\n+++ b/drivers/net/mlx5/mlx5_flow_hw.c\n@@ -8469,7 +8469,7 @@ void flow_hw_init_tags_set(struct rte_eth_dev *dev)\n \t * The CAPA is global for common device but only used in net.\n \t * It is shared per eswitch domain.\n \t */\n-\tunset |= 1 << mlx5_regc_index(reg->mtr_color_reg);\n+\tunset |= 1 << mlx5_regc_index(reg->aso_reg);\n \tunset |= 1 << mlx5_regc_index(REG_C_6);\n \tif (sh->config.dv_esw_en)\n \t\tunset |= 1 << mlx5_regc_index(REG_C_0);\n@@ -8480,7 +8480,6 @@ void flow_hw_init_tags_set(struct rte_eth_dev *dev)\n \t\tif (!!((1 << i) & masks))\n \t\t\treg->hw_avl_tags[j++] = mlx5_regc_value(i);\n \t}\n-\treg->mlx5_flow_hw_aso_tag = reg->mtr_color_reg;\n }\n \n static int\ndiff --git a/drivers/net/mlx5/mlx5_flow_meter.c b/drivers/net/mlx5/mlx5_flow_meter.c\nindex eb88dfe39c..7cbf772ea4 100644\n--- a/drivers/net/mlx5/mlx5_flow_meter.c\n+++ b/drivers/net/mlx5/mlx5_flow_meter.c\n@@ -67,7 +67,7 @@ mlx5_flow_meter_action_create(struct mlx5_priv *priv,\n \tval = (ebs_eir >> ASO_DSEG_EBS_MAN_OFFSET) & ASO_DSEG_MAN_MASK;\n \tMLX5_SET(flow_meter_parameters, fmp, ebs_mantissa, val);\n \tmtr_init.next_table = def_policy->sub_policy.tbl_rsc->obj;\n-\tmtr_init.reg_c_index = priv->sh->registers.mtr_color_reg - REG_C_0;\n+\tmtr_init.reg_c_index = priv->sh->registers.aso_reg - REG_C_0;\n \tmtr_init.flow_meter_parameter = fmp;\n \tmtr_init.flow_meter_parameter_sz =\n \t\tMLX5_ST_SZ_BYTES(flow_meter_parameters);\n@@ -1618,7 +1618,7 @@ mlx5_flow_meter_action_modify(struct mlx5_priv *priv,\n \t\t\treturn ret;\n \t} else {\n \t\t/* Fill command parameters. */\n-\t\tmod_attr.reg_c_index = sh->registers.mtr_color_reg - REG_C_0;\n+\t\tmod_attr.reg_c_index = sh->registers.aso_reg - REG_C_0;\n \t\tmod_attr.flow_meter_parameter = in;\n \t\tmod_attr.flow_meter_parameter_sz =\n \t\t\t\tMLX5_ST_SZ_BYTES(flow_meter_parameters);\n", "prefixes": [ "06/30" ] }