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GET /api/patches/133580/?format=api
{ "id": 133580, "url": "http://patchwork.dpdk.org/api/patches/133580/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20231029163202.216450-7-getelson@nvidia.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20231029163202.216450-7-getelson@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20231029163202.216450-7-getelson@nvidia.com", "date": "2023-10-29T16:31:39", "name": "[07/30] net/mlx5: initialize HWS flow tags registers in shared dev context", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "e9e910a01e0b3b5271fbc1fa6186c7d491e0c2c1", "submitter": { "id": 1882, "url": "http://patchwork.dpdk.org/api/people/1882/?format=api", "name": "Gregory Etelson", "email": "getelson@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patchwork.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20231029163202.216450-7-getelson@nvidia.com/mbox/", "series": [ { "id": 30049, "url": "http://patchwork.dpdk.org/api/series/30049/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=30049", "date": "2023-10-29T16:31:33", "name": "[01/30] net/mlx5/hws: Definer, add mlx5dr context to definer_conv_data", "version": 1, "mbox": "http://patchwork.dpdk.org/series/30049/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/133580/comments/", "check": "warning", "checks": "http://patchwork.dpdk.org/api/patches/133580/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 267CA43238;\n\tSun, 29 Oct 2023 17:33:20 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 8237540E64;\n\tSun, 29 Oct 2023 17:32:59 +0100 (CET)", "from NAM12-MW2-obe.outbound.protection.outlook.com\n (mail-mw2nam12on2045.outbound.protection.outlook.com [40.107.244.45])\n by mails.dpdk.org (Postfix) with ESMTP id 561B540E2D\n for <dev@dpdk.org>; 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helo=mail.nvidia.com; pr=C", "From": "Gregory Etelson <getelson@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "<getelson@nvidia.com>, <mkashani@nvidia.com>, <rasland@nvidia.com>, \"Ori\n Kam\" <orika@nvidia.com>, Matan Azrad <matan@nvidia.com>, Viacheslav Ovsiienko\n <viacheslavo@nvidia.com>, Suanming Mou <suanmingm@nvidia.com>", "Subject": "[PATCH 07/30] net/mlx5: initialize HWS flow tags registers in shared\n dev context", "Date": "Sun, 29 Oct 2023 18:31:39 +0200", "Message-ID": "<20231029163202.216450-7-getelson@nvidia.com>", "X-Mailer": "git-send-email 2.39.2", "In-Reply-To": "<20231029163202.216450-1-getelson@nvidia.com>", "References": "<20231029163202.216450-1-getelson@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.231.35]", "X-ClientProxiedBy": "rnnvmail203.nvidia.com (10.129.68.9) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "BL02EPF0001A0FC:EE_|IA1PR12MB8190:EE_", "X-MS-Office365-Filtering-Correlation-Id": "e1db4714-d9cf-4915-187c-08dbd89cb475", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n JlN6O/b1tvcRM4uJbErRKIQZBxIEvO1NCuff1wWGR7d55Z8YMU0WuX1WPGCeBZ0NAZQFIWZ6Crldv97Wqrx2hASKDYT1QE5QIobap3BEY+i9IB13lZNO9ykreL7EP3LNXD8ywqn4wyMbSMdwVIYnEfUbqghTGnnnuCTUbekDKr51GyurUw7jY5ufLulW67EkkLgXCzUkajP/t8voN8kfQfIA0l/uBvVVP4tscNJGBYkC0zDOECoVOh0n+xbrDg6d9KUdTLxCNglgCT2ifyK7ZG3k3MH980bZHxxJeE3ZMjwI+nENgy6txgTrt2cQtpdXIYSrQ514c5mw+ZACULbwOMFWx8qa89x7SNthvYQjy+TX+vr1jfgUI3SrVi7tGtGp5b+LW/Deb3WzQmt9XG+LvUzkFd/Qskixwr9V87YX31q5O4O4lgpk7aADqhGb0tI2xhJSLkeodMiRWd+AAOz77eAsoDPu/ajJGa/IJgP9kvYu+5HaWwjy87wV/+nuk75Eonpz6KJ3I20pSbMCcy26EgmtHwZzxTvCSEr0qV4Ca37dVp774KJOk6Ry/OJNKODxk3rtZqOUNVpCoXoNCIU9kIERHBKc8w6dBGVIIQdz6bSBcmHTMf3teHMbqze7ob+nuy+45pcAhLOeiLFISk9U0JoAqwGAW7nwQysFAcS9jthXx2x0A4S41bU5hOWMxz7oNCh54+E0tywDgYxwI2XGAaktnhZW4BDIqwbQA87AtkOwDptU2ZS/AtR6XTJaHtyfnzz1DKPGRtCNJ4fGfKBxCHf/4bx6Sy0y8Do5Lny7+OA=", "X-Forefront-Antispam-Report": "CIP:216.228.117.161; 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Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BL02EPF0001A0FC.namprd03.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "IA1PR12MB8190", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Move HWS flow tags registers initialization to shared dev context.\n\nSigned-off-by: Gregory Etelson <getelson@nvidia.com>\nAcked-by: Ori Kam <orika@nvidia.com>\n---\n drivers/net/mlx5/linux/mlx5_os.c | 35 ++-------------\n drivers/net/mlx5/mlx5.c | 75 ++++++++++++++++++++++++++++++++\n drivers/net/mlx5/mlx5.h | 6 +++\n drivers/net/mlx5/mlx5_flow.h | 3 --\n drivers/net/mlx5/mlx5_flow_hw.c | 34 ---------------\n 5 files changed, 84 insertions(+), 69 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c\nindex ed273e14cf..ec067ef52c 100644\n--- a/drivers/net/mlx5/linux/mlx5_os.c\n+++ b/drivers/net/mlx5/linux/mlx5_os.c\n@@ -1304,38 +1304,12 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \t\tstruct mlx5_hca_attr *hca_attr = &sh->cdev->config.hca_attr;\n \n \t\tsh->steering_format_version = hca_attr->steering_format_version;\n-#if defined(HAVE_MLX5DV_DR) && \\\n-\t(defined(HAVE_MLX5_DR_CREATE_ACTION_FLOW_METER) || \\\n-\t defined(HAVE_MLX5_DR_CREATE_ACTION_ASO))\n+#if defined(HAVE_MLX5_DR_CREATE_ACTION_ASO_EXT)\n \t\tif (hca_attr->qos.sup && hca_attr->qos.flow_meter_old &&\n \t\t sh->config.dv_flow_en) {\n-\t\t\tuint8_t reg_c_mask = hca_attr->qos.flow_meter_reg_c_ids;\n-\t\t\t/*\n-\t\t\t * Meter needs two REG_C's for color match and pre-sfx\n-\t\t\t * flow match. Here get the REG_C for color match.\n-\t\t\t * REG_C_0 and REG_C_1 is reserved for metadata feature.\n-\t\t\t */\n-\t\t\treg_c_mask &= 0xfc;\n-\t\t\tif (rte_popcount32(reg_c_mask) < 1) {\n-\t\t\t\tpriv->mtr_en = 0;\n-\t\t\t\tDRV_LOG(WARNING, \"No available register for\"\n-\t\t\t\t\t\" meter.\");\n-\t\t\t} else {\n-\t\t\t\t/*\n-\t\t\t\t * The meter color register is used by the\n-\t\t\t\t * flow-hit feature as well.\n-\t\t\t\t * The flow-hit feature must use REG_C_3\n-\t\t\t\t * Prefer REG_C_3 if it is available.\n-\t\t\t\t */\n-\t\t\t\tif (reg_c_mask & (1 << (REG_C_3 - REG_C_0)))\n-\t\t\t\t\tsh->registers.aso_reg = REG_C_3;\n-\t\t\t\telse\n-\t\t\t\t\tsh->registers.aso_reg =\n-\t\t\t\t\t\tffs(reg_c_mask) - 1 + REG_C_0;\n+\t\t\tif (sh->registers.aso_reg != REG_NON) {\n \t\t\t\tpriv->mtr_en = 1;\n \t\t\t\tpriv->mtr_reg_share = hca_attr->qos.flow_meter;\n-\t\t\t\tDRV_LOG(DEBUG, \"The REG_C meter uses is %d\",\n-\t\t\t\t\tsh->registers.aso_reg);\n \t\t\t}\n \t\t}\n \t\tif (hca_attr->qos.sup && hca_attr->qos.flow_meter_aso_sup) {\n@@ -1358,7 +1332,7 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \t\t\tsh->tunnel_header_0_1 = 1;\n \t\tif (hca_attr->flow.tunnel_header_2_3)\n \t\t\tsh->tunnel_header_2_3 = 1;\n-#endif\n+#endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO_EXT */\n #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO\n \t\tif (hca_attr->flow_hit_aso && sh->registers.aso_reg == REG_C_3) {\n \t\t\tsh->flow_hit_aso_en = 1;\n@@ -1617,9 +1591,6 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \t\t\t\terr = ENOTSUP;\n \t\t\t\tgoto error;\n \t\t}\n-\t\t/* Only HWS requires this information. */\n-\t\tif (sh->refcnt == 1)\n-\t\t\tflow_hw_init_tags_set(eth_dev);\n \t\tif (priv->sh->config.dv_esw_en &&\n \t\t flow_hw_create_vport_action(eth_dev)) {\n \t\t\tDRV_LOG(ERR, \"port %u failed to create vport action\",\ndiff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c\nindex c13ce2c13c..840c566162 100644\n--- a/drivers/net/mlx5/mlx5.c\n+++ b/drivers/net/mlx5/mlx5.c\n@@ -1599,6 +1599,80 @@ mlx5_rt_timestamp_config(struct mlx5_dev_ctx_shared *sh,\n \t}\n }\n \n+static void\n+mlx5_init_hws_flow_tags_registers(struct mlx5_dev_ctx_shared *sh)\n+{\n+\tstruct mlx5_dev_registers *reg = &sh->registers;\n+\tuint32_t meta_mode = sh->config.dv_xmeta_en;\n+\tuint8_t masks = (uint8_t)sh->cdev->config.hca_attr.set_reg_c;\n+\tuint8_t unset = 0;\n+\tuint32_t i, j;\n+\n+\t/*\n+\t * The CAPA is global for common device but only used in net.\n+\t * It is shared per eswitch domain.\n+\t */\n+\tif (reg->aso_reg != REG_NON)\n+\t\tunset |= 1 << mlx5_regc_index(reg->aso_reg);\n+\tunset |= 1 << mlx5_regc_index(REG_C_6);\n+\tif (sh->config.dv_esw_en)\n+\t\tunset |= 1 << mlx5_regc_index(REG_C_0);\n+\tif (meta_mode == MLX5_XMETA_MODE_META32_HWS)\n+\t\tunset |= 1 << mlx5_regc_index(REG_C_1);\n+\tmasks &= ~unset;\n+\tfor (i = 0, j = 0; i < MLX5_FLOW_HW_TAGS_MAX; i++) {\n+\t\tif (!!((1 << i) & masks))\n+\t\t\treg->hw_avl_tags[j++] = mlx5_regc_value(i);\n+\t}\n+}\n+\n+static void\n+mlx5_init_aso_register(struct mlx5_dev_ctx_shared *sh)\n+{\n+#if defined(HAVE_MLX5_DR_CREATE_ACTION_ASO_EXT)\n+\tconst struct mlx5_hca_attr *hca_attr = &sh->cdev->config.hca_attr;\n+\tconst struct mlx5_hca_qos_attr *qos = &hca_attr->qos;\n+\tuint8_t reg_c_mask = qos->flow_meter_reg_c_ids & 0xfc;\n+\n+\tif (!(qos->sup && qos->flow_meter_old && sh->config.dv_flow_en))\n+\t\treturn;\n+\t/*\n+\t * Meter needs two REG_C's for color match and pre-sfx\n+\t * flow match. Here get the REG_C for color match.\n+\t * REG_C_0 and REG_C_1 is reserved for metadata feature.\n+\t */\n+\tif (__builtin_popcount(reg_c_mask) > 0) {\n+\t\t/*\n+\t\t * The meter color register is used by the\n+\t\t * flow-hit feature as well.\n+\t\t * The flow-hit feature must use REG_C_3\n+\t\t * Prefer REG_C_3 if it is available.\n+\t\t */\n+\t\tif (reg_c_mask & (1 << mlx5_regc_index(REG_C_3)))\n+\t\t\tsh->registers.aso_reg = REG_C_3;\n+\t\telse\n+\t\t\tsh->registers.aso_reg =\n+\t\t\t\tmlx5_regc_value(ffs(reg_c_mask) - 1);\n+\t}\n+#else\n+\tRTE_SET_USED(sh);\n+#endif\n+}\n+\n+static void\n+mlx5_init_shared_dev_registers(struct mlx5_dev_ctx_shared *sh)\n+{\n+\tif (sh->cdev->config.devx)\n+\t\tmlx5_init_aso_register(sh);\n+\tif (sh->registers.aso_reg != REG_NON) {\n+\t\tDRV_LOG(DEBUG, \"ASO register: REG_C%d\",\n+\t\t\tmlx5_regc_index(sh->registers.aso_reg));\n+\t} else {\n+\t\tDRV_LOG(DEBUG, \"ASO register: NONE\");\n+\t}\n+\tmlx5_init_hws_flow_tags_registers(sh);\n+}\n+\n /**\n * Allocate shared device context. If there is multiport device the\n * master and representors will share this context, if there is single\n@@ -1720,6 +1794,7 @@ mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,\n \t/* Add context to the global device list. */\n \tLIST_INSERT_HEAD(&mlx5_dev_ctx_list, sh, next);\n \trte_spinlock_init(&sh->geneve_tlv_opt_sl);\n+\tmlx5_init_shared_dev_registers(sh);\n exit:\n \tpthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);\n \treturn sh;\ndiff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex 99a2ad88ed..a0dcd788b4 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -1380,6 +1380,12 @@ struct mlx5_dev_registers {\n \tenum modify_reg hw_avl_tags[MLX5_FLOW_HW_TAGS_MAX];\n };\n \n+#if defined(HAVE_MLX5DV_DR) && \\\n+\t(defined(HAVE_MLX5_DR_CREATE_ACTION_FLOW_METER) || \\\n+\t defined(HAVE_MLX5_DR_CREATE_ACTION_ASO))\n+#define HAVE_MLX5_DR_CREATE_ACTION_ASO_EXT\n+#endif\n+\n /*\n * Shared Infiniband device context for Master/Representors\n * which belong to same IB device with multiple IB ports.\ndiff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h\nindex 250d9eb1fc..aea8b38f39 100644\n--- a/drivers/net/mlx5/mlx5_flow.h\n+++ b/drivers/net/mlx5/mlx5_flow.h\n@@ -1727,9 +1727,6 @@ flow_hw_get_reg_id_from_ctx(void *dr_ctx,\n \n void flow_hw_set_port_info(struct rte_eth_dev *dev);\n void flow_hw_clear_port_info(struct rte_eth_dev *dev);\n-\n-void flow_hw_init_tags_set(struct rte_eth_dev *dev);\n-\n int flow_hw_create_vport_action(struct rte_eth_dev *dev);\n void flow_hw_destroy_vport_action(struct rte_eth_dev *dev);\n \ndiff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c\nindex c48c2eec39..b0ef14c14e 100644\n--- a/drivers/net/mlx5/mlx5_flow_hw.c\n+++ b/drivers/net/mlx5/mlx5_flow_hw.c\n@@ -8448,40 +8448,6 @@ flow_hw_clear_port_info(struct rte_eth_dev *dev)\n \tinfo->is_wire = 0;\n }\n \n-/*\n- * Initialize the information of available tag registers and an intersection\n- * of all the probed devices' REG_C_Xs.\n- * PS. No port concept in steering part, right now it cannot be per port level.\n- *\n- * @param[in] dev\n- * Pointer to the rte_eth_dev structure.\n- */\n-void flow_hw_init_tags_set(struct rte_eth_dev *dev)\n-{\n-\tstruct mlx5_dev_ctx_shared *sh = MLX5_SH(dev);\n-\tstruct mlx5_dev_registers *reg = &sh->registers;\n-\tuint32_t meta_mode = sh->config.dv_xmeta_en;\n-\tuint8_t masks = (uint8_t)sh->cdev->config.hca_attr.set_reg_c;\n-\tuint8_t unset = 0;\n-\tuint32_t i, j;\n-\n-\t/*\n-\t * The CAPA is global for common device but only used in net.\n-\t * It is shared per eswitch domain.\n-\t */\n-\tunset |= 1 << mlx5_regc_index(reg->aso_reg);\n-\tunset |= 1 << mlx5_regc_index(REG_C_6);\n-\tif (sh->config.dv_esw_en)\n-\t\tunset |= 1 << mlx5_regc_index(REG_C_0);\n-\tif (meta_mode == MLX5_XMETA_MODE_META32_HWS)\n-\t\tunset |= 1 << mlx5_regc_index(REG_C_1);\n-\tmasks &= ~unset;\n-\tfor (i = 0, j = 0; i < MLX5_FLOW_HW_TAGS_MAX; i++) {\n-\t\tif (!!((1 << i) & masks))\n-\t\t\treg->hw_avl_tags[j++] = mlx5_regc_value(i);\n-\t}\n-}\n-\n static int\n flow_hw_conntrack_destroy(struct rte_eth_dev *dev __rte_unused,\n \t\t\t uint32_t idx,\n", "prefixes": [ "07/30" ] }