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GET /api/patches/133585/?format=api
{ "id": 133585, "url": "http://patchwork.dpdk.org/api/patches/133585/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20231029163202.216450-12-getelson@nvidia.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20231029163202.216450-12-getelson@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20231029163202.216450-12-getelson@nvidia.com", "date": "2023-10-29T16:31:44", "name": "[12/30] net/mlx5: add support for more registers", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "cebfef83b48948125d3a7a08318bd05fa490be69", "submitter": { "id": 1882, "url": "http://patchwork.dpdk.org/api/people/1882/?format=api", "name": "Gregory Etelson", "email": "getelson@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patchwork.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20231029163202.216450-12-getelson@nvidia.com/mbox/", "series": [ { "id": 30049, "url": "http://patchwork.dpdk.org/api/series/30049/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=30049", "date": "2023-10-29T16:31:33", "name": "[01/30] net/mlx5/hws: Definer, add mlx5dr context to definer_conv_data", "version": 1, "mbox": "http://patchwork.dpdk.org/series/30049/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/133585/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/133585/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 7170643238;\n\tSun, 29 Oct 2023 17:34:07 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 4CA8740DCB;\n\tSun, 29 Oct 2023 17:33:11 +0100 (CET)", "from NAM11-CO1-obe.outbound.protection.outlook.com\n (mail-co1nam11on2083.outbound.protection.outlook.com [40.107.220.83])\n by mails.dpdk.org (Postfix) with ESMTP id 52C7F410FA\n for <dev@dpdk.org>; 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helo=mail.nvidia.com; pr=C", "From": "Gregory Etelson <getelson@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "<getelson@nvidia.com>, <mkashani@nvidia.com>, <rasland@nvidia.com>, \"Ori\n Kam\" <orika@nvidia.com>, Matan Azrad <matan@nvidia.com>, Viacheslav Ovsiienko\n <viacheslavo@nvidia.com>, Suanming Mou <suanmingm@nvidia.com>", "Subject": "[PATCH 12/30] net/mlx5: add support for more registers", "Date": "Sun, 29 Oct 2023 18:31:44 +0200", "Message-ID": "<20231029163202.216450-12-getelson@nvidia.com>", "X-Mailer": "git-send-email 2.39.2", "In-Reply-To": "<20231029163202.216450-1-getelson@nvidia.com>", "References": "<20231029163202.216450-1-getelson@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.231.35]", "X-ClientProxiedBy": "rnnvmail203.nvidia.com (10.129.68.9) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "BL02EPF0001A0FC:EE_|DM6PR12MB4388:EE_", "X-MS-Office365-Filtering-Correlation-Id": "6f4c5cb4-d5bc-436b-a045-08dbd89cbbef", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n Ef4buF0r4687hSE7DZh6F3LanXtfvWlbcbslA0thGpXo189Umvdp6OR3iD0tuQ/omVhWD6fUZVf3A8o1LZ9kxtDK7sY7BoogS9OcqBtYGo+lDfPg/mZKOv7B1G8AvhLE8v3JtUkC/4KYmjdBELQaLhxNPpR+LVxkoIpazzv+z01bQs7RXWBT9EBMcmzbpl3Qn/3skfzpTz6oO8CihbjElgpPWfdwtbjGA+i7Nwga9iIGX0B42EjLY+CG+4ziU7LX1V6xZ+BLIHQRr1bf+PBPRSrFoXY3+nVEcq7JRiOiNX2k/EzjVKc8zvwyRZ97cPAhXgQ5O7pAslHX85uWRlo21aARAHLL+P0228MBmvmU6pRUyYWH/kxaKga47wlJvbDvIvomxA+NtE9suv2u6FLctncPB+Vv9Jze/EWtBDs7/4hQNbBWuWGRCgJWu+Mm+kJ5atw3BhD3mhPZGqvrcEH96HcQkMzatkuBVgINji9PSsfZANQMIjJDC9VAf+LTrsLvtmtHEwJ7//Yn5Gox/9rSwPh1FZINNWZAhMYY0hQxXGrUXkKbZa183yhej0Nf1jp9dhfeoliBivwe5duNJ2I6NPN4rkfncuANFqcqNOlXdVsNOW07zbMym3Wu0pwBNjacEA5waLhUA6riqJtDbFvIQzCwDUc5EiH9lDT0n/WrVk4RE4YfLmT56Vs3O1AIn85ONs0GF1Y9BySn5cOFEsy42fd+f0NzSXeKACVfFlUaCehu/3I+sHIxlrJbqTk2SVkM", "X-Forefront-Antispam-Report": "CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE;\n SFS:(13230031)(4636009)(136003)(346002)(376002)(396003)(39860400002)(230922051799003)(82310400011)(1800799009)(186009)(64100799003)(451199024)(36840700001)(40470700004)(46966006)(478600001)(36756003)(86362001)(5660300002)(7696005)(47076005)(40480700001)(6666004)(316002)(6916009)(356005)(7636003)(70206006)(70586007)(54906003)(36860700001)(41300700001)(2906002)(82740400003)(8676002)(8936002)(4326008)(6286002)(16526019)(26005)(336012)(426003)(1076003)(2616005)(107886003)(55016003)(83380400001)(40460700003);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "29 Oct 2023 16:33:08.0723 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 6f4c5cb4-d5bc-436b-a045-08dbd89cbbef", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BL02EPF0001A0FC.namprd03.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DM6PR12MB4388", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Ori Kam <orika@nvidia.com>\n\nThis commit adds the support for a additional registers that were added\nto the HW.\n\nSigned-off-by: Ori Kam <orika@nvidia.com>\n---\n drivers/common/mlx5/mlx5_devx_cmds.c | 16 +++++++++----\n drivers/common/mlx5/mlx5_devx_cmds.h | 2 +-\n drivers/common/mlx5/mlx5_prm.h | 36 ++++++++++++++++++++++++----\n drivers/net/mlx5/mlx5.c | 4 ++--\n drivers/net/mlx5/mlx5.h | 2 +-\n drivers/net/mlx5/mlx5_flow_dv.c | 4 ++++\n drivers/net/mlx5/mlx5_flow_hw.c | 2 +-\n 7 files changed, 53 insertions(+), 13 deletions(-)", "diff": "diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c\nindex 3afb2e9f80..4d8818924a 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.c\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.c\n@@ -1229,7 +1229,7 @@ mlx5_devx_cmd_query_hca_attr(void *ctx,\n \tattr->modify_outer_ip_ecn = MLX5_GET\n \t\t(flow_table_nic_cap, hcattr,\n \t\t ft_header_modify_nic_receive.outer_ip_ecn);\n-\tattr->set_reg_c = 0xff;\n+\tattr->set_reg_c = 0xffff;\n \tif (attr->nic_flow_table) {\n #define GET_RX_REG_X_BITS \\\n \t\tMLX5_GET(flow_table_nic_cap, hcattr, \\\n@@ -1238,10 +1238,16 @@ mlx5_devx_cmd_query_hca_attr(void *ctx,\n \t\tMLX5_GET(flow_table_nic_cap, hcattr, \\\n \t\t\t ft_header_modify_nic_transmit.metadata_reg_c_x)\n \n-\t\tuint32_t tx_reg, rx_reg;\n+\t\tuint32_t tx_reg, rx_reg, reg_c_8_15;\n \n \t\ttx_reg = GET_TX_REG_X_BITS;\n+\t\treg_c_8_15 = MLX5_GET(flow_table_nic_cap, hcattr,\n+\t\t\t\t ft_field_support_2_nic_transmit.metadata_reg_c_8_15);\n+\t\ttx_reg |= ((0xff & reg_c_8_15) << 8);\n \t\trx_reg = GET_RX_REG_X_BITS;\n+\t\treg_c_8_15 = MLX5_GET(flow_table_nic_cap, hcattr,\n+\t\t\t\t ft_field_support_2_nic_receive.metadata_reg_c_8_15);\n+\t\trx_reg |= ((0xff & reg_c_8_15) << 8);\n \t\tattr->set_reg_c &= (rx_reg & tx_reg);\n \n #undef GET_RX_REG_X_BITS\n@@ -1371,7 +1377,7 @@ mlx5_devx_cmd_query_hca_attr(void *ctx,\n \t\t\tMLX5_GET(esw_cap, hcattr, esw_manager_vport_number);\n \t}\n \tif (attr->eswitch_manager) {\n-\t\tuint32_t esw_reg;\n+\t\tuint32_t esw_reg, reg_c_8_15;\n \n \t\thcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,\n \t\t\t\tMLX5_GET_HCA_CAP_OP_MOD_ESW_FLOW_TABLE |\n@@ -1380,7 +1386,9 @@ mlx5_devx_cmd_query_hca_attr(void *ctx,\n \t\t\treturn rc;\n \t\tesw_reg = MLX5_GET(flow_table_esw_cap, hcattr,\n \t\t\t\t ft_header_modify_esw_fdb.metadata_reg_c_x);\n-\t\tattr->set_reg_c &= esw_reg;\n+\t\treg_c_8_15 = MLX5_GET(flow_table_esw_cap, hcattr,\n+\t\t\t\t ft_field_support_2_esw_fdb.metadata_reg_c_8_15);\n+\t\tattr->set_reg_c &= ((0xff & reg_c_8_15) << 8) | esw_reg;\n \t}\n \treturn 0;\n error:\ndiff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h\nindex 11772431ae..7f23e925a5 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.h\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.h\n@@ -301,7 +301,7 @@ struct mlx5_hca_attr {\n \tuint32_t cqe_compression_128:1;\n \tuint32_t multi_pkt_send_wqe:1;\n \tuint32_t enhanced_multi_pkt_send_wqe:1;\n-\tuint32_t set_reg_c:8;\n+\tuint32_t set_reg_c:16;\n \tuint32_t nic_flow_table:1;\n \tuint32_t modify_outer_ip_ecn:1;\n \tunion {\ndiff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h\nindex 19c6d0282b..2b499666f8 100644\n--- a/drivers/common/mlx5/mlx5_prm.h\n+++ b/drivers/common/mlx5/mlx5_prm.h\n@@ -840,6 +840,14 @@ enum mlx5_modification_field {\n \tMLX5_MODI_IN_MPLS_LABEL_3,\n \tMLX5_MODI_IN_MPLS_LABEL_4,\n \tMLX5_MODI_OUT_IPV6_NEXT_HDR = 0x4A,\n+\tMLX5_MODI_META_REG_C_8 = 0x8F,\n+\tMLX5_MODI_META_REG_C_9 = 0x90,\n+\tMLX5_MODI_META_REG_C_10 = 0x91,\n+\tMLX5_MODI_META_REG_C_11 = 0x92,\n+\tMLX5_MODI_META_REG_C_12 = 0x93,\n+\tMLX5_MODI_META_REG_C_13 = 0x94,\n+\tMLX5_MODI_META_REG_C_14 = 0x95,\n+\tMLX5_MODI_META_REG_C_15 = 0x96,\n \tMLX5_MODI_INVALID = INT_MAX,\n };\n \n@@ -2227,8 +2235,22 @@ struct mlx5_ifc_ft_fields_support_2_bits {\n \tu8 inner_ipv4_checksum_ok[0x1];\n \tu8 inner_l4_checksum_ok[0x1];\n \tu8 outer_ipv4_checksum_ok[0x1];\n-\tu8 outer_l4_checksum_ok[0x1];\n-\tu8 reserved_at_20[0x60];\n+\tu8 outer_l4_checksum_ok[0x1]; /* end of DW0 */\n+\tu8 reserved_at_20[0x18];\n+\tunion {\n+\t\tstruct {\n+\t\t\tu8 metadata_reg_c_15[0x1];\n+\t\t\tu8 metadata_reg_c_14[0x1];\n+\t\t\tu8 metadata_reg_c_13[0x1];\n+\t\t\tu8 metadata_reg_c_12[0x1];\n+\t\t\tu8 metadata_reg_c_11[0x1];\n+\t\t\tu8 metadata_reg_c_10[0x1];\n+\t\t\tu8 metadata_reg_c_9[0x1];\n+\t\t\tu8 metadata_reg_c_8[0x1];\n+\t\t};\n+\t\tu8 metadata_reg_c_8_15[0x8];\n+\t}; /* end of DW1 */\n+\tu8 reserved_at_40[0x40];\n };\n \n struct mlx5_ifc_flow_table_nic_cap_bits {\n@@ -2250,7 +2272,10 @@ struct mlx5_ifc_flow_table_nic_cap_bits {\n \t\tft_header_modify_nic_receive;\n \tstruct mlx5_ifc_ft_fields_support_2_bits\n \t\tft_field_support_2_nic_receive;\n-\tu8 reserved_at_1480[0x780];\n+\tu8 reserved_at_1480[0x280];\n+\tstruct mlx5_ifc_ft_fields_support_2_bits\n+\t\tft_field_support_2_nic_transmit;\n+\tu8 reserved_at_1780[0x480];\n \tstruct mlx5_ifc_ft_fields_support_bits\n \t\tft_header_modify_nic_transmit;\n \tu8 reserved_at_2000[0x6000];\n@@ -2259,7 +2284,10 @@ struct mlx5_ifc_flow_table_nic_cap_bits {\n struct mlx5_ifc_flow_table_esw_cap_bits {\n \tu8 reserved_at_0[0x800];\n \tstruct mlx5_ifc_ft_fields_support_bits ft_header_modify_esw_fdb;\n-\tu8 reserved_at_C00[0x7400];\n+\tu8 reserved_at_C00[0x800];\n+\tstruct mlx5_ifc_ft_fields_support_2_bits\n+\t\tft_field_support_2_esw_fdb;\n+\tu8 reserved_at_1480[0x6b80];\n };\n \n enum mlx5_ifc_cross_vhca_object_to_object_supported_types {\ndiff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c\nindex 840c566162..cdb4eeb612 100644\n--- a/drivers/net/mlx5/mlx5.c\n+++ b/drivers/net/mlx5/mlx5.c\n@@ -1604,8 +1604,8 @@ mlx5_init_hws_flow_tags_registers(struct mlx5_dev_ctx_shared *sh)\n {\n \tstruct mlx5_dev_registers *reg = &sh->registers;\n \tuint32_t meta_mode = sh->config.dv_xmeta_en;\n-\tuint8_t masks = (uint8_t)sh->cdev->config.hca_attr.set_reg_c;\n-\tuint8_t unset = 0;\n+\tuint16_t masks = (uint16_t)sh->cdev->config.hca_attr.set_reg_c;\n+\tuint16_t unset = 0;\n \tuint32_t i, j;\n \n \t/*\ndiff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex a0dcd788b4..0289cbd04b 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -1373,7 +1373,7 @@ struct mlx5_hws_cnt_svc_mng {\n \tstruct mlx5_hws_aso_mng aso_mng __rte_cache_aligned;\n };\n \n-#define MLX5_FLOW_HW_TAGS_MAX 8\n+#define MLX5_FLOW_HW_TAGS_MAX 12\n \n struct mlx5_dev_registers {\n \tenum modify_reg aso_reg;\ndiff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c\nindex 9268a07c84..bdc8d0076a 100644\n--- a/drivers/net/mlx5/mlx5_flow_dv.c\n+++ b/drivers/net/mlx5/mlx5_flow_dv.c\n@@ -970,6 +970,10 @@ static enum mlx5_modification_field reg_to_field[] = {\n \t[REG_C_5] = MLX5_MODI_META_REG_C_5,\n \t[REG_C_6] = MLX5_MODI_META_REG_C_6,\n \t[REG_C_7] = MLX5_MODI_META_REG_C_7,\n+\t[REG_C_8] = MLX5_MODI_META_REG_C_8,\n+\t[REG_C_9] = MLX5_MODI_META_REG_C_9,\n+\t[REG_C_10] = MLX5_MODI_META_REG_C_10,\n+\t[REG_C_11] = MLX5_MODI_META_REG_C_11,\n };\n \n /**\ndiff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c\nindex 9e549a1ba2..ceeb82a649 100644\n--- a/drivers/net/mlx5/mlx5_flow_hw.c\n+++ b/drivers/net/mlx5/mlx5_flow_hw.c\n@@ -5615,7 +5615,7 @@ flow_hw_pattern_validate(struct rte_eth_dev *dev,\n \t\t{\n \t\t\tconst struct rte_flow_item_tag *tag =\n \t\t\t\t(const struct rte_flow_item_tag *)items[i].spec;\n-\t\t\tuint8_t regcs = (uint8_t)priv->sh->cdev->config.hca_attr.set_reg_c;\n+\t\t\tuint16_t regcs = (uint8_t)priv->sh->cdev->config.hca_attr.set_reg_c;\n \n \t\t\tif (!((1 << (tag->index - REG_C_0)) & regcs))\n \t\t\t\treturn rte_flow_error_set(error, EINVAL,\n", "prefixes": [ "12/30" ] }