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GET /api/patches/133675/?format=api
{ "id": 133675, "url": "http://patchwork.dpdk.org/api/patches/133675/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20231031142733.2009166-8-dsosnowski@nvidia.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20231031142733.2009166-8-dsosnowski@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20231031142733.2009166-8-dsosnowski@nvidia.com", "date": "2023-10-31T14:27:32", "name": "[7/8] net/mlx5: sort port spawn data with uplink ports first", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "b6fc95ed8a6a278267c2f11b9a4a717a540372e0", "submitter": { "id": 2386, "url": "http://patchwork.dpdk.org/api/people/2386/?format=api", "name": "Dariusz Sosnowski", "email": "dsosnowski@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patchwork.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20231031142733.2009166-8-dsosnowski@nvidia.com/mbox/", "series": [ { "id": 30075, "url": "http://patchwork.dpdk.org/api/series/30075/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=30075", "date": "2023-10-31T14:27:26", "name": "net/mlx5: add Multiport E-Switch support", "version": 1, "mbox": "http://patchwork.dpdk.org/series/30075/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/133675/comments/", "check": "warning", "checks": "http://patchwork.dpdk.org/api/patches/133675/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id B272E43252;\n\tTue, 31 Oct 2023 15:29:11 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id AEB99427D7;\n\tTue, 31 Oct 2023 15:28:36 +0100 (CET)", "from NAM12-MW2-obe.outbound.protection.outlook.com\n (mail-mw2nam12on2045.outbound.protection.outlook.com [40.107.244.45])\n by mails.dpdk.org (Postfix) with ESMTP id 9ADA340DDE\n for <dev@dpdk.org>; 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helo=mail.nvidia.com; pr=C", "From": "Dariusz Sosnowski <dsosnowski@nvidia.com>", "To": "Matan Azrad <matan@nvidia.com>, Viacheslav Ovsiienko\n <viacheslavo@nvidia.com>, Ori Kam <orika@nvidia.com>, Suanming Mou\n <suanmingm@nvidia.com>", "CC": "<dev@dpdk.org>, Raslan Darawsheh <rasland@nvidia.com>", "Subject": "[PATCH 7/8] net/mlx5: sort port spawn data with uplink ports first", "Date": "Tue, 31 Oct 2023 16:27:32 +0200", "Message-ID": "<20231031142733.2009166-8-dsosnowski@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20231031142733.2009166-1-dsosnowski@nvidia.com>", "References": "<20231031142733.2009166-1-dsosnowski@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.231.35]", "X-ClientProxiedBy": "rnnvmail202.nvidia.com (10.129.68.7) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "MWH0EPF000971E6:EE_|CH3PR12MB8535:EE_", "X-MS-Office365-Filtering-Correlation-Id": "a9b1553b-42bd-4928-172c-08dbda1da7a1", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n oks3NSJKjvR7iawyxLsKxsE52r/R+AUpvw2UJgFvOUOkpFda9aqSyBg7nLmLiiwE1T/SWO9KkMl0XjqNK0cAZbxS+SkhwLpmlNMCs0XURogvnLsi3ovNKKkfTIu1Zh7xjNNuHQjEUPAyjzMND5QhNa24EBeFtyaqA2H5Ce4KF4zpgYr+EXcbq480rfTxXQsDGfd/Pg3D5FInXouZcWgofdIk050OigXjEGZd9MpZ+CZFNEISOkUuXXtngVmw+cCiSRbDxB2L6g6gdxNe+QD/LdrkO1XDIc+Eo4zPGZfzlWU+XlKHqPn0mJhm5aHzpGuUPwjrHGL5JaQ6PpdlSvMm1zav5Be5IG9JDV36E0Pig9UyekPwpUL0o4AJQLcclclTwmZe8O6H1QGv+ljRRAcPRLICCgvD0ESpZfdBIaYThIKq5H4ssKDFA/4ToAyj2abBY3Ulqop5cSwJIiQ2Pwr0oRXWIMMh08W523HkLF4IhuyREbb8r74zny8NzfRCJzp6KH4D1ZA3pUP4u+jkiJoxFXh5EoDKiYBuJJSDV9jM4OEW7vLhGANtUWJrO002t4KKLyTdYpEw0RqGFfKwCM0ixUWnNlpexOxCdDjct9dP7y57N5N8TPaD1mxYqAUnc5+v/RiuH13ua1MullNaIVqBA6O+YHeEiGmTTEA/qoztazUd/cJnB+zt+N9zhlt71m5syj+bP+KjKZ2kubG422QUX+hdDDWz8SMTbRFQoYYTp1JYY1camMgBDyyCfu5l2w9t", "X-Forefront-Antispam-Report": "CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE;\n SFS:(13230031)(4636009)(346002)(396003)(376002)(136003)(39860400002)(230922051799003)(1800799009)(82310400011)(451199024)(186009)(64100799003)(40470700004)(36840700001)(46966006)(2906002)(40460700003)(40480700001)(478600001)(55016003)(6666004)(2616005)(107886003)(1076003)(16526019)(6286002)(26005)(426003)(336012)(82740400003)(47076005)(7636003)(356005)(36756003)(83380400001)(86362001)(36860700001)(7696005)(54906003)(110136005)(41300700001)(6636002)(316002)(70586007)(70206006)(5660300002)(8936002)(8676002)(4326008);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "31 Oct 2023 14:28:30.2753 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n a9b1553b-42bd-4928-172c-08dbda1da7a1", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n MWH0EPF000971E6.namprd02.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "CH3PR12MB8535", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "This patch changes the behavior of the comparator used to\nsort mlx5_dev_spawn_data structures, to put them in a more\nuser friendly order\n\nBefore this patch, ports were sorted assuming there is\nonly a single master port. It resulted in an order where\nmaster port first comes second, then representors in ascending\norder of IDs.\n\nThis approach however is not desirable with devices configured\nfor Multiport E-Switch, since uplink ports which do not correspond\nto the owning PCI device are representors as well and they will be\nmixed with VF/SF representors.\n\nTo change that, this patch amends the comparator to force uplink ports\nto be first. If there are many uplink ports, the master port will\ncome first and the rest will be sorted by port index.\n\nSigned-off-by: Dariusz Sosnowski <dsosnowski@nvidia.com>\nAcked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>\n---\n drivers/net/mlx5/linux/mlx5_os.c | 8 +++++++-\n 1 file changed, 7 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c\nindex 8ddf38288e..07f31de5ae 100644\n--- a/drivers/net/mlx5/linux/mlx5_os.c\n+++ b/drivers/net/mlx5/linux/mlx5_os.c\n@@ -1797,9 +1797,15 @@ mlx5_dev_spawn_data_cmp(const void *a, const void *b)\n \t\t&((const struct mlx5_dev_spawn_data *)a)->info;\n \tconst struct mlx5_switch_info *si_b =\n \t\t&((const struct mlx5_dev_spawn_data *)b)->info;\n+\tint uplink_a = si_a->name_type == MLX5_PHYS_PORT_NAME_TYPE_UPLINK;\n+\tint uplink_b = si_b->name_type == MLX5_PHYS_PORT_NAME_TYPE_UPLINK;\n \tint ret;\n \n-\t/* Master device first. */\n+\t/* Uplink ports first. */\n+\tret = uplink_b - uplink_a;\n+\tif (ret)\n+\t\treturn ret;\n+\t/* Then master devices. */\n \tret = si_b->master - si_a->master;\n \tif (ret)\n \t\treturn ret;\n", "prefixes": [ "7/8" ] }