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GET /api/patches/134450/?format=api
{ "id": 134450, "url": "http://patchwork.dpdk.org/api/patches/134450/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20231117123744.592459-1-venkatx.sivaramakrishnan@intel.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20231117123744.592459-1-venkatx.sivaramakrishnan@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20231117123744.592459-1-venkatx.sivaramakrishnan@intel.com", "date": "2023-11-17T12:37:44", "name": "[v2] crypto/qat: fix block cipher misalignment for AES CBC and 3DES CBC", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "b662091872c68a9e1fc5e63cec9b5a622dc35d28", "submitter": { "id": 3155, "url": "http://patchwork.dpdk.org/api/people/3155/?format=api", "name": "Sivaramakrishnan Venkat", "email": "venkatx.sivaramakrishnan@intel.com" }, "delegate": { "id": 6690, "url": "http://patchwork.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20231117123744.592459-1-venkatx.sivaramakrishnan@intel.com/mbox/", "series": [ { "id": 30327, "url": "http://patchwork.dpdk.org/api/series/30327/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=30327", "date": "2023-11-17T12:37:44", "name": "[v2] crypto/qat: fix block cipher misalignment for AES CBC and 3DES CBC", "version": 2, "mbox": "http://patchwork.dpdk.org/series/30327/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/134450/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/134450/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 2C91643354;\n\tFri, 17 Nov 2023 13:37:55 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id B0C7240ED1;\n\tFri, 17 Nov 2023 13:37:54 +0100 (CET)", "from mgamail.intel.com (mgamail.intel.com [134.134.136.100])\n by mails.dpdk.org (Postfix) with ESMTP id 1662C40648;\n Fri, 17 Nov 2023 13:37:51 +0100 (CET)", "from fmviesa001.fm.intel.com ([10.60.135.141])\n by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 17 Nov 2023 04:37:49 -0800", "from silpixa00400902.ir.intel.com ([10.243.23.146])\n by fmviesa001.fm.intel.com with ESMTP; 17 Nov 2023 04:37:48 -0800" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1700224672; x=1731760672;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=/tzuxuyWLJPTOXyCj5GeXCtaP7fD5PpjJcTfpV6WgPA=;\n b=G8wFyesM/QnV56a1LnF0HDJ2VRQovZk/EHGVS4+RLnIYdpVnfow7+4A7\n uNYTe1qKBbsLNM+JPvT8Ok1Tm7BdDtqv0R7SPFdinsoHz3rAi9GNY3KaR\n y3XJ+l2P1Y3ZgJTEcLzO7t000azEnEzaTs9xS9+TUKNi24p4S2UKjiAO2\n F5bfRMIMgA3zsc3812I8vmRuFNNeatqza1qGD4t/covvxioKVNpBDpiyp\n wm8zWUSzMjrsJZKCcwEoCFFMKwSekka0HqQePUPBlQ7qSPECJAmEMhfRV\n XVq+rqVfDd8fMkpAzInr47m8m2GRN63ujLIPB/d/o/DiOrrx+21oHfRHr Q==;", "X-IronPort-AV": [ "E=McAfee;i=\"6600,9927,10896\"; a=\"457790495\"", "E=Sophos;i=\"6.04,206,1695711600\"; d=\"scan'208\";a=\"457790495\"", "E=Sophos;i=\"6.04,206,1695711600\"; d=\"scan'208\";a=\"13916851\"" ], "X-ExtLoop1": "1", "From": "Sivaramakrishnan Venkat <venkatx.sivaramakrishnan@intel.com>", "To": "dev@dpdk.org", "Cc": "stable@dpdk.org, kai.ji@intel.com, gakhil@marvell.com,\n Sivaramakrishnan Venkat <venkatx.sivaramakrishnan@intel.com>", "Subject": "[PATCH v2] crypto/qat: fix block cipher misalignment for AES CBC and\n 3DES CBC", "Date": "Fri, 17 Nov 2023 12:37:44 +0000", "Message-Id": "<20231117123744.592459-1-venkatx.sivaramakrishnan@intel.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20231103133037.782512-1-venkatx.sivaramakrishnan@intel.com>", "References": "<20231103133037.782512-1-venkatx.sivaramakrishnan@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "check cipher length alignment for 3DES CBC and AES CBC\nto change it to NULL service type for buffer misalignment.\n\nFixes: def38073ac90 (\"crypto/qat: check cipher buffer alignment\")\nCc: stable@dpdk.org\n\nSigned-off-by: Sivaramakrishnan Venkat <venkatx.sivaramakrishnan@intel.com>\nAcked-by: Kai Ji <kai.ji@intel.com>\n---\nv2:\n Dropped new tests patch.\n Removed settings reponse header directly.\n Cleared cookie status instead of setting to SUCCESS.\n---\n drivers/crypto/qat/dev/qat_crypto_pmd_gens.h | 27 +++++++++++++++-----\n drivers/crypto/qat/dev/qat_sym_pmd_gen1.c | 12 ++++-----\n drivers/crypto/qat/qat_sym.h | 8 ++++++\n 3 files changed, 34 insertions(+), 13 deletions(-)", "diff": "diff --git a/drivers/crypto/qat/dev/qat_crypto_pmd_gens.h b/drivers/crypto/qat/dev/qat_crypto_pmd_gens.h\nindex eebf2e6eb8..b8ddf42d6f 100644\n--- a/drivers/crypto/qat/dev/qat_crypto_pmd_gens.h\n+++ b/drivers/crypto/qat/dev/qat_crypto_pmd_gens.h\n@@ -618,7 +618,8 @@ static __rte_always_inline void\n enqueue_one_cipher_job_gen1(struct qat_sym_session *ctx,\n \tstruct icp_qat_fw_la_bulk_req *req,\n \tstruct rte_crypto_va_iova_ptr *iv,\n-\tunion rte_crypto_sym_ofs ofs, uint32_t data_len)\n+\tunion rte_crypto_sym_ofs ofs, uint32_t data_len,\n+\tstruct qat_sym_op_cookie *cookie)\n {\n \tstruct icp_qat_fw_la_cipher_req_params *cipher_param;\n \n@@ -629,6 +630,15 @@ enqueue_one_cipher_job_gen1(struct qat_sym_session *ctx,\n \tcipher_param->cipher_offset = ofs.ofs.cipher.head;\n \tcipher_param->cipher_length = data_len - ofs.ofs.cipher.head -\n \t\t\tofs.ofs.cipher.tail;\n+\n+\tif (AES_OR_3DES_MISALIGNED) {\n+\t\tQAT_LOG(DEBUG,\n+\t \"Input cipher buffer misalignment detected and change job as NULL operation\");\n+\t\tstruct icp_qat_fw_comn_req_hdr *header = &req->comn_hdr;\n+\t\theader->service_type = ICP_QAT_FW_COMN_REQ_NULL;\n+\t\theader->service_cmd_id = ICP_QAT_FW_NULL_REQ_SERV_ID;\n+\t\tcookie->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;\n+\t}\n }\n \n static __rte_always_inline void\n@@ -685,7 +695,8 @@ enqueue_one_chain_job_gen1(struct qat_sym_session *ctx,\n \tstruct rte_crypto_va_iova_ptr *cipher_iv,\n \tstruct rte_crypto_va_iova_ptr *digest,\n \tstruct rte_crypto_va_iova_ptr *auth_iv,\n-\tunion rte_crypto_sym_ofs ofs, uint32_t data_len)\n+\tunion rte_crypto_sym_ofs ofs, uint32_t data_len,\n+\tstruct qat_sym_op_cookie *cookie)\n {\n \tstruct icp_qat_fw_la_cipher_req_params *cipher_param;\n \tstruct icp_qat_fw_la_auth_req_params *auth_param;\n@@ -722,11 +733,13 @@ enqueue_one_chain_job_gen1(struct qat_sym_session *ctx,\n \t * error detected.\n \t */\n \tif (AES_OR_3DES_MISALIGNED) {\n-\t\tQAT_LOG(ERR, \"Input cipher length alignment error detected.\\n\");\n-\t\tctx->qat_cipher_alg = ICP_QAT_HW_CIPHER_ALGO_NULL;\n-\t\tctx->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_NULL;\n-\t\tcipher_param->cipher_length = 0;\n-\t\tauth_param->auth_len = 0;\n+\t\tQAT_LOG(DEBUG,\n+\t \"Input cipher buffer misalignment detected and change job as NULL operation\");\n+\t\tstruct icp_qat_fw_comn_req_hdr *header = &req->comn_hdr;\n+\t\theader->service_type = ICP_QAT_FW_COMN_REQ_NULL;\n+\t\theader->service_cmd_id = ICP_QAT_FW_NULL_REQ_SERV_ID;\n+\t\tcookie->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;\n+\t\treturn -1;\n \t}\n \n \tswitch (ctx->qat_hash_alg) {\ndiff --git a/drivers/crypto/qat/dev/qat_sym_pmd_gen1.c b/drivers/crypto/qat/dev/qat_sym_pmd_gen1.c\nindex e4bcfa59e7..208b7e0ba6 100644\n--- a/drivers/crypto/qat/dev/qat_sym_pmd_gen1.c\n+++ b/drivers/crypto/qat/dev/qat_sym_pmd_gen1.c\n@@ -248,7 +248,7 @@ qat_sym_build_op_cipher_gen1(void *in_op, struct qat_sym_session *ctx,\n \t\treturn -EINVAL;\n \t}\n \n-\tenqueue_one_cipher_job_gen1(ctx, req, &cipher_iv, ofs, total_len);\n+\tenqueue_one_cipher_job_gen1(ctx, req, &cipher_iv, ofs, total_len, op_cookie);\n \n \tqat_sym_debug_log_dump(req, ctx, in_sgl.vec, in_sgl.num, &cipher_iv,\n \t\t\tNULL, NULL, NULL);\n@@ -383,7 +383,7 @@ qat_sym_build_op_chain_gen1(void *in_op, struct qat_sym_session *ctx,\n \n \tenqueue_one_chain_job_gen1(ctx, req, in_sgl.vec, in_sgl.num,\n \t\t\tout_sgl.vec, out_sgl.num, &cipher_iv, &digest, &auth_iv,\n-\t\t\tofs, total_len);\n+\t\t\tofs, total_len, cookie);\n \n \tqat_sym_debug_log_dump(req, ctx, in_sgl.vec, in_sgl.num, &cipher_iv,\n \t\t\t&auth_iv, NULL, &digest);\n@@ -507,7 +507,7 @@ qat_sym_dp_enqueue_single_cipher_gen1(void *qp_data, uint8_t *drv_ctx,\n \tif (unlikely(data_len < 0))\n \t\treturn -1;\n \n-\tenqueue_one_cipher_job_gen1(ctx, req, iv, ofs, (uint32_t)data_len);\n+\tenqueue_one_cipher_job_gen1(ctx, req, iv, ofs, (uint32_t)data_len, cookie);\n \n \tqat_sym_debug_log_dump(req, ctx, data, n_data_vecs, iv,\n \t\t\tNULL, NULL, NULL);\n@@ -564,7 +564,7 @@ qat_sym_dp_enqueue_cipher_jobs_gen1(void *qp_data, uint8_t *drv_ctx,\n \t\tif (unlikely(data_len < 0))\n \t\t\tbreak;\n \t\tenqueue_one_cipher_job_gen1(ctx, req, &vec->iv[i], ofs,\n-\t\t\t(uint32_t)data_len);\n+\t\t\t(uint32_t)data_len, cookie);\n \t\ttail = (tail + tx_queue->msg_size) & tx_queue->modulo_mask;\n \n \t\tqat_sym_debug_log_dump(req, ctx, vec->src_sgl[i].vec,\n@@ -740,7 +740,7 @@ qat_sym_dp_enqueue_single_chain_gen1(void *qp_data, uint8_t *drv_ctx,\n \n \tif (unlikely(enqueue_one_chain_job_gen1(ctx, req, data, n_data_vecs,\n \t\t\tNULL, 0, cipher_iv, job_digest, auth_iv, ofs,\n-\t\t\t(uint32_t)data_len)))\n+\t\t\t(uint32_t)data_len, cookie)))\n \t\treturn -1;\n \n \tdp_ctx->tail = tail;\n@@ -811,7 +811,7 @@ qat_sym_dp_enqueue_chain_jobs_gen1(void *qp_data, uint8_t *drv_ctx,\n \t\t\t\tvec->src_sgl[i].vec, vec->src_sgl[i].num,\n \t\t\t\tNULL, 0,\n \t\t\t\t&vec->iv[i], job_digest,\n-\t\t\t\t&vec->auth_iv[i], ofs, (uint32_t)data_len)))\n+\t\t\t\t&vec->auth_iv[i], ofs, (uint32_t)data_len, cookie)))\n \t\t\tbreak;\n \n \t\ttail = (tail + tx_queue->msg_size) & tx_queue->modulo_mask;\ndiff --git a/drivers/crypto/qat/qat_sym.h b/drivers/crypto/qat/qat_sym.h\nindex b4e19e3015..71e9d5f34b 100644\n--- a/drivers/crypto/qat/qat_sym.h\n+++ b/drivers/crypto/qat/qat_sym.h\n@@ -117,6 +117,7 @@ struct qat_sym_op_cookie {\n \t} opt;\n \tuint8_t digest_null[4];\n \tphys_addr_t digest_null_phys_addr;\n+\tenum rte_crypto_op_status status;\n };\n \n struct qat_sym_dp_ctx {\n@@ -321,6 +322,7 @@ qat_sym_process_response(void **op, uint8_t *resp, void *op_cookie,\n \t\t\t(resp_msg->opaque_data);\n \tstruct qat_sym_session *sess;\n \tuint8_t is_docsis_sec;\n+\tstruct qat_sym_op_cookie *cookie = NULL;\n \n #if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG\n \tQAT_DP_HEXDUMP_LOG(DEBUG, \"qat_response:\", (uint8_t *)resp_msg,\n@@ -366,6 +368,12 @@ qat_sym_process_response(void **op, uint8_t *resp, void *op_cookie,\n \t\t\t\tsess->auth_key_length);\n \t}\n \n+\tcookie = (struct qat_sym_op_cookie *) op_cookie;\n+\tif (cookie->status == RTE_CRYPTO_OP_STATUS_INVALID_ARGS) {\n+\t\trx_op->status = cookie->status;\n+\t\tcookie->status = 0;\n+\t}\n+\n \t*op = (void *)rx_op;\n \n \t/*\n", "prefixes": [ "v2" ] }