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GET /api/patches/135280/?format=api
{ "id": 135280, "url": "http://patchwork.dpdk.org/api/patches/135280/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20231218134142.84397-2-arkadiuszx.kusztal@intel.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20231218134142.84397-2-arkadiuszx.kusztal@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20231218134142.84397-2-arkadiuszx.kusztal@intel.com", "date": "2023-12-18T13:41:42", "name": "[2/2] common/qat: add vqat confiuration macros", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "b187ff7816261bab39b9c66dd63ab587eafc41a0", "submitter": { "id": 452, "url": "http://patchwork.dpdk.org/api/people/452/?format=api", "name": "Arkadiusz Kusztal", "email": "arkadiuszx.kusztal@intel.com" }, "delegate": { "id": 6690, "url": "http://patchwork.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20231218134142.84397-2-arkadiuszx.kusztal@intel.com/mbox/", "series": [ { "id": 30590, "url": "http://patchwork.dpdk.org/api/series/30590/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=30590", "date": "2023-12-18T13:41:41", "name": "[1/2] common/qat: add vqat definition to pmd map", "version": 1, "mbox": "http://patchwork.dpdk.org/series/30590/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/135280/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/135280/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 45D0343735;\n\tMon, 18 Dec 2023 15:53:37 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 902A4427DF;\n\tMon, 18 Dec 2023 15:53:33 +0100 (CET)", "from mgamail.intel.com (mgamail.intel.com [198.175.65.12])\n by mails.dpdk.org (Postfix) with ESMTP id 1AC6C427DC\n for <dev@dpdk.org>; Mon, 18 Dec 2023 15:53:31 +0100 (CET)", "from fmsmga006.fm.intel.com ([10.253.24.20])\n by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 18 Dec 2023 06:53:31 -0800", "from silpixa00399302.ir.intel.com ([10.237.214.136])\n by fmsmga006.fm.intel.com with ESMTP; 18 Dec 2023 06:53:29 -0800" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1702911212; x=1734447212;\n h=from:to:cc:subject:date:message-id:in-reply-to: references;\n bh=ZM9ySOjjEXYKdSWCoWoDb/z6eTAe6i2lWnXjh1qr0JM=;\n b=BaCKjqh/9k0RLYM3HQLzAsq8haJs7zAkv+HyFeEWovrJ5O89BdCqRQVA\n Fh/nfzSFOHp/S5dZfGb0stVktBP9gOUN4NdpfCjJ1L8mjvdHqFyBeazJj\n TN742rhPjV6utkQO1Zy6KqeAQhI+xCVA70vVzaNQpOeOLy7YyUgTdLdM1\n rAQkmFQEyo4y2+vXRZCzVJHknqvWgcRCQSSpggd2SSOfDFb1//EzTAGkg\n W1mlezvsFQaSX5dt/BxxnU22vbPznMkRrVZkuVc8dZFK8BMY9h1+a2R70\n P0xVPWRnOoTMv3mAD28j3r1pFJvH1Zmx6MJn5Y45eVv8xp8rEOgjsym+9 A==;", "X-IronPort-AV": [ "E=McAfee;i=\"6600,9927,10928\"; a=\"2725517\"", "E=Sophos;i=\"6.04,285,1695711600\";\n d=\"scan'208\";a=\"2725517\"", "E=McAfee;i=\"6600,9927,10928\"; a=\"1022776803\"", "E=Sophos;i=\"6.04,285,1695711600\"; d=\"scan'208\";a=\"1022776803\"" ], "X-ExtLoop1": "1", "From": "Arkadiusz Kusztal <arkadiuszx.kusztal@intel.com>", "To": "dev@dpdk.org", "Cc": "gakhil@marvell.com, kai.ji@intel.com, ciara.power@intel.com,\n Arkadiusz Kusztal <arkadiuszx.kusztal@intel.com>", "Subject": "[PATCH 2/2] common/qat: add vqat confiuration macros", "Date": "Mon, 18 Dec 2023 13:41:42 +0000", "Message-Id": "<20231218134142.84397-2-arkadiuszx.kusztal@intel.com>", "X-Mailer": "git-send-email 2.13.6", "In-Reply-To": "<20231218134142.84397-1-arkadiuszx.kusztal@intel.com>", "References": "<20231218134142.84397-1-arkadiuszx.kusztal@intel.com>", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "This commit adds vqat (virtual QAT device) configuration\nmacros to the Intel QuickAssist Technology PMD.\n\nSigned-off-by: Arkadiusz Kusztal <arkadiuszx.kusztal@intel.com>\n---\n .../qat/qat_adf/adf_transport_access_macros_vqat.h | 82 ++++++++++++++++++++++\n 1 file changed, 82 insertions(+)\n create mode 100644 drivers/common/qat/qat_adf/adf_transport_access_macros_vqat.h", "diff": "diff --git a/drivers/common/qat/qat_adf/adf_transport_access_macros_vqat.h b/drivers/common/qat/qat_adf/adf_transport_access_macros_vqat.h\nnew file mode 100644\nindex 0000000000..9acf7c614d\n--- /dev/null\n+++ b/drivers/common/qat/qat_adf/adf_transport_access_macros_vqat.h\n@@ -0,0 +1,82 @@\n+/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)\n+ * Copyright(c) 2023 Intel Corporation\n+ */\n+\n+#ifndef ADF_TRANSPORT_ACCESS_MACROS_VQAT_H\n+#define ADF_TRANSPORT_ACCESS_MACROS_VQAT_H\n+\n+#define ADF_RINGS_PER_INT_SRCSEL_VQAT 2\n+#define ADF_BANK_INT_SRC_SEL_MASK_VQAT 0x44UL\n+#define ADF_BANK_INT_FLAG_CLEAR_MASK_VQAT 0x3\n+#define ADF_RING_BUNDLE_SIZE_VQAT 0x2000\n+#define ADF_RING_CSR_ADDR_OFFSET_VQAT 0x0\n+#define ADF_RING_CSR_RING_CONFIG_VQAT ADF_VQAT_R0_CONFIG\n+#define ADF_RING_CSR_RING_LBASE_VQAT ADF_VQAT_R0_LBASE\n+#define ADF_RING_CSR_RING_UBASE_VQAT ADF_VQAT_R0_UBASE\n+#define ADF_RING_CSR_RP_IDX_TX 0\n+#define ADF_RING_CSR_RP_IDX_RX 1\n+\n+#define BUILD_RING_BASE_ADDR_VQAT(addr, size) \\\n+\t((((addr) >> 6) & (0xFFFFFFFFFFFFFFFFULL << (size))) << 6)\n+#define READ_CSR_RING_HEAD_VQAT(csr_base_addr, bank, ring) \\\n+\tADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET_VQAT, \\\n+\t\t(ADF_RING_BUNDLE_SIZE_VQAT * (bank)) + \\\n+\t\tADF_RING_CSR_RING_HEAD + ((ring) << 2))\n+#define READ_CSR_RING_TAIL_VQAT(csr_base_addr, bank, ring) \\\n+\tADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET_VQAT, \\\n+\t\t(ADF_RING_BUNDLE_SIZE_VQAT * (bank)) + \\\n+\t\tADF_RING_CSR_RING_TAIL + ((ring) << 2))\n+#define READ_CSR_STAT_VQAT(csr_base_addr, bank) \\\n+\tADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET_VQAT, \\\n+\t\t(ADF_RING_BUNDLE_SIZE_VQAT * (bank)) + \\\n+\t\tADF_RING_CSR_STAT)\n+#define READ_CSR_UO_STAT_VQAT(csr_base_addr, bank) \\\n+\tADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET_VQAT, \\\n+\t\t(ADF_RING_BUNDLE_SIZE_VQAT * (bank)) + \\\n+\t\tADF_RING_CSR_UO_STAT)\n+#define READ_CSR_E_STAT_VQAT(csr_base_addr, bank) \\\n+\tADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET_VQAT, \\\n+\t\t(ADF_RING_BUNDLE_SIZE_VQAT * (bank)) + \\\n+\t\tADF_RING_CSR_E_STAT)\n+#define READ_CSR_NE_STAT_VQAT(csr_base_addr, bank) \\\n+\tADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET_VQAT, \\\n+\t\t(ADF_RING_BUNDLE_SIZE_VQAT * (bank)) + \\\n+\t\tADF_RING_CSR_NE_STAT)\n+#define READ_CSR_NF_STAT_VQAT(csr_base_addr, bank) \\\n+\tADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET_VQAT, \\\n+\t\t(ADF_RING_BUNDLE_SIZE_VQAT * (bank)) + \\\n+\t\tADF_RING_CSR_NF_STAT)\n+#define READ_CSR_F_STAT_VQAT(csr_base_addr, bank) \\\n+\tADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET_VQAT, \\\n+\t\t(ADF_RING_BUNDLE_SIZE_VQAT * (bank)) + \\\n+\t\tADF_RING_CSR_F_STAT)\n+#define READ_CSR_C_STAT_VQAT(csr_base_addr, bank) \\\n+\tADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET_VQAT, \\\n+\t\t(ADF_RING_BUNDLE_SIZE_VQAT * (bank)) + \\\n+\t\tADF_RING_CSR_C_STAT)\n+#define READ_CSR_RING_CONFIG_VQAT(csr_base_addr, bank, ring) \\\n+\tADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET_VQAT, \\\n+\t\t(ADF_RING_BUNDLE_SIZE_VQAT * (bank)) + \\\n+\t\tADF_RING_CSR_RING_CONFIG_VQAT + ((ring) << 2))\n+#define WRITE_CSR_RING_CONFIG_VQAT(csr_base_addr, bank, ring, value) \\\n+\tADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET_VQAT, \\\n+\t\t(ADF_RING_BUNDLE_SIZE_VQAT * (bank)) + \\\n+\t\tADF_RING_CSR_RING_CONFIG_VQAT + ((ring) << 2), (value))\n+#define WRITE_CSR_RING_BASE_VQAT(csr_base_addr, bank, ring, value)\t\\\n+do {\t\t\t\t\t\t\t\t\t\\\n+\tvoid __iomem *_csr_base_addr = csr_base_addr;\t\t\t\\\n+\tu32 _bank = bank;\t\t\t\t\t\t\\\n+\tu32 _ring = ring;\t\t\t\t\t\t\\\n+\tdma_addr_t _value = value;\t\t\t\t\t\\\n+\tu32 l_base = 0, u_base = 0;\t\t\t\t\t\\\n+\tl_base = (u32)((_value) & 0xFFFFFFFF);\t\t\t\t\\\n+\tu_base = (u32)(((_value) & 0xFFFFFFFF00000000ULL) >> 32);\t\\\n+\tADF_CSR_WR((_csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET_VQAT,\t\\\n+\t\t(ADF_RING_BUNDLE_SIZE_VQAT * (_bank)) +\t\t\t\\\n+\t\tADF_RING_CSR_RING_LBASE_VQAT + ((_ring) << 2), l_base);\t\\\n+\tADF_CSR_WR((_csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET_VQAT,\t\\\n+\t\t(ADF_RING_BUNDLE_SIZE_VQAT * (_bank)) +\t\t\t\\\n+\t\tADF_RING_CSR_RING_UBASE_VQAT + ((_ring) << 2), u_base);\t\\\n+} while (0)\n+\n+#endif\n", "prefixes": [ "2/2" ] }