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GET /api/patches/135395/?format=api
{ "id": 135395, "url": "http://patchwork.dpdk.org/api/patches/135395/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20231220132616.318983-2-nishikanta.nayak@intel.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20231220132616.318983-2-nishikanta.nayak@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20231220132616.318983-2-nishikanta.nayak@intel.com", "date": "2023-12-20T13:26:14", "name": "[2/4] common/qat: update common driver to support GEN5", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "9fdb8d7bc76f44b42d5625c1a8393dcc8fa9267e", "submitter": { "id": 3253, "url": "http://patchwork.dpdk.org/api/people/3253/?format=api", "name": "Nayak, Nishikanta", "email": "nishikanta.nayak@intel.com" }, "delegate": { "id": 6690, "url": "http://patchwork.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20231220132616.318983-2-nishikanta.nayak@intel.com/mbox/", "series": [ { "id": 30630, "url": "http://patchwork.dpdk.org/api/series/30630/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=30630", "date": "2023-12-20T13:26:13", "name": "[1/4] common/qat: add files specific to GEN5", "version": 1, "mbox": "http://patchwork.dpdk.org/series/30630/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/135395/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/135395/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 1389C4374A;\n\tWed, 20 Dec 2023 14:26:58 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 8627E410EE;\n\tWed, 20 Dec 2023 14:26:52 +0100 (CET)", "from mgamail.intel.com (mgamail.intel.com [134.134.136.126])\n by mails.dpdk.org (Postfix) with ESMTP id 4BF644021F\n for <dev@dpdk.org>; Wed, 20 Dec 2023 14:26:49 +0100 (CET)", "from fmsmga008.fm.intel.com ([10.253.24.58])\n by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 20 Dec 2023 05:26:48 -0800", "from silpixa00400355.ir.intel.com (HELO\n silpixa00400355.ger.corp.intel.com) ([10.237.222.80])\n by fmsmga008.fm.intel.com with ESMTP; 20 Dec 2023 05:26:47 -0800" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1703078809; x=1734614809;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=vXNVeSUb+slx32luvo6A51kf9HytgOdY/+lTWOoJHII=;\n b=S7SBgFIPXI2MBycqMOBM5df45u70FFwFNkt21i2dtNqlhqYBUpn36hce\n 6xVRdmb11XAwcdSsstSJpYiL0GTixXSCgpmhRqnjXYDfZBgrIg1OZIVjh\n DdNhm6KZ0dvJrQfbfNrWVuJaz8Xam0blYOJaBkpaWUcAt0h29xm8XLilA\n a3dfrFiVoEMNyBodO2pWGlIxn9Eyjvc3DY5hD8cUM7jnca2AlCv7AgnEZ\n rHgAPwLJnfZcfwMdTahaPmRS9uhrfaV1u4622/2AeVJzaq2Z16om33QxU\n 7UopjGGG907eHwJvMjGDVT7A0IPFEqKeAiPqZqL2irtcgo0FN+ginA6xX Q==;", "X-IronPort-AV": [ "E=McAfee;i=\"6600,9927,10929\"; a=\"380801525\"", "E=Sophos;i=\"6.04,291,1695711600\"; d=\"scan'208\";a=\"380801525\"", "E=McAfee;i=\"6600,9927,10929\"; a=\"842276266\"", "E=Sophos;i=\"6.04,291,1695711600\"; d=\"scan'208\";a=\"842276266\"" ], "X-ExtLoop1": "1", "From": "Nishikant Nayak <nishikanta.nayak@intel.com>", "To": "dev@dpdk.org", "Cc": "kai.ji@intel.com, ciara.power@intel.com, arkadiuszx.kusztal@intel.com,\n Nishikant Nayak <nishikanta.nayak@intel.com>", "Subject": "[PATCH 2/4] common/qat: update common driver to support GEN5", "Date": "Wed, 20 Dec 2023 13:26:14 +0000", "Message-Id": "<20231220132616.318983-2-nishikanta.nayak@intel.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20231220132616.318983-1-nishikanta.nayak@intel.com>", "References": "<20231220132616.318983-1-nishikanta.nayak@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Adding GEN5 specific macros which is required for updating\nthe support for GEN5 features.\nAlso this patch adds other macros which is being used by GEN5\nSpecific APIs.\n\nSigned-off-by: Nishikant Nayak <nishikanta.nayak@intel.com>\n---\n drivers/common/qat/meson.build | 2 +\n .../qat/qat_adf/adf_transport_access_macros.h | 1 +\n drivers/common/qat/qat_adf/icp_qat_fw.h | 27 ++++++++++\n drivers/common/qat/qat_adf/icp_qat_fw_la.h | 51 +++++++++++++++++++\n drivers/common/qat/qat_common.h | 1 +\n drivers/common/qat/qat_device.c | 9 ++++\n 6 files changed, 91 insertions(+)", "diff": "diff --git a/drivers/common/qat/meson.build b/drivers/common/qat/meson.build\nindex 5c36fbb270..35389e5aba 100644\n--- a/drivers/common/qat/meson.build\n+++ b/drivers/common/qat/meson.build\n@@ -82,6 +82,7 @@ sources += files(\n 'dev/qat_dev_gen2.c',\n 'dev/qat_dev_gen3.c',\n 'dev/qat_dev_gen4.c',\n+ 'dev/qat_dev_gen5.c',\n )\n includes += include_directories(\n 'qat_adf',\n@@ -108,6 +109,7 @@ if qat_crypto\n 'dev/qat_crypto_pmd_gen2.c',\n 'dev/qat_crypto_pmd_gen3.c',\n 'dev/qat_crypto_pmd_gen4.c',\n+ 'dev/qat_crypto_pmd_gen5.c',\n ]\n sources += files(join_paths(qat_crypto_relpath, f))\n endforeach\ndiff --git a/drivers/common/qat/qat_adf/adf_transport_access_macros.h b/drivers/common/qat/qat_adf/adf_transport_access_macros.h\nindex 12a7258c60..19bd812419 100644\n--- a/drivers/common/qat/qat_adf/adf_transport_access_macros.h\n+++ b/drivers/common/qat/qat_adf/adf_transport_access_macros.h\n@@ -47,6 +47,7 @@\n #define ADF_RING_SIZE_512 0x03\n #define ADF_RING_SIZE_4K 0x06\n #define ADF_RING_SIZE_16K 0x08\n+#define ADF_RING_SIZE_64K 0x0A\n #define ADF_RING_SIZE_4M 0x10\n #define ADF_MIN_RING_SIZE ADF_RING_SIZE_128\n #define ADF_MAX_RING_SIZE ADF_RING_SIZE_4M\ndiff --git a/drivers/common/qat/qat_adf/icp_qat_fw.h b/drivers/common/qat/qat_adf/icp_qat_fw.h\nindex 3aa17ae041..b06b7ec989 100644\n--- a/drivers/common/qat/qat_adf/icp_qat_fw.h\n+++ b/drivers/common/qat/qat_adf/icp_qat_fw.h\n@@ -123,6 +123,11 @@ struct icp_qat_fw_comn_resp {\n #define ICP_QAT_FW_COMN_NULL_VERSION_FLAG_BITPOS 0\n #define ICP_QAT_FW_COMN_NULL_VERSION_FLAG_MASK 0x1\n \n+/* GEN5 specific Common Header fields */\n+#define ICP_QAT_FW_COMN_DESC_LAYOUT_BITPOS 5\n+#define ICP_QAT_FW_COMN_DESC_LAYOUT_MASK 0x3\n+#define ICP_QAT_FW_COMN_GEN5_DESC_LAYOUT 3\n+\n #define ICP_QAT_FW_COMN_OV_SRV_TYPE_GET(icp_qat_fw_comn_req_hdr_t) \\\n \ticp_qat_fw_comn_req_hdr_t.service_type\n \n@@ -168,6 +173,12 @@ struct icp_qat_fw_comn_resp {\n \t(((valid) & ICP_QAT_FW_COMN_VALID_FLAG_MASK) << \\\n \t ICP_QAT_FW_COMN_VALID_FLAG_BITPOS)\n \n+#define ICP_QAT_FW_COMN_HDR_FLAGS_BUILD_GEN5(valid, desc_layout) \\\n+\t((((valid) & ICP_QAT_FW_COMN_VALID_FLAG_MASK) << \\\n+\tICP_QAT_FW_COMN_VALID_FLAG_BITPOS) | \\\n+\t(((desc_layout) & ICP_QAT_FW_COMN_DESC_LAYOUT_MASK) << \\\n+\tICP_QAT_FW_COMN_DESC_LAYOUT_BITPOS))\n+\n #define QAT_COMN_PTR_TYPE_BITPOS 0\n #define QAT_COMN_PTR_TYPE_MASK 0x1\n #define QAT_COMN_CD_FLD_TYPE_BITPOS 1\n@@ -180,10 +191,20 @@ struct icp_qat_fw_comn_resp {\n #define QAT_COMN_EXT_FLAGS_MASK 0x1\n #define QAT_COMN_EXT_FLAGS_USED 0x1\n \n+/* GEN5 specific Common Request Flags fields */\n+#define QAT_COMN_KEYBUF_USAGE_BITPOS 1\n+#define QAT_COMN_KEYBUF_USAGE_MASK 0x1\n+#define QAT_COMN_KEY_BUFFER_USED 1\n+\n #define ICP_QAT_FW_COMN_FLAGS_BUILD(cdt, ptr) \\\n \t((((cdt) & QAT_COMN_CD_FLD_TYPE_MASK) << QAT_COMN_CD_FLD_TYPE_BITPOS) \\\n \t | (((ptr) & QAT_COMN_PTR_TYPE_MASK) << QAT_COMN_PTR_TYPE_BITPOS))\n \n+#define ICP_QAT_FW_COMN_FLAGS_BUILD_GEN5(ptr, keybuf) \\\n+\t((((ptr) & QAT_COMN_PTR_TYPE_MASK) << QAT_COMN_PTR_TYPE_BITPOS) | \\\n+\t (((keybuf) & QAT_COMN_PTR_TYPE_MASK) << \\\n+\t QAT_COMN_KEYBUF_USAGE_BITPOS))\n+\n #define ICP_QAT_FW_COMN_PTR_TYPE_GET(flags) \\\n \tQAT_FIELD_GET(flags, QAT_COMN_PTR_TYPE_BITPOS, QAT_COMN_PTR_TYPE_MASK)\n \n@@ -249,6 +270,8 @@ struct icp_qat_fw_comn_resp {\n #define QAT_COMN_RESP_CMP_END_OF_LAST_BLK_MASK 0x1\n #define QAT_COMN_RESP_UNSUPPORTED_REQUEST_BITPOS 2\n #define QAT_COMN_RESP_UNSUPPORTED_REQUEST_MASK 0x1\n+#define QAT_COMN_RESP_INVALID_PARAM_BITPOS 1\n+#define QAT_COMN_RESP_INVALID_PARAM_MASK 0x1\n #define QAT_COMN_RESP_XLT_WA_APPLIED_BITPOS 0\n #define QAT_COMN_RESP_XLT_WA_APPLIED_MASK 0x1\n \n@@ -280,6 +303,10 @@ struct icp_qat_fw_comn_resp {\n \tQAT_FIELD_GET(status, QAT_COMN_RESP_UNSUPPORTED_REQUEST_BITPOS, \\\n \tQAT_COMN_RESP_UNSUPPORTED_REQUEST_MASK)\n \n+#define ICP_QAT_FW_COMN_RESP_INVALID_PARAM_STAT_GET(status) \\\n+\tQAT_FIELD_GET(status, QAT_COMN_RESP_INVALID_PARAM_BITPOS, \\\n+\tQAT_COMN_RESP_INVALID_PARAM_MASK)\n+\n #define ICP_QAT_FW_COMN_STATUS_FLAG_OK 0\n #define ICP_QAT_FW_COMN_STATUS_FLAG_ERROR 1\n #define ICP_QAT_FW_COMN_STATUS_CMP_END_OF_LAST_BLK_FLAG_CLR 0\ndiff --git a/drivers/common/qat/qat_adf/icp_qat_fw_la.h b/drivers/common/qat/qat_adf/icp_qat_fw_la.h\nindex 70f0effa62..f61241d12a 100644\n--- a/drivers/common/qat/qat_adf/icp_qat_fw_la.h\n+++ b/drivers/common/qat/qat_adf/icp_qat_fw_la.h\n@@ -22,11 +22,18 @@ enum icp_qat_fw_la_cmd_id {\n \tICP_QAT_FW_LA_CMD_DELIMITER = 18\n };\n \n+/* In GEN5 Command ID 4 corresponds to AEAD */\n+#define ICP_QAT_FW_LA_CMD_AEAD 4\n+\n #define ICP_QAT_FW_LA_ICV_VER_STATUS_PASS ICP_QAT_FW_COMN_STATUS_FLAG_OK\n #define ICP_QAT_FW_LA_ICV_VER_STATUS_FAIL ICP_QAT_FW_COMN_STATUS_FLAG_ERROR\n #define ICP_QAT_FW_LA_TRNG_STATUS_PASS ICP_QAT_FW_COMN_STATUS_FLAG_OK\n #define ICP_QAT_FW_LA_TRNG_STATUS_FAIL ICP_QAT_FW_COMN_STATUS_FLAG_ERROR\n \n+/* GEN5 Hash, HMAC and GCM Verification Status */\n+#define ICP_QAT_FW_LA_VER_STATUS_FAIL ICP_QAT_FW_COMN_STATUS_FLAG_OK\n+\n+\n struct icp_qat_fw_la_bulk_req {\n \tstruct icp_qat_fw_comn_req_hdr comn_hdr;\n \tstruct icp_qat_fw_comn_req_hdr_cd_pars cd_pars;\n@@ -81,6 +88,18 @@ struct icp_qat_fw_la_bulk_req {\n #define ICP_QAT_FW_LA_PARTIAL_END 2\n #define QAT_LA_PARTIAL_BITPOS 0\n #define QAT_LA_PARTIAL_MASK 0x3\n+\n+/* GEN5 specific Crypto Flags fields */\n+#define ICP_QAT_FW_SYM_AEAD_ALGO_BITPOS 6\n+#define ICP_QAT_FW_SYM_AEAD_ALGO_MASK 0x3\n+#define ICP_QAT_FW_SYM_IV_SIZE_BITPOS 9\n+#define ICP_QAT_FW_SYM_IV_SIZE_MASK 0x3\n+#define ICP_QAT_FW_SYM_IV_IN_DESC_BITPOS 11\n+#define ICP_QAT_FW_SYM_IV_IN_DESC_MASK 0x1\n+#define ICP_QAT_FW_SYM_IV_IN_DESC_VALID 1\n+#define ICP_QAT_FW_SYM_DIRECTION_BITPOS 15\n+#define ICP_QAT_FW_SYM_DIRECTION_MASK 0x1\n+\n #define ICP_QAT_FW_LA_FLAGS_BUILD(zuc_proto, gcm_iv_len, auth_rslt, proto, \\\n \tcmp_auth, ret_auth, update_state, \\\n \tciph_iv, ciphcfg, partial) \\\n@@ -188,6 +207,23 @@ struct icp_qat_fw_la_bulk_req {\n \tQAT_FIELD_SET(flags, val, QAT_LA_PARTIAL_BITPOS, \\\n \tQAT_LA_PARTIAL_MASK)\n \n+/* GEN5 specific Crypto Flags operations */\n+#define ICP_QAT_FW_SYM_AEAD_ALGO_SET(flags, val) \\\n+\t\tQAT_FIELD_SET(flags, val, ICP_QAT_FW_SYM_AEAD_ALGO_BITPOS, \\\n+\t\tICP_QAT_FW_SYM_AEAD_ALGO_MASK)\n+\n+#define ICP_QAT_FW_SYM_IV_SIZE_SET(flags, val) \\\n+\t\tQAT_FIELD_SET(flags, val, ICP_QAT_FW_SYM_IV_SIZE_BITPOS, \\\n+\t\tICP_QAT_FW_SYM_IV_SIZE_MASK)\n+\n+#define ICP_QAT_FW_SYM_IV_IN_DESC_FLAG_SET(flags, val) \\\n+\t\tQAT_FIELD_SET(flags, val, ICP_QAT_FW_SYM_IV_IN_DESC_BITPOS, \\\n+\t\tICP_QAT_FW_SYM_IV_IN_DESC_MASK)\n+\n+#define ICP_QAT_FW_SYM_DIR_FLAG_SET(flags, val) \\\n+\t\tQAT_FIELD_SET(flags, val, ICP_QAT_FW_SYM_DIRECTION_BITPOS, \\\n+\t\tICP_QAT_FW_SYM_DIRECTION_MASK)\n+\n #define QAT_FW_LA_MODE2 1\n #define QAT_FW_LA_NO_MODE2 0\n #define QAT_FW_LA_MODE2_MASK 0x1\n@@ -410,4 +446,19 @@ struct icp_qat_fw_la_cipher_20_req_params {\n \tuint8_t spc_auth_res_sz;\n };\n \n+struct icp_qat_fw_la_cipher_30_req_params {\n+\t\tuint32_t spc_aad_sz;\n+\t\tuint8_t cipher_length;\n+\t\tuint8_t reserved[2];\n+\t\tuint8_t spc_auth_res_sz;\n+\t\tunion {\n+\t\t\t\tuint32_t cipher_IV_array[ICP_QAT_FW_NUM_LONGWORDS_4];\n+\t\t\t\tstruct {\n+\t\t\t\t\t\tuint64_t cipher_IV_ptr;\n+\t\t\t\t\t\tuint64_t resrvd1;\n+\t\t\t} s;\n+\n+\t\t} u;\n+};\n+\n #endif\ndiff --git a/drivers/common/qat/qat_common.h b/drivers/common/qat/qat_common.h\nindex 9411a79301..dc48a2e1ee 100644\n--- a/drivers/common/qat/qat_common.h\n+++ b/drivers/common/qat/qat_common.h\n@@ -21,6 +21,7 @@ enum qat_device_gen {\n \tQAT_GEN2,\n \tQAT_GEN3,\n \tQAT_GEN4,\n+\tQAT_GEN5,\n \tQAT_N_GENS\n };\n \ndiff --git a/drivers/common/qat/qat_device.c b/drivers/common/qat/qat_device.c\nindex f55dc3c6f0..d4f5391d12 100644\n--- a/drivers/common/qat/qat_device.c\n+++ b/drivers/common/qat/qat_device.c\n@@ -62,6 +62,12 @@ static const struct rte_pci_id pci_id_qat_map[] = {\n \t\t{\n \t\t\tRTE_PCI_DEVICE(0x8086, 0x4945),\n \t\t},\n+\t\t{\n+\t\t\tRTE_PCI_DEVICE(0x8086, 0x1454), /* GEN5: AVFs */\n+\t\t},\n+\t\t{\n+\t\t\tRTE_PCI_DEVICE(0x8086, 0x1456), /* GEN5: CPF */\n+\t\t},\n \t\t{.device_id = 0},\n };\n \n@@ -199,6 +205,9 @@ pick_gen(const struct rte_pci_device *pci_dev)\n \tcase 0x4943:\n \tcase 0x4945:\n \t\treturn QAT_GEN4;\n+\tcase 0x1454: /* QAT30: AVF */\n+\tcase 0x1456: /* QAT30: CPF-mdev */\n+\t\treturn QAT_GEN5;\n \tdefault:\n \t\tQAT_LOG(ERR, \"Invalid dev_id, can't determine generation\");\n \t\treturn QAT_N_GENS;\n", "prefixes": [ "2/4" ] }