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GET /api/patches/135396/?format=api
{ "id": 135396, "url": "http://patchwork.dpdk.org/api/patches/135396/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20231220132616.318983-3-nishikanta.nayak@intel.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20231220132616.318983-3-nishikanta.nayak@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20231220132616.318983-3-nishikanta.nayak@intel.com", "date": "2023-12-20T13:26:15", "name": "[3/4] crypto/qat: update headers for GEN5 support", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "4c0fd3057127106b0afa9d032de0b2079d2fd40c", "submitter": { "id": 3253, "url": "http://patchwork.dpdk.org/api/people/3253/?format=api", "name": "Nayak, Nishikanta", "email": "nishikanta.nayak@intel.com" }, "delegate": { "id": 6690, "url": "http://patchwork.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20231220132616.318983-3-nishikanta.nayak@intel.com/mbox/", "series": [ { "id": 30630, "url": "http://patchwork.dpdk.org/api/series/30630/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=30630", "date": "2023-12-20T13:26:13", "name": "[1/4] common/qat: add files specific to GEN5", "version": 1, "mbox": "http://patchwork.dpdk.org/series/30630/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/135396/comments/", "check": "warning", "checks": "http://patchwork.dpdk.org/api/patches/135396/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 2C0434374A;\n\tWed, 20 Dec 2023 14:27:04 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id B20A142E59;\n\tWed, 20 Dec 2023 14:26:53 +0100 (CET)", "from mgamail.intel.com (mgamail.intel.com [134.134.136.126])\n by mails.dpdk.org (Postfix) with ESMTP id 0013A4067C\n for <dev@dpdk.org>; Wed, 20 Dec 2023 14:26:51 +0100 (CET)", "from fmsmga008.fm.intel.com ([10.253.24.58])\n by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 20 Dec 2023 05:26:51 -0800", "from silpixa00400355.ir.intel.com (HELO\n silpixa00400355.ger.corp.intel.com) ([10.237.222.80])\n by fmsmga008.fm.intel.com with ESMTP; 20 Dec 2023 05:26:49 -0800" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1703078812; x=1734614812;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=03YcFYIUsrJaKolvBy58JUwOhAPZF98hANTXspdM27I=;\n b=SWNK4t2dxOKmmbdlrJQil6VHZJsgnboSg49AiaXrtl6trMrmAhJR0qW8\n 6TYMZCM4JiZg8YYbx1DL3pVWGOG/MZK5aZ0V6IxeeLjoVY0ArmPI4y1sx\n 7stYTnTOssLH0XISrjAQggRI+it7MvOJUK5QUwmTgQ3x7/QJbCZUFkSdN\n j+JAxCap4Dpvh4TgBn1WoE6SUAWug0nP05EuV5MeGPh7+ArN7p1Vm1MBY\n hRRacFEAJTamYYw+W3mvYwcPBErcfozRi07enQbwPQCesdqbvkVO1TY/I\n UYQ2w40zOBIqYtKm1NQo591oKdfqfxzm8AU09z6OoeG88W4Kay1VFKrdY w==;", "X-IronPort-AV": [ "E=McAfee;i=\"6600,9927,10929\"; a=\"380801533\"", "E=Sophos;i=\"6.04,291,1695711600\"; d=\"scan'208\";a=\"380801533\"", "E=McAfee;i=\"6600,9927,10929\"; a=\"842276293\"", "E=Sophos;i=\"6.04,291,1695711600\"; d=\"scan'208\";a=\"842276293\"" ], "X-ExtLoop1": "1", "From": "Nishikant Nayak <nishikanta.nayak@intel.com>", "To": "dev@dpdk.org", "Cc": "kai.ji@intel.com, ciara.power@intel.com, arkadiuszx.kusztal@intel.com,\n Nishikant Nayak <nishikanta.nayak@intel.com>,\n Akhil Goyal <gakhil@marvell.com>, Fan Zhang <fanzhang.oss@gmail.com>", "Subject": "[PATCH 3/4] crypto/qat: update headers for GEN5 support", "Date": "Wed, 20 Dec 2023 13:26:15 +0000", "Message-Id": "<20231220132616.318983-3-nishikanta.nayak@intel.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20231220132616.318983-1-nishikanta.nayak@intel.com>", "References": "<20231220132616.318983-1-nishikanta.nayak@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "This patch handles the changes required for updating the common\nheader fields specific to GEN5, Also added/updated of the response\nprocessing APIs based on GEN5 requirement.\n\nSigned-off-by: Nishikant Nayak <nishikanta.nayak@intel.com>\n---\n drivers/crypto/qat/qat_sym.c | 10 ++++-\n drivers/crypto/qat/qat_sym.h | 60 +++++++++++++++++++++++++++-\n drivers/crypto/qat/qat_sym_session.c | 52 ++++++++++++++++++++++++\n drivers/crypto/qat/qat_sym_session.h | 5 ++-\n lib/cryptodev/rte_crypto_sym.h | 3 ++\n 5 files changed, 126 insertions(+), 4 deletions(-)", "diff": "diff --git a/drivers/crypto/qat/qat_sym.c b/drivers/crypto/qat/qat_sym.c\nindex 6e03bde841..8fbb8831ab 100644\n--- a/drivers/crypto/qat/qat_sym.c\n+++ b/drivers/crypto/qat/qat_sym.c\n@@ -179,8 +179,14 @@ uint16_t\n qat_sym_dequeue_burst(void *qp, struct rte_crypto_op **ops,\n \t\tuint16_t nb_ops)\n {\n-\treturn qat_dequeue_op_burst(qp, (void **)ops,\n-\t\t\t\tqat_sym_process_response, nb_ops);\n+\tstruct qat_qp *tmp_qp = (struct qat_qp *)qp;\n+\n+\tif (tmp_qp->qat_dev_gen == QAT_GEN5)\n+\t\treturn qat_dequeue_op_burst(qp, (void **)ops,\n+\t\t\t\tqat_sym_process_response_gen5, nb_ops);\n+\telse\n+\t\treturn qat_dequeue_op_burst(qp, (void **)ops,\n+\t\t\t\t\tqat_sym_process_response, nb_ops);\n }\n \n int\ndiff --git a/drivers/crypto/qat/qat_sym.h b/drivers/crypto/qat/qat_sym.h\nindex 71e9d5f34b..7db21fc341 100644\n--- a/drivers/crypto/qat/qat_sym.h\n+++ b/drivers/crypto/qat/qat_sym.h\n@@ -95,6 +95,12 @@\n /* Maximum data length for single pass GMAC: 2^14-1 */\n #define QAT_AES_GMAC_SPC_MAX_SIZE 16383\n \n+/* Digest length for GCM Algo is 16 bytes */\n+#define GCM_256_DIGEST_LEN\t16\n+\n+/* IV length for GCM algo is 12 bytes */\n+#define GCM_IV_LENGTH 12\n+\n struct qat_sym_session;\n \n struct qat_sym_sgl {\n@@ -383,6 +389,52 @@ qat_sym_process_response(void **op, uint8_t *resp, void *op_cookie,\n \treturn 1;\n }\n \n+static __rte_always_inline int\n+qat_sym_process_response_gen5(void **op, uint8_t *resp,\n+\tvoid *op_cookie __rte_unused,\n+\tuint64_t *dequeue_err_count __rte_unused)\n+{\n+\tstruct icp_qat_fw_comn_resp *resp_msg =\n+\t\t(struct icp_qat_fw_comn_resp *)resp;\n+\tstruct rte_crypto_op *rx_op = (struct rte_crypto_op *)(uintptr_t)\n+\t\t(resp_msg->opaque_data);\n+\tstruct qat_sym_session *sess;\n+\n+#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG\n+\tQAT_DP_HEXDUMP_LOG(DEBUG, \"qat_response:\", (uint8_t *)resp_msg,\n+\t\tsizeof(struct icp_qat_fw_comn_resp));\n+#endif\n+\n+\tsess = CRYPTODEV_GET_SYM_SESS_PRIV(rx_op->sym->session);\n+\n+\trx_op->status = RTE_CRYPTO_OP_STATUS_SUCCESS;\n+\n+\tif (ICP_QAT_FW_COMN_STATUS_FLAG_OK !=\n+\t\tICP_QAT_FW_COMN_RESP_UNSUPPORTED_REQUEST_STAT_GET(\n+\t\t\tresp_msg->comn_hdr.comn_status))\n+\t\trx_op->status = RTE_CRYPTO_OP_STATUS_NOT_PROCESSED;\n+\n+\telse if (ICP_QAT_FW_COMN_STATUS_FLAG_OK !=\n+\t\tICP_QAT_FW_COMN_RESP_INVALID_PARAM_STAT_GET(\n+\t\t\tresp_msg->comn_hdr.comn_status))\n+\t\trx_op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;\n+\n+\tif (sess->qat_dir == ICP_QAT_HW_CIPHER_DECRYPT) {\n+\t\tif (ICP_QAT_FW_LA_VER_STATUS_FAIL ==\n+\t\t\tICP_QAT_FW_COMN_RESP_CRYPTO_STAT_GET(\n+\t\t\t\tresp_msg->comn_hdr.comn_status))\n+\t\t\trx_op->status =\tRTE_CRYPTO_OP_STATUS_AUTH_FAILED;\n+\t}\n+\n+\t*op = (void *)rx_op;\n+\n+\t/*\n+\t * return 1 as dequeue op only move on to the next op\n+\t * if one was ready to return to API\n+\t */\n+\treturn 1;\n+}\n+\n int\n qat_sym_configure_dp_ctx(struct rte_cryptodev *dev, uint16_t qp_id,\n \tstruct rte_crypto_raw_dp_ctx *raw_dp_ctx,\n@@ -448,7 +500,13 @@ qat_sym_preprocess_requests(void **ops __rte_unused,\n \n static inline void\n qat_sym_process_response(void **op __rte_unused, uint8_t *resp __rte_unused,\n-\tvoid *op_cookie __rte_unused)\n+\tvoid *op_cookie __rte_unused, uint64_t *dequeue_err_count __rte_unused)\n+{\n+}\n+\n+static inline void\n+qat_sym_process_response_gen5(void **op __rte_unused, uint8_t *resp __rte_unused,\n+\tvoid *op_cookie __rte_unused, uint64_t *dequeue_err_count __rte_unused)\n {\n }\n \ndiff --git a/drivers/crypto/qat/qat_sym_session.c b/drivers/crypto/qat/qat_sym_session.c\nindex 9f4f6c3d93..c97d6509b8 100644\n--- a/drivers/crypto/qat/qat_sym_session.c\n+++ b/drivers/crypto/qat/qat_sym_session.c\n@@ -136,6 +136,9 @@ qat_sym_cd_auth_set(struct qat_sym_session *cdesc,\n static void\n qat_sym_session_init_common_hdr(struct qat_sym_session *session);\n \n+static void\n+qat_sym_session_init_gen5_hdr(struct qat_sym_session *session);\n+\n /* Req/cd init functions */\n \n static void\n@@ -738,6 +741,12 @@ qat_sym_session_set_parameters(struct rte_cryptodev *dev,\n \t\tsession->qat_cmd);\n \t\treturn -ENOTSUP;\n \t}\n+\n+\tif (qat_dev_gen == QAT_GEN5) {\n+\t\tqat_sym_session_init_gen5_hdr(session);\n+\t\treturn 0;\n+\t}\n+\n \tqat_sym_session_finalize(session);\n \n \treturn qat_sym_gen_dev_ops[qat_dev_gen].set_session((void *)dev,\n@@ -1082,6 +1091,12 @@ qat_sym_session_configure_aead(struct rte_cryptodev *dev,\n \t\tif (qat_sym_cd_cipher_set(session,\n \t\t\t\taead_xform->key.data, aead_xform->key.length))\n \t\t\treturn -EINVAL;\n+\n+\t\tif (qat_dev_gen == QAT_GEN5) {\n+\t\t\tsession->auth_key_length = aead_xform->key.length;\n+\t\t\tmemcpy(session->key_array, aead_xform->key.data,\n+\t\t\t\taead_xform->key.length);\n+\t\t}\n \t} else if ((aead_xform->op == RTE_CRYPTO_AEAD_OP_ENCRYPT &&\n \t\t\taead_xform->algo == RTE_CRYPTO_AEAD_AES_GCM) ||\n \t\t\t(aead_xform->op == RTE_CRYPTO_AEAD_OP_DECRYPT &&\n@@ -1970,6 +1985,43 @@ qat_sym_session_init_common_hdr(struct qat_sym_session *session)\n \t\t\t\t\tICP_QAT_FW_LA_NO_DIGEST_IN_BUFFER);\n }\n \n+static void\n+qat_sym_session_init_gen5_hdr(struct qat_sym_session *session)\n+{\n+\tstruct icp_qat_fw_la_bulk_req *req_tmpl = &session->fw_req;\n+\tstruct icp_qat_fw_comn_req_hdr *header = &req_tmpl->comn_hdr;\n+\n+\t/*\n+\t * GEN5 specifies separate command id for AEAD operations but Cryptodev\n+\t * API processes AEAD operations as Single pass Crypto operations.\n+\t * Hence even for GEN5, Session Algo Command ID is CIPHER.\n+\t * Note, however Session Algo Mode is AEAD.\n+\t */\n+\theader->service_cmd_id = ICP_QAT_FW_LA_CMD_AEAD;\n+\theader->service_type = ICP_QAT_FW_COMN_REQ_CPM_FW_LA;\n+\theader->hdr_flags =\n+\tICP_QAT_FW_COMN_HDR_FLAGS_BUILD_GEN5(ICP_QAT_FW_COMN_REQ_FLAG_SET,\n+\t\t\tICP_QAT_FW_COMN_GEN5_DESC_LAYOUT);\n+\theader->comn_req_flags =\n+\t\tICP_QAT_FW_COMN_FLAGS_BUILD_GEN5(QAT_COMN_PTR_TYPE_SGL,\n+\t\t\tQAT_COMN_KEY_BUFFER_USED);\n+\n+\tICP_QAT_FW_SYM_AEAD_ALGO_SET(header->serv_specif_flags,\n+\t\tRTE_CRYPTO_AEAD_AES_GCM_GEN5);\n+\tICP_QAT_FW_SYM_IV_SIZE_SET(header->serv_specif_flags,\n+\t\tICP_QAT_FW_LA_GCM_IV_LEN_12_OCTETS);\n+\tICP_QAT_FW_SYM_IV_IN_DESC_FLAG_SET(header->serv_specif_flags,\n+\t\tICP_QAT_FW_SYM_IV_IN_DESC_VALID);\n+\n+\tif (session->qat_dir == ICP_QAT_HW_CIPHER_DECRYPT) {\n+\t\tICP_QAT_FW_SYM_DIR_FLAG_SET(header->serv_specif_flags,\n+\t\t\tICP_QAT_HW_CIPHER_DECRYPT);\n+\t} else {\n+\t\tICP_QAT_FW_SYM_DIR_FLAG_SET(header->serv_specif_flags,\n+\t\t\tICP_QAT_HW_CIPHER_ENCRYPT);\n+\t}\n+}\n+\n int qat_sym_cd_cipher_set(struct qat_sym_session *cdesc,\n \t\t\t\t\t\tconst uint8_t *cipherkey,\n \t\t\t\t\t\tuint32_t cipherkeylen)\ndiff --git a/drivers/crypto/qat/qat_sym_session.h b/drivers/crypto/qat/qat_sym_session.h\nindex 9209e2e8df..821c53dfbb 100644\n--- a/drivers/crypto/qat/qat_sym_session.h\n+++ b/drivers/crypto/qat/qat_sym_session.h\n@@ -111,7 +111,10 @@ struct qat_sym_session {\n \tenum icp_qat_hw_auth_op auth_op;\n \tenum icp_qat_hw_auth_mode auth_mode;\n \tvoid *bpi_ctx;\n-\tstruct qat_sym_cd cd;\n+\tunion {\n+\t\tstruct qat_sym_cd cd;\n+\t\tuint8_t key_array[32];\n+\t};\n \tuint8_t prefix_state[QAT_PREFIX_TBL_SIZE] __rte_cache_aligned;\n \tuint8_t *cd_cur_ptr;\n \tphys_addr_t cd_paddr;\ndiff --git a/lib/cryptodev/rte_crypto_sym.h b/lib/cryptodev/rte_crypto_sym.h\nindex 53b18b9412..e545b1ba76 100644\n--- a/lib/cryptodev/rte_crypto_sym.h\n+++ b/lib/cryptodev/rte_crypto_sym.h\n@@ -492,6 +492,9 @@ enum rte_crypto_aead_operation {\n \t/**< Verify digest and decrypt */\n };\n \n+/* In GEN5 AEAD AES GCM Algorithm has ID 0 */\n+#define RTE_CRYPTO_AEAD_AES_GCM_GEN5 0\n+\n /** Authentication operation name strings */\n extern const char *\n rte_crypto_aead_operation_strings[];\n", "prefixes": [ "3/4" ] }