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GET /api/patches/135504/?format=api
{ "id": 135504, "url": "http://patchwork.dpdk.org/api/patches/135504/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20231222150553.2695916-1-rushilg@google.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20231222150553.2695916-1-rushilg@google.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20231222150553.2695916-1-rushilg@google.com", "date": "2023-12-22T15:05:53", "name": "net/gve: Enable stats reporting for GQ format", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "77bc97e0c15c565a090502423c3f3c3ba1122c16", "submitter": { "id": 2890, "url": "http://patchwork.dpdk.org/api/people/2890/?format=api", "name": "Rushil Gupta", "email": "rushilg@google.com" }, "delegate": { "id": 319, "url": "http://patchwork.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20231222150553.2695916-1-rushilg@google.com/mbox/", "series": [ { "id": 30657, "url": "http://patchwork.dpdk.org/api/series/30657/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=30657", "date": "2023-12-22T15:05:53", "name": "net/gve: Enable stats reporting for GQ format", "version": 1, "mbox": "http://patchwork.dpdk.org/series/30657/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/135504/comments/", "check": "warning", "checks": "http://patchwork.dpdk.org/api/patches/135504/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 4EC0B43760;\n\tFri, 22 Dec 2023 16:05:58 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id C1B0B402E7;\n\tFri, 22 Dec 2023 16:05:57 +0100 (CET)", "from mail-yb1-f202.google.com (mail-yb1-f202.google.com\n [209.85.219.202])\n by mails.dpdk.org (Postfix) with ESMTP id 35A26402A6\n for <dev@dpdk.org>; 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Fri, 22 Dec\n 2023 07:05:55 -0800 (PST)", "Date": "Fri, 22 Dec 2023 15:05:53 +0000", "Mime-Version": "1.0", "X-Mailer": "git-send-email 2.43.0.472.g3155946c3a-goog", "Message-ID": "<20231222150553.2695916-1-rushilg@google.com>", "Subject": "[PATCH] net/gve: Enable stats reporting for GQ format", "From": "Rushil Gupta <rushilg@google.com>", "To": "qi.z.zhang@intel.com, ferruh.yigit@amd.com", "Cc": "junfeng.guo@intel.com, dev@dpdk.org, Rushil Gupta <rushilg@google.com>,\n Joshua Washington <joshwash@google.com>", "Content-Type": "text/plain; charset=\"UTF-8\"", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Read from shared region to retrieve imissed statistics for GQ.\nTested using `show port xstats <port-id>` in interactive mode.\nThis metric can be triggered by using queues > cores.\n\nSigned-off-by: Rushil Gupta <rushilg@google.com>\nReviewed-by: Joshua Washington <joshwash@google.com>\n---\n drivers/net/gve/base/gve_adminq.h | 11 +++\n drivers/net/gve/gve_ethdev.c | 142 ++++++++++++++++++++++++++++--\n drivers/net/gve/gve_ethdev.h | 20 ++++-\n 3 files changed, 167 insertions(+), 6 deletions(-)", "diff": "diff --git a/drivers/net/gve/base/gve_adminq.h b/drivers/net/gve/base/gve_adminq.h\nindex e30b184913..f05362f85f 100644\n--- a/drivers/net/gve/base/gve_adminq.h\n+++ b/drivers/net/gve/base/gve_adminq.h\n@@ -314,6 +314,17 @@ struct gve_stats_report {\n \n GVE_CHECK_STRUCT_LEN(8, gve_stats_report);\n \n+/* Numbers of gve tx/rx stats in stats report. */\n+#define GVE_TX_STATS_REPORT_NUM 6\n+#define GVE_RX_STATS_REPORT_NUM 2\n+\n+/* Interval to schedule a stats report update, 20000ms. */\n+#define GVE_STATS_REPORT_TIMER_PERIOD 20000\n+\n+/* Numbers of NIC tx/rx stats in stats report. */\n+#define NIC_TX_STATS_REPORT_NUM 0\n+#define NIC_RX_STATS_REPORT_NUM 4\n+\n enum gve_stat_names {\n \t/* stats from gve */\n \tTX_WAKE_CNT\t\t\t= 1,\ndiff --git a/drivers/net/gve/gve_ethdev.c b/drivers/net/gve/gve_ethdev.c\nindex ecd37ff37f..bb535a863f 100644\n--- a/drivers/net/gve/gve_ethdev.c\n+++ b/drivers/net/gve/gve_ethdev.c\n@@ -125,6 +125,73 @@ gve_link_update(struct rte_eth_dev *dev, __rte_unused int wait_to_complete)\n \treturn rte_eth_linkstatus_set(dev, &link);\n }\n \n+static int gve_alloc_stats_report(struct gve_priv *priv,\n+ uint16_t nb_tx_queues, uint16_t nb_rx_queues)\n+{\n+\tchar z_name[RTE_MEMZONE_NAMESIZE];\n+\tint tx_stats_cnt;\n+\tint rx_stats_cnt;\n+\n+\ttx_stats_cnt = (GVE_TX_STATS_REPORT_NUM + NIC_TX_STATS_REPORT_NUM) *\n+\t\tnb_tx_queues;\n+\trx_stats_cnt = (GVE_RX_STATS_REPORT_NUM + NIC_RX_STATS_REPORT_NUM) *\n+\t\tnb_rx_queues;\n+\tpriv->stats_report_len = sizeof(struct gve_stats_report) +\n+\t\tsizeof(struct stats) * (tx_stats_cnt + rx_stats_cnt);\n+\n+\tsnprintf(z_name, sizeof(z_name), \"stats_report_%s\", priv->pci_dev->device.name);\n+\tpriv->stats_report_mem = rte_memzone_reserve_aligned(z_name,\n+\t\t\tpriv->stats_report_len,\n+\t\t\trte_socket_id(),\n+\t\t\tRTE_MEMZONE_IOVA_CONTIG, PAGE_SIZE);\n+\n+\tif (!priv->stats_report_mem)\n+\t\treturn -ENOMEM;\n+\n+\t/* offset by skipping stats written by gve. */\n+\tpriv->stats_start_idx = (GVE_TX_STATS_REPORT_NUM * nb_tx_queues) +\n+\t\t(GVE_RX_STATS_REPORT_NUM * nb_rx_queues);\n+\tpriv->stats_end_idx = priv->stats_start_idx +\n+\t\t(NIC_TX_STATS_REPORT_NUM * nb_tx_queues) +\n+\t\t(NIC_RX_STATS_REPORT_NUM * nb_rx_queues) - 1;\n+\n+\treturn 0;\n+}\n+\n+static void gve_free_stats_report(struct rte_eth_dev *dev)\n+{\n+ struct gve_priv *priv = dev->data->dev_private;\n+ rte_memzone_free(priv->stats_report_mem);\n+}\n+\n+/* Read Rx NIC stats from shared region */\n+static void gve_get_imissed_from_nic(struct rte_eth_dev *dev)\n+{\n+\tstruct gve_stats_report *stats_report;\n+\tstruct gve_rx_queue *rxq;\n+\tstruct gve_priv *priv;\n+\tstruct stats stat;\n+\tint queue_id;\n+\tint stat_id;\n+\tint i;\n+\n+\tpriv = dev->data->dev_private;\n+\tstats_report = (struct gve_stats_report *)\n+\t\tpriv->stats_report_mem->addr;\n+\n+\tfor (i = priv->stats_start_idx; i <= priv->stats_end_idx; i++) {\n+\t\tstat = stats_report->stats[i];\n+\t\tqueue_id = cpu_to_be32(stat.queue_id);\n+\t\trxq = dev->data->rx_queues[queue_id];\n+\t\tif (rxq == NULL)\n+\t\t\tcontinue;\n+\t\tstat_id = cpu_to_be32(stat.stat_name);\n+\t\t/* Update imissed. */\n+\t\tif (stat_id == RX_NO_BUFFERS_POSTED)\n+\t\t\trxq->stats.imissed = cpu_to_be64(stat.value);\n+\t}\n+}\n+\n static int\n gve_start_queues(struct rte_eth_dev *dev)\n {\n@@ -176,6 +243,7 @@ gve_start_queues(struct rte_eth_dev *dev)\n static int\n gve_dev_start(struct rte_eth_dev *dev)\n {\n+\tstruct gve_priv *priv;\n \tint ret;\n \n \tret = gve_start_queues(dev);\n@@ -187,6 +255,27 @@ gve_dev_start(struct rte_eth_dev *dev)\n \tdev->data->dev_started = 1;\n \tgve_link_update(dev, 0);\n \n+\tpriv = dev->data->dev_private;\n+\t/* No stats available yet for Dqo. */\n+\tif (gve_is_gqi(priv))\n+\t{\n+\t\tret = gve_alloc_stats_report(priv,\n+\t\t\t\tdev->data->nb_tx_queues,\n+\t\t\t\tdev->data->nb_rx_queues);\n+\t\tif (ret != 0) {\n+\t\t\tPMD_DRV_LOG(ERR,\n+\t\t\t\t\"Failed to allocate region for stats reporting.\");\n+\t\t\treturn ret;\n+\t\t}\n+\t\tret = gve_adminq_report_stats(priv, priv->stats_report_len,\n+\t\t\t\tpriv->stats_report_mem->iova,\n+\t\t\t\tGVE_STATS_REPORT_TIMER_PERIOD);\n+\t\tif (ret != 0) {\n+\t\t\tPMD_DRV_LOG(ERR, \"gve_adminq_report_stats command failed.\");\n+\t\t\treturn ret;\n+\t\t}\n+\t}\n+\n \treturn 0;\n }\n \n@@ -200,6 +289,9 @@ gve_dev_stop(struct rte_eth_dev *dev)\n \n \tdev->data->dev_started = 0;\n \n+\tif (gve_is_gqi(dev->data->dev_private))\n+\t\tgve_free_stats_report(dev);\n+\n \treturn 0;\n }\n \n@@ -352,6 +444,8 @@ static int\n gve_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)\n {\n \tuint16_t i;\n+\tif (gve_is_gqi(dev->data->dev_private))\n+\t\tgve_get_imissed_from_nic(dev);\n \n \tfor (i = 0; i < dev->data->nb_tx_queues; i++) {\n \t\tstruct gve_tx_queue *txq = dev->data->tx_queues[i];\n@@ -372,6 +466,7 @@ gve_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)\n \t\tstats->ibytes += rxq->stats.bytes;\n \t\tstats->ierrors += rxq->stats.errors;\n \t\tstats->rx_nombuf += rxq->stats.no_mbufs;\n+\t\tstats->imissed += rxq->stats.imissed;\n \t}\n \n \treturn 0;\n@@ -443,6 +538,7 @@ static const struct gve_xstats_name_offset rx_xstats_name_offset[] = {\n \t{ \"errors\", RX_QUEUE_STATS_OFFSET(errors) },\n \t{ \"mbuf_alloc_errors\", RX_QUEUE_STATS_OFFSET(no_mbufs) },\n \t{ \"mbuf_alloc_errors_bulk\", RX_QUEUE_STATS_OFFSET(no_mbufs_bulk) },\n+\t{ \"imissed\", RX_QUEUE_STATS_OFFSET(imissed) },\n };\n \n static int\n@@ -614,17 +710,53 @@ gve_teardown_device_resources(struct gve_priv *priv)\n \tgve_clear_device_resources_ok(priv);\n }\n \n+static uint8_t\n+pci_dev_find_capability(struct rte_pci_device *pdev, int cap)\n+{\n+\tuint8_t pos, id;\n+\tuint16_t ent;\n+\tint loops;\n+\tint ret;\n+\n+\tret = rte_pci_read_config(pdev, &pos, sizeof(pos), PCI_CAPABILITY_LIST);\n+\tif (ret != sizeof(pos))\n+\t\treturn 0;\n+\n+\tloops = (PCI_CFG_SPACE_SIZE - PCI_STD_HEADER_SIZEOF) / PCI_CAP_SIZEOF;\n+\n+\twhile (pos && loops--) {\n+\t\tret = rte_pci_read_config(pdev, &ent, sizeof(ent), pos);\n+\t\tif (ret != sizeof(ent))\n+\t\t\treturn 0;\n+\n+\t\tid = ent & 0xff;\n+\t\tif (id == 0xff)\n+\t\t\tbreak;\n+\n+\t\tif (id == cap)\n+\t\t\treturn pos;\n+\n+\t\tpos = (ent >> 8);\n+\t}\n+\n+\treturn 0;\n+}\n+\n static int\n pci_dev_msix_vec_count(struct rte_pci_device *pdev)\n {\n-\toff_t msix_pos = rte_pci_find_capability(pdev, RTE_PCI_CAP_ID_MSIX);\n+\tuint8_t msix_cap = pci_dev_find_capability(pdev, PCI_CAP_ID_MSIX);\n \tuint16_t control;\n+\tint ret;\n \n-\tif (msix_pos > 0 && rte_pci_read_config(pdev, &control, sizeof(control),\n-\t\t\tmsix_pos + RTE_PCI_MSIX_FLAGS) == sizeof(control))\n-\t\treturn (control & RTE_PCI_MSIX_FLAGS_QSIZE) + 1;\n+\tif (!msix_cap)\n+\t\treturn 0;\n \n-\treturn 0;\n+\tret = rte_pci_read_config(pdev, &control, sizeof(control), msix_cap + PCI_MSIX_FLAGS);\n+\tif (ret != sizeof(control))\n+\t\treturn 0;\n+\n+\treturn (control & PCI_MSIX_FLAGS_QSIZE) + 1;\n }\n \n static int\ndiff --git a/drivers/net/gve/gve_ethdev.h b/drivers/net/gve/gve_ethdev.h\nindex 58d8943e71..0e1bfec871 100644\n--- a/drivers/net/gve/gve_ethdev.h\n+++ b/drivers/net/gve/gve_ethdev.h\n@@ -8,13 +8,25 @@\n #include <ethdev_driver.h>\n #include <ethdev_pci.h>\n #include <rte_ether.h>\n-#include <rte_pci.h>\n \n #include \"base/gve.h\"\n \n /* TODO: this is a workaround to ensure that Tx complq is enough */\n #define DQO_TX_MULTIPLIER 4\n \n+/*\n+ * Following macros are derived from linux/pci_regs.h, however,\n+ * we can't simply include that header here, as there is no such\n+ * file for non-Linux platform.\n+ */\n+#define PCI_CFG_SPACE_SIZE\t256\n+#define PCI_CAPABILITY_LIST\t0x34\t/* Offset of first capability list entry */\n+#define PCI_STD_HEADER_SIZEOF\t64\n+#define PCI_CAP_SIZEOF\t\t4\n+#define PCI_CAP_ID_MSIX\t\t0x11\t/* MSI-X */\n+#define PCI_MSIX_FLAGS\t\t2\t/* Message Control */\n+#define PCI_MSIX_FLAGS_QSIZE\t0x07FF\t/* Table size */\n+\n #define GVE_DEFAULT_RX_FREE_THRESH 64\n #define GVE_DEFAULT_TX_FREE_THRESH 32\n #define GVE_DEFAULT_TX_RS_THRESH 32\n@@ -85,6 +97,7 @@ struct gve_rx_stats {\n \tuint64_t errors;\n \tuint64_t no_mbufs;\n \tuint64_t no_mbufs_bulk;\n+\tuint64_t imissed;\n };\n \n struct gve_xstats_name_offset {\n@@ -272,6 +285,11 @@ struct gve_priv {\n \n \tstruct gve_tx_queue **txqs;\n \tstruct gve_rx_queue **rxqs;\n+\n+\tuint32_t stats_report_len;\n+\tconst struct rte_memzone *stats_report_mem;\n+\tuint16_t stats_start_idx; /* start index of array of stats written by NIC */\n+\tuint16_t stats_end_idx; /* end index of array of stats written by NIC */\n };\n \n static inline bool\n", "prefixes": [] }