Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/135631/?format=api
{ "id": 135631, "url": "http://patchwork.dpdk.org/api/patches/135631/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20231230163509.175037-1-chuanyu.xue@uconn.edu/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20231230163509.175037-1-chuanyu.xue@uconn.edu>", "list_archive_url": "https://inbox.dpdk.org/dev/20231230163509.175037-1-chuanyu.xue@uconn.edu", "date": "2023-12-30T16:35:09", "name": "[v2] net/e1000: support launchtime feature", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "1dc22c0703ffdd138359fb6f7eab6ab770a15f82", "submitter": { "id": 3251, "url": "http://patchwork.dpdk.org/api/people/3251/?format=api", "name": "Chuanyu Xue", "email": "chuanyu.xue@uconn.edu" }, "delegate": { "id": 1540, "url": "http://patchwork.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20231230163509.175037-1-chuanyu.xue@uconn.edu/mbox/", "series": [ { "id": 30685, "url": "http://patchwork.dpdk.org/api/series/30685/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=30685", "date": "2023-12-30T16:35:09", "name": "[v2] net/e1000: support launchtime feature", "version": 2, "mbox": "http://patchwork.dpdk.org/series/30685/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/135631/comments/", "check": "warning", "checks": "http://patchwork.dpdk.org/api/patches/135631/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 423A5437D0;\n\tSat, 30 Dec 2023 17:35:44 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 01CF1402C4;\n\tSat, 30 Dec 2023 17:35:42 +0100 (CET)", "from mail-qv1-f44.google.com (mail-qv1-f44.google.com\n [209.85.219.44]) by mails.dpdk.org (Postfix) with ESMTP id E376A402B9\n for <dev@dpdk.org>; Sat, 30 Dec 2023 17:35:40 +0100 (CET)", "by mail-qv1-f44.google.com with SMTP id\n 6a1803df08f44-67f85d29d14so59920946d6.1\n for <dev@dpdk.org>; Sat, 30 Dec 2023 08:35:40 -0800 (PST)", "from localhost.localdomain ([137.99.252.108])\n by smtp.gmail.com with ESMTPSA id\n lf6-20020a0562142cc600b0067f99bc67a2sm6990932qvb.77.2023.12.30.08.35.39\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Sat, 30 Dec 2023 08:35:39 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=uconn-edu.20230601.gappssmtp.com; s=20230601; t=1703954140; x=1704558940;\n darn=dpdk.org;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:from:to:cc:subject:date\n :message-id:reply-to;\n bh=SSv7cVqZ6xviK8l3Kn9DfREqd25V5zJT9AYp1Fzuvhk=;\n b=fjMS0w+ckFTH7bQzjaKVYxnXP1kyrJ9eZJFQeXzVVSeZYooDhJ1vrUsQW8INfzi4l9\n e4unOTD/75DzoEh8LRmXIMo/XP/OWsCqVT3obxJ3WroHzYq3YdxdoCNmSziKtHt4wxF6\n 7pz+E62e47NW6LlihzKBU7Cxc8Wz/ERvWzbg4+ehqO6LiDT7R9BUOP0nXXx7AXhnhluQ\n HWwtTdRtxYppX+CRNagmOVLMIr77rKq9j7AZRdWtQ6t5kqKyAqnzNwne1HoKL6x8v1y3\n QAV6l9p8BIYJ8RhgLv0LV1jglIoM0a3ixG1GG/HFFDeftUSf8blVbX5YLaIr2zRUOY7z\n TDhg==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20230601; t=1703954140; x=1704558940;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc\n :subject:date:message-id:reply-to;\n bh=SSv7cVqZ6xviK8l3Kn9DfREqd25V5zJT9AYp1Fzuvhk=;\n b=RbZ/KtJ/ia0kBzNJMJ4SBq7jJEOFngQNjuYc/ODMDkII2MvHUbsTFKSznartR93M4E\n /3yxepSJ8CW1RPrYK5yMBS1Ex1aCSOjnyf4aN+yBOC3C9xwFPhIp9WPWrZtUtmzrANgg\n l6JjDcehnIYXxrTA012Sojr0UhFHNT4cGjrT30PJ0rk5wtIXRFu0nHeU29YFX0azVV0c\n tc79pwGVVEx+yw7/ERuupRqw86Q9oe5VDTV2b5fdQb4uzG9Ioze6tk3qtBYjmx1tBzBZ\n 7x4yqA0M8QW8RsR9o5utEIoQJTl7Vpm64b+fdWRuSayn+fk1Mozf6f+ML2RKn/uQr/z6\n 5mkg==", "X-Gm-Message-State": "AOJu0YzgMRI1smwfuwwzDTPopVkhc0aBlB+WEt1CX4tEIHo2K4F8Xa/e\n ntU8y7oZSdEcs4lSQISm2HSFaunU9EMIew==", "X-Google-Smtp-Source": "\n AGHT+IFxaTis9eE2DVbhgnNcuHQUWs9WQlB7uuM0OkeNE5+y2gWGdXn2EFNwLzugRQmcaBvVfkougg==", "X-Received": "by 2002:a05:6214:20e5:b0:67e:f56c:b6c0 with SMTP id\n 5-20020a05621420e500b0067ef56cb6c0mr25812686qvk.60.1703954140057;\n Sat, 30 Dec 2023 08:35:40 -0800 (PST)", "From": "Chuanyu Xue <chuanyu.xue@uconn.edu>", "To": "simei.su@intel.com, wenzhuo.lu@intel.com, qi.z.zhang@intel.com,\n beilei.xing@intel.com", "Cc": "dev@dpdk.org,\n\tChuanyu Xue <chuanyu.xue@uconn.edu>", "Subject": "[PATCH v2] net/e1000: support launchtime feature", "Date": "Sat, 30 Dec 2023 11:35:09 -0500", "Message-Id": "<20231230163509.175037-1-chuanyu.xue@uconn.edu>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20231217202040.478959-1-chuanyu.xue@uconn.edu>", "References": "<20231217202040.478959-1-chuanyu.xue@uconn.edu>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Enable the time-based scheduled Tx of packets based on the\nRTE_ETH_TX_OFFLOAD_SEND_ON_TIMESTAMP flag. The launchtime defines the\npacket transmission time based on PTP clock at MAC layer, which should\nbe set to the advanced transmit descriptor.\n\nSigned-off-by: Chuanyu Xue <chuanyu.xue@uconn.edu>\n---\nchange log:\n\nv2:\n- Add delay compensation for i210 NIC by setting tx offset register.\n- Revise read_clock function.\n\n drivers/net/e1000/base/e1000_regs.h | 1 +\n drivers/net/e1000/e1000_ethdev.h | 14 +++++++\n drivers/net/e1000/igb_ethdev.c | 63 ++++++++++++++++++++++++++++-\n drivers/net/e1000/igb_rxtx.c | 42 +++++++++++++++----\n 4 files changed, 112 insertions(+), 8 deletions(-)", "diff": "diff --git a/drivers/net/e1000/base/e1000_regs.h b/drivers/net/e1000/base/e1000_regs.h\nindex d44de59c29..092d9d71e6 100644\n--- a/drivers/net/e1000/base/e1000_regs.h\n+++ b/drivers/net/e1000/base/e1000_regs.h\n@@ -162,6 +162,7 @@\n \n /* QAV Tx mode control register */\n #define E1000_I210_TQAVCTRL\t0x3570\n+#define E1000_I210_LAUNCH_OS0 0x3578\n \n /* QAV Tx mode control register bitfields masks */\n /* QAV enable */\ndiff --git a/drivers/net/e1000/e1000_ethdev.h b/drivers/net/e1000/e1000_ethdev.h\nindex 718a9746ed..339ae1f4b6 100644\n--- a/drivers/net/e1000/e1000_ethdev.h\n+++ b/drivers/net/e1000/e1000_ethdev.h\n@@ -382,6 +382,20 @@ extern struct igb_rss_filter_list igb_filter_rss_list;\n TAILQ_HEAD(igb_flow_mem_list, igb_flow_mem);\n extern struct igb_flow_mem_list igb_flow_list;\n \n+/*\n+ * Macros to compensate the constant latency observed in i210 for launch time\n+ *\n+ * launch time = (offset_speed - offset_base + txtime) * 32\n+ * offset_speed is speed dependent, set in E1000_I210_LAUNCH_OS0\n+ */\n+#define IGB_I210_TX_OFFSET_BASE\t\t\t\t0xffe0\n+#define IGB_I210_TX_OFFSET_SPEED_10\t\t\t0xc7a0\n+#define IGB_I210_TX_OFFSET_SPEED_100\t\t0x86e0\n+#define IGB_I210_TX_OFFSET_SPEED_1000\t\t0xbe00\n+\n+extern uint64_t igb_tx_timestamp_dynflag;\n+extern int igb_tx_timestamp_dynfield_offset;\n+\n extern const struct rte_flow_ops igb_flow_ops;\n \n /*\ndiff --git a/drivers/net/e1000/igb_ethdev.c b/drivers/net/e1000/igb_ethdev.c\nindex 8858f975f8..2262035710 100644\n--- a/drivers/net/e1000/igb_ethdev.c\n+++ b/drivers/net/e1000/igb_ethdev.c\n@@ -223,6 +223,7 @@ static int igb_timesync_read_time(struct rte_eth_dev *dev,\n \t\t\t\t struct timespec *timestamp);\n static int igb_timesync_write_time(struct rte_eth_dev *dev,\n \t\t\t\t const struct timespec *timestamp);\n+static int eth_igb_read_clock(struct rte_eth_dev *dev, uint64_t *clock);\n static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,\n \t\t\t\t\tuint16_t queue_id);\n static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,\n@@ -313,6 +314,9 @@ static const struct rte_pci_id pci_id_igbvf_map[] = {\n \t{ .vendor_id = 0, /* sentinel */ },\n };\n \n+uint64_t igb_tx_timestamp_dynflag;\n+int igb_tx_timestamp_dynfield_offset = -1;\n+\n static const struct rte_eth_desc_lim rx_desc_lim = {\n \t.nb_max = E1000_MAX_RING_DESC,\n \t.nb_min = E1000_MIN_RING_DESC,\n@@ -389,6 +393,7 @@ static const struct eth_dev_ops eth_igb_ops = {\n \t.timesync_adjust_time = igb_timesync_adjust_time,\n \t.timesync_read_time = igb_timesync_read_time,\n \t.timesync_write_time = igb_timesync_write_time,\n+\t.read_clock\t\t = eth_igb_read_clock,\n };\n \n /*\n@@ -1188,6 +1193,40 @@ eth_igb_rxtx_control(struct rte_eth_dev *dev,\n \tE1000_WRITE_FLUSH(hw);\n }\n \n+\n+static uint32_t igb_tx_offset(struct rte_eth_dev *dev)\n+{\n+\tstruct e1000_hw *hw =\n+\t\tE1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\n+\tuint16_t duplex, speed;\n+\thw->mac.ops.get_link_up_info(hw, &speed, &duplex);\n+\n+\tuint32_t launch_os0 = E1000_READ_REG(hw, E1000_I210_LAUNCH_OS0);\n+\tif (hw->mac.type != e1000_i210) {\n+\t\t/* Set launch offset to base, no compensation */\n+\t\tlaunch_os0 |= IGB_I210_TX_OFFSET_BASE;\n+\t} else {\n+\t\t/* Set launch offset depend on link speeds */\n+\t\tswitch (speed) {\n+\t\tcase SPEED_10:\n+\t\t\tlaunch_os0 |= IGB_I210_TX_OFFSET_SPEED_10;\n+\t\t\tbreak;\n+\t\tcase SPEED_100:\n+\t\t\tlaunch_os0 |= IGB_I210_TX_OFFSET_SPEED_100;\n+\t\t\tbreak;\n+\t\tcase SPEED_1000:\n+\t\t\tlaunch_os0 |= IGB_I210_TX_OFFSET_SPEED_1000;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tlaunch_os0 |= IGB_I210_TX_OFFSET_BASE;\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+\treturn launch_os0;\n+}\n+\n static int\n eth_igb_start(struct rte_eth_dev *dev)\n {\n@@ -1198,6 +1237,7 @@ eth_igb_start(struct rte_eth_dev *dev)\n \tstruct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);\n \tstruct rte_intr_handle *intr_handle = pci_dev->intr_handle;\n \tint ret, mask;\n+\tuint32_t tqavctrl;\n \tuint32_t intr_vector = 0;\n \tuint32_t ctrl_ext;\n \tuint32_t *speeds;\n@@ -1273,6 +1313,15 @@ eth_igb_start(struct rte_eth_dev *dev)\n \n \teth_igb_tx_init(dev);\n \n+\tif (igb_tx_timestamp_dynflag > 0) {\n+\t\ttqavctrl = E1000_READ_REG(hw, E1000_I210_TQAVCTRL);\n+\t\ttqavctrl |= E1000_TQAVCTRL_MODE; /* Enable Qav mode */\n+\t\ttqavctrl |= E1000_TQAVCTRL_FETCH_ARB; /* ARB fetch, no Round Robin*/\n+\t\ttqavctrl |= E1000_TQAVCTRL_LAUNCH_TIMER_ENABLE; /* Enable Tx launch time*/\n+\t\tE1000_WRITE_REG(hw, E1000_I210_TQAVCTRL, tqavctrl);\n+\t\tE1000_WRITE_REG(hw, E1000_I210_LAUNCH_OS0, igb_tx_offset(dev));\n+\t}\n+\n \t/* This can fail when allocating mbufs for descriptor rings */\n \tret = eth_igb_rx_init(dev);\n \tif (ret) {\n@@ -1393,7 +1442,6 @@ eth_igb_start(struct rte_eth_dev *dev)\n \n \teth_igb_rxtx_control(dev, true);\n \teth_igb_link_update(dev, 0);\n-\n \tPMD_INIT_LOG(DEBUG, \"<<\");\n \n \treturn 0;\n@@ -4882,6 +4930,19 @@ igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,\n \treturn 0;\n }\n \n+static int\n+eth_igb_read_clock(struct rte_eth_dev *dev, uint64_t *clock)\n+{\n+\tstruct e1000_adapter *adapter = dev->data->dev_private;\n+\tstruct rte_timecounter *tc = &adapter->systime_tc;\n+\tuint64_t cycles;\n+\n+\tcycles = igb_read_systime_cyclecounter(dev);\n+\t*clock = rte_timecounter_update(tc, cycles);\n+\n+\treturn 0;\n+}\n+\n static int\n eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)\n {\ndiff --git a/drivers/net/e1000/igb_rxtx.c b/drivers/net/e1000/igb_rxtx.c\nindex 448c4b7d9d..5cafd6f1ce 100644\n--- a/drivers/net/e1000/igb_rxtx.c\n+++ b/drivers/net/e1000/igb_rxtx.c\n@@ -244,12 +244,13 @@ check_tso_para(uint64_t ol_req, union igb_tx_offload ol_para)\n static inline void\n igbe_set_xmit_ctx(struct igb_tx_queue* txq,\n \t\tvolatile struct e1000_adv_tx_context_desc *ctx_txd,\n-\t\tuint64_t ol_flags, union igb_tx_offload tx_offload)\n+\t\tuint64_t ol_flags, union igb_tx_offload tx_offload, uint64_t txtime)\n {\n \tuint32_t type_tucmd_mlhl;\n \tuint32_t mss_l4len_idx;\n \tuint32_t ctx_idx, ctx_curr;\n \tuint32_t vlan_macip_lens;\n+\tuint32_t launch_time;\n \tunion igb_tx_offload tx_offload_mask;\n \n \tctx_curr = txq->ctx_curr;\n@@ -312,16 +313,25 @@ igbe_set_xmit_ctx(struct igb_tx_queue* txq,\n \t\t}\n \t}\n \n-\ttxq->ctx_cache[ctx_curr].flags = ol_flags;\n-\ttxq->ctx_cache[ctx_curr].tx_offload.data =\n-\t\ttx_offload_mask.data & tx_offload.data;\n-\ttxq->ctx_cache[ctx_curr].tx_offload_mask = tx_offload_mask;\n+\tif (!txtime) {\n+\t\ttxq->ctx_cache[ctx_curr].flags = ol_flags;\n+\t\ttxq->ctx_cache[ctx_curr].tx_offload.data =\n+\t\t\ttx_offload_mask.data & tx_offload.data;\n+\t\ttxq->ctx_cache[ctx_curr].tx_offload_mask = tx_offload_mask;\n+\t}\n \n \tctx_txd->type_tucmd_mlhl = rte_cpu_to_le_32(type_tucmd_mlhl);\n \tvlan_macip_lens = (uint32_t)tx_offload.data;\n \tctx_txd->vlan_macip_lens = rte_cpu_to_le_32(vlan_macip_lens);\n \tctx_txd->mss_l4len_idx = rte_cpu_to_le_32(mss_l4len_idx);\n \tctx_txd->u.seqnum_seed = 0;\n+\n+\tif (txtime) {\n+\t\tlaunch_time = (txtime - IGB_I210_TX_OFFSET_BASE) % NSEC_PER_SEC;\n+\t\tctx_txd->u.launch_time = rte_cpu_to_le_32(launch_time / 32);\n+\t} else {\n+\t\tctx_txd->u.launch_time = 0;\n+\t}\n }\n \n /*\n@@ -400,6 +410,7 @@ eth_igb_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,\n \tuint32_t new_ctx = 0;\n \tuint32_t ctx = 0;\n \tunion igb_tx_offload tx_offload = {0};\n+\tuint64_t ts;\n \n \ttxq = tx_queue;\n \tsw_ring = txq->sw_ring;\n@@ -552,7 +563,13 @@ eth_igb_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,\n \t\t\t\t\ttxe->mbuf = NULL;\n \t\t\t\t}\n \n-\t\t\t\tigbe_set_xmit_ctx(txq, ctx_txd, tx_ol_req, tx_offload);\n+\t\t\t\tif (igb_tx_timestamp_dynflag > 0) {\n+\t\t\t\t\tts = *RTE_MBUF_DYNFIELD(tx_pkt,\n+\t\t\t\t\t\tigb_tx_timestamp_dynfield_offset, uint64_t *);\n+\t\t\t\t\tigbe_set_xmit_ctx(txq, ctx_txd, tx_ol_req, tx_offload, ts);\n+\t\t\t\t} else {\n+\t\t\t\t\tigbe_set_xmit_ctx(txq, ctx_txd, tx_ol_req, tx_offload, 0);\n+\t\t\t\t}\n \n \t\t\t\ttxe->last_id = tx_last;\n \t\t\t\ttx_id = txe->next_id;\n@@ -1464,7 +1481,8 @@ igb_get_tx_port_offloads_capa(struct rte_eth_dev *dev)\n \t\t\t RTE_ETH_TX_OFFLOAD_TCP_CKSUM |\n \t\t\t RTE_ETH_TX_OFFLOAD_SCTP_CKSUM |\n \t\t\t RTE_ETH_TX_OFFLOAD_TCP_TSO |\n-\t\t\t RTE_ETH_TX_OFFLOAD_MULTI_SEGS;\n+\t\t\t RTE_ETH_TX_OFFLOAD_MULTI_SEGS |\n+\t\t\t RTE_ETH_TX_OFFLOAD_SEND_ON_TIMESTAMP;\n \n \treturn tx_offload_capa;\n }\n@@ -2579,9 +2597,11 @@ eth_igb_tx_init(struct rte_eth_dev *dev)\n {\n \tstruct e1000_hw *hw;\n \tstruct igb_tx_queue *txq;\n+\tuint64_t offloads = dev->data->dev_conf.txmode.offloads;\n \tuint32_t tctl;\n \tuint32_t txdctl;\n \tuint16_t i;\n+\tint err;\n \n \thw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n \n@@ -2612,6 +2632,14 @@ eth_igb_tx_init(struct rte_eth_dev *dev)\n \t\tdev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STARTED;\n \t}\n \n+\tif (offloads & RTE_ETH_TX_OFFLOAD_SEND_ON_TIMESTAMP) {\n+\t\terr = rte_mbuf_dyn_tx_timestamp_register(\n+\t\t\t&igb_tx_timestamp_dynfield_offset,\n+\t\t\t&igb_tx_timestamp_dynflag);\n+\t\tif (err)\n+\t\t\tPMD_DRV_LOG(ERR, \"Failed to register tx timestamp dynamic field\");\n+\t}\n+\n \t/* Program the Transmit Control Register. */\n \ttctl = E1000_READ_REG(hw, E1000_TCTL);\n \ttctl &= ~E1000_TCTL_CT;\n", "prefixes": [ "v2" ] }