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GET /api/patches/136540/?format=api
{ "id": 136540, "url": "http://patchwork.dpdk.org/api/patches/136540/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20240208165038.36265-5-hernan.vargas@intel.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240208165038.36265-5-hernan.vargas@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240208165038.36265-5-hernan.vargas@intel.com", "date": "2024-02-08T16:50:36", "name": "[v7,4/6] baseband/fpga_5gnr_fec: rework total number queues", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "ac22b908586791051d37f2199bd7d65b4cc6c6c6", "submitter": { "id": 2659, "url": "http://patchwork.dpdk.org/api/people/2659/?format=api", "name": "Hernan Vargas", "email": "hernan.vargas@intel.com" }, "delegate": { "id": 2642, "url": "http://patchwork.dpdk.org/api/users/2642/?format=api", "username": "mcoquelin", "first_name": "Maxime", "last_name": "Coquelin", "email": "maxime.coquelin@redhat.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20240208165038.36265-5-hernan.vargas@intel.com/mbox/", "series": [ { "id": 31054, "url": "http://patchwork.dpdk.org/api/series/31054/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=31054", "date": "2024-02-08T16:50:32", "name": "changes for 24.03", "version": 7, "mbox": "http://patchwork.dpdk.org/series/31054/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/136540/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/136540/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 81FFF43AE0;\n\tThu, 8 Feb 2024 17:54:29 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 3231C42E51;\n\tThu, 8 Feb 2024 17:54:03 +0100 (CET)", "from mgamail.intel.com (mgamail.intel.com [192.198.163.13])\n by mails.dpdk.org (Postfix) with ESMTP id 0D5D040295\n for <dev@dpdk.org>; Thu, 8 Feb 2024 17:53:56 +0100 (CET)", "from fmviesa008.fm.intel.com ([10.60.135.148])\n by fmvoesa107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 08 Feb 2024 08:53:56 -0800", "from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103])\n by fmviesa008.fm.intel.com with ESMTP; 08 Feb 2024 08:53:55 -0800" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1707411237; x=1738947237;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=CBo2sYjHsu9XpNY8qEbFAyFXBUDunU5hphfJmvzAU/Q=;\n b=RzlOTt1fq03pdlWUR+whQkSZYscmVIOQKMffC113V3Y6cUZVN/qWt5+J\n TdcjrtujuIqsIvqelkzl80j0IrZwe+oCcC24lX7q5YijiseuwxgSDQsV/\n zL3dxSGUtNCZ+pm7BThgpD8PHtmls/O7rihDiYCEQMBaTf5GsXlYpiqv3\n vdGIOwjBOig+I1wyI83ClG/pVI6yM3MtvikZ4t9+ttE9cugL8x0KHUSd5\n Ummi6N3ec/XZ/ZykAPBOxJXsO03nKMkL2UVV5YJt/pbBC45nUoWdrCDki\n 6Zs2uQtYTmT5Qm2O+2/SFhgQ5aNSUXB2oetmkZqSWwBWtKuiYF61rAQVB w==;", "X-IronPort-AV": [ "E=McAfee;i=\"6600,9927,10978\"; a=\"4244310\"", "E=Sophos;i=\"6.05,254,1701158400\";\n d=\"scan'208\";a=\"4244310\"", "E=Sophos;i=\"6.05,254,1701158400\";\n d=\"scan'208\";a=\"1933643\"" ], "X-ExtLoop1": "1", "From": "Hernan Vargas <hernan.vargas@intel.com>", "To": "dev@dpdk.org, gakhil@marvell.com, trix@redhat.com,\n maxime.coquelin@redhat.com", "Cc": "nicolas.chautru@intel.com, qi.z.zhang@intel.com,\n Hernan Vargas <hernan.vargas@intel.com>", "Subject": "[PATCH v7 4/6] baseband/fpga_5gnr_fec: rework total number queues", "Date": "Thu, 8 Feb 2024 08:50:36 -0800", "Message-Id": "<20240208165038.36265-5-hernan.vargas@intel.com>", "X-Mailer": "git-send-email 2.37.1", "In-Reply-To": "<20240208165038.36265-1-hernan.vargas@intel.com>", "References": "<20240208165038.36265-1-hernan.vargas@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Add total_num_queues to the FPGA device struct as a preliminary rework\nfor the introduction of different FPGA variants.\n\nSigned-off-by: Hernan Vargas <hernan.vargas@intel.com>\nReviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>\n---\n .../baseband/fpga_5gnr_fec/fpga_5gnr_fec.h | 2 +\n .../fpga_5gnr_fec/rte_fpga_5gnr_fec.c | 37 +++++++++++--------\n 2 files changed, 23 insertions(+), 16 deletions(-)", "diff": "diff --git a/drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h b/drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h\nindex 982e956dc819..879e5467ef3d 100644\n--- a/drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h\n+++ b/drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h\n@@ -131,6 +131,8 @@ struct fpga_5gnr_fec_device {\n \tuint64_t q_assigned_bit_map;\n \t/** True if this is a PF FPGA 5GNR device. */\n \tbool pf_device;\n+\t/** Maximum number of possible queues for this device. */\n+\tuint8_t total_num_queues;\n };\n \n /** Structure associated with each queue. */\ndiff --git a/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c b/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c\nindex f9a776e6aea5..3fb505775f61 100644\n--- a/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c\n+++ b/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c\n@@ -203,7 +203,7 @@ fpga_5gnr_setup_queues(struct rte_bbdev *dev, uint16_t num_queues, int socket_id\n \t * replaced with a queue ID and if it's not then\n \t * FPGA_5GNR_INVALID_HW_QUEUE_ID is returned.\n \t */\n-\tfor (q_id = 0; q_id < VC_5GNR_TOTAL_NUM_QUEUES; ++q_id) {\n+\tfor (q_id = 0; q_id < d->total_num_queues; ++q_id) {\n \t\tuint32_t hw_q_id = fpga_5gnr_reg_read_32(d->mmio_base,\n \t\t\t\tVC_5GNR_QUEUE_MAP + (q_id << 2));\n \n@@ -367,7 +367,7 @@ fpga_5gnr_dev_info_get(struct rte_bbdev *dev, struct rte_bbdev_driver_info *dev_\n \n \t/* Calculates number of queues assigned to device */\n \tdev_info->max_num_queues = 0;\n-\tfor (q_id = 0; q_id < VC_5GNR_TOTAL_NUM_QUEUES; ++q_id) {\n+\tfor (q_id = 0; q_id < d->total_num_queues; ++q_id) {\n \t\tuint32_t hw_q_id = fpga_5gnr_reg_read_32(d->mmio_base,\n \t\t\t\tVC_5GNR_QUEUE_MAP + (q_id << 2));\n \t\tif (hw_q_id != FPGA_5GNR_INVALID_HW_QUEUE_ID)\n@@ -394,11 +394,11 @@ fpga_5gnr_find_free_queue_idx(struct rte_bbdev *dev,\n \tstruct fpga_5gnr_fec_device *d = dev->data->dev_private;\n \tuint64_t q_idx;\n \tuint8_t i = 0;\n-\tuint8_t range = VC_5GNR_TOTAL_NUM_QUEUES >> 1;\n+\tuint8_t range = d->total_num_queues >> 1;\n \n \tif (conf->op_type == RTE_BBDEV_OP_LDPC_ENC) {\n-\t\ti = VC_5GNR_NUM_DL_QUEUES;\n-\t\trange = VC_5GNR_TOTAL_NUM_QUEUES;\n+\t\ti = d->total_num_queues >> 1;\n+\t\trange = d->total_num_queues;\n \t}\n \n \tfor (; i < range; ++i) {\n@@ -661,7 +661,7 @@ fpga_5gnr_dev_interrupt_handler(void *cb_arg)\n \tuint8_t i;\n \n \t/* Scan queue assigned to this device */\n-\tfor (i = 0; i < VC_5GNR_TOTAL_NUM_QUEUES; ++i) {\n+\tfor (i = 0; i < d->total_num_queues; ++i) {\n \t\tq_idx = 1ULL << i;\n \t\tif (d->q_bound_bit_map & q_idx) {\n \t\t\tqueue_id = get_queue_id(dev->data, i);\n@@ -710,22 +710,25 @@ fpga_5gnr_intr_enable(struct rte_bbdev *dev)\n {\n \tint ret;\n \tuint8_t i;\n+\tstruct fpga_5gnr_fec_device *d = dev->data->dev_private;\n+\tuint8_t num_intr_vec;\n \n+\tnum_intr_vec = d->total_num_queues - RTE_INTR_VEC_RXTX_OFFSET;\n \tif (!rte_intr_cap_multiple(dev->intr_handle)) {\n \t\trte_bbdev_log(ERR, \"Multiple intr vector is not supported by FPGA (%s)\",\n \t\t\t\tdev->data->name);\n \t\treturn -ENOTSUP;\n \t}\n \n-\t/* Create event file descriptors for each of 64 queue. Event fds will be\n-\t * mapped to FPGA IRQs in rte_intr_enable(). This is a 1:1 mapping where\n-\t * the IRQ number is a direct translation to the queue number.\n+\t/* Create event file descriptors for each of the supported queues (Maximum 64).\n+\t * Event fds will be mapped to FPGA IRQs in rte_intr_enable().\n+\t * This is a 1:1 mapping where the IRQ number is a direct translation to the queue number.\n \t *\n-\t * 63 (VC_5GNR_NUM_INTR_VEC) event fds are created as rte_intr_enable()\n+\t * num_intr_vec event fds are created as rte_intr_enable()\n \t * mapped the first IRQ to already created interrupt event file\n \t * descriptor (intr_handle->fd).\n \t */\n-\tif (rte_intr_efd_enable(dev->intr_handle, VC_5GNR_NUM_INTR_VEC)) {\n+\tif (rte_intr_efd_enable(dev->intr_handle, num_intr_vec)) {\n \t\trte_bbdev_log(ERR, \"Failed to create fds for %u queues\", dev->data->num_queues);\n \t\treturn -1;\n \t}\n@@ -735,7 +738,7 @@ fpga_5gnr_intr_enable(struct rte_bbdev *dev)\n \t * It ensures that callback function assigned to that descriptor will\n \t * invoked when any FPGA queue issues interrupt.\n \t */\n-\tfor (i = 0; i < VC_5GNR_NUM_INTR_VEC; ++i) {\n+\tfor (i = 0; i < num_intr_vec; ++i) {\n \t\tif (rte_intr_efds_index_set(dev->intr_handle, i,\n \t\t\t\trte_intr_fd_get(dev->intr_handle)))\n \t\t\treturn -rte_errno;\n@@ -2083,6 +2086,8 @@ fpga_5gnr_fec_init(struct rte_bbdev *dev, struct rte_pci_driver *drv)\n \t\t\t!strcmp(drv->driver.name, RTE_STR(FPGA_5GNR_FEC_PF_DRIVER_NAME));\n \t((struct fpga_5gnr_fec_device *) dev->data->dev_private)->mmio_base =\n \t\t\tpci_dev->mem_resource[0].addr;\n+\t((struct fpga_5gnr_fec_device *) dev->data->dev_private)->total_num_queues =\n+\t\t\tVC_5GNR_TOTAL_NUM_QUEUES;\n \n \trte_bbdev_log_debug(\n \t\t\t\"Init device %s [%s] @ virtaddr %p phyaddr %#\"PRIx64,\n@@ -2242,7 +2247,7 @@ static int vc_5gnr_configure(const char *dev_name, const struct rte_fpga_5gnr_fe\n \n \t/* Clear all queues registers */\n \tpayload_32 = FPGA_5GNR_INVALID_HW_QUEUE_ID;\n-\tfor (q_id = 0; q_id < VC_5GNR_TOTAL_NUM_QUEUES; ++q_id) {\n+\tfor (q_id = 0; q_id < d->total_num_queues; ++q_id) {\n \t\taddress = (q_id << 2) + VC_5GNR_QUEUE_MAP;\n \t\tfpga_5gnr_reg_write_32(d->mmio_base, address, payload_32);\n \t}\n@@ -2303,7 +2308,7 @@ static int vc_5gnr_configure(const char *dev_name, const struct rte_fpga_5gnr_fe\n \t */\n \tif (conf->pf_mode_en) {\n \t\tpayload_32 = 0x1;\n-\t\tfor (q_id = 0; q_id < VC_5GNR_TOTAL_NUM_QUEUES; ++q_id) {\n+\t\tfor (q_id = 0; q_id < d->total_num_queues; ++q_id) {\n \t\t\taddress = (q_id << 2) + VC_5GNR_QUEUE_MAP;\n \t\t\tfpga_5gnr_reg_write_32(d->mmio_base, address, payload_32);\n \t\t}\n@@ -2321,11 +2326,11 @@ static int vc_5gnr_configure(const char *dev_name, const struct rte_fpga_5gnr_fe\n \t\t */\n \t\tif ((total_ul_q_id > VC_5GNR_NUM_UL_QUEUES) ||\n \t\t\t(total_dl_q_id > VC_5GNR_NUM_DL_QUEUES) ||\n-\t\t\t(total_q_id > VC_5GNR_TOTAL_NUM_QUEUES)) {\n+\t\t\t(total_q_id > d->total_num_queues)) {\n \t\t\trte_bbdev_log(ERR,\n \t\t\t\t\t\"VC 5GNR FPGA Configuration failed. Too many queues to configure: UL_Q %u, DL_Q %u, FPGA_Q %u\",\n \t\t\t\t\ttotal_ul_q_id, total_dl_q_id,\n-\t\t\t\t\tVC_5GNR_TOTAL_NUM_QUEUES);\n+\t\t\t\t\td->total_num_queues);\n \t\t\treturn -EINVAL;\n \t\t}\n \t\ttotal_ul_q_id = 0;\n", "prefixes": [ "v7", "4/6" ] }