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GET /api/patches/136590/?format=api
{ "id": 136590, "url": "http://patchwork.dpdk.org/api/patches/136590/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20240212123216.517767-3-getelson@nvidia.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240212123216.517767-3-getelson@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240212123216.517767-3-getelson@nvidia.com", "date": "2024-02-12T12:32:16", "name": "[v2,2/2] net/mlx5: improve pattern template validation", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "0d0d0e7f83e48b40dbad227f384f613a014d7f11", "submitter": { "id": 1882, "url": "http://patchwork.dpdk.org/api/people/1882/?format=api", "name": "Gregory Etelson", "email": "getelson@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patchwork.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20240212123216.517767-3-getelson@nvidia.com/mbox/", "series": [ { "id": 31074, "url": "http://patchwork.dpdk.org/api/series/31074/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=31074", "date": "2024-02-12T12:32:14", "name": "net/mlx5: update pattern validations", "version": 2, "mbox": "http://patchwork.dpdk.org/series/31074/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/136590/comments/", "check": "fail", "checks": "http://patchwork.dpdk.org/api/patches/136590/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 0D46943B00;\n\tMon, 12 Feb 2024 13:32:57 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 55990402F2;\n\tMon, 12 Feb 2024 13:32:53 +0100 (CET)", "from NAM10-BN7-obe.outbound.protection.outlook.com\n (mail-bn7nam10on2078.outbound.protection.outlook.com [40.107.92.78])\n by mails.dpdk.org (Postfix) with ESMTP id 1454E402A3\n for <dev@dpdk.org>; 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helo=mail.nvidia.com; pr=C", "From": "Gregory Etelson <getelson@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "<getelson@nvidia.com>, <mkashani@nvidia.com>, Dariusz Sosnowski\n <dsosnowski@nvidia.com>, Viacheslav Ovsiienko <viacheslavo@nvidia.com>, \"Ori\n Kam\" <orika@nvidia.com>, Suanming Mou <suanmingm@nvidia.com>, Matan Azrad\n <matan@nvidia.com>", "Subject": "[PATCH v2 2/2] net/mlx5: improve pattern template validation", "Date": "Mon, 12 Feb 2024 14:32:16 +0200", "Message-ID": "<20240212123216.517767-3-getelson@nvidia.com>", "X-Mailer": "git-send-email 2.39.2", "In-Reply-To": "<20240212123216.517767-1-getelson@nvidia.com>", "References": "<20240202150617.328603-2-getelson@nvidia.com>\n <20240212123216.517767-1-getelson@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.231.35]", "X-ClientProxiedBy": "rnnvmail202.nvidia.com (10.129.68.7) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "CH1PEPF0000A349:EE_|DS7PR12MB6007:EE_", "X-MS-Office365-Filtering-Correlation-Id": "17077c4c-a111-4a5d-5540-08dc2bc6b907", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n +2qrwxjv16w+XVXgXClrqoyJ/X74IPEGY97lvBg2oXFJEddQpE+BXDiOUB8kR0qT1JzprV0lTISLmhwoXWcXb1gn+7EVlpp57W1vH1mSpccEDnKZ8aN9lLpUQycF6iQYRRQnyfASNTJI63YVy9VO2USnZMtYi3DLfwW1MB64aSZgDiPP4+Ed0ubz7gGI7324LieCSRt9odS7jA+3x7R2Tuw5ejkh6FIO+tR8AFY3hHGHhAQ2ZJKyJi3oVA6ua1G9vvsec5OjAxB+zbUNDnmKdF17AgNR2ln7Wb3lo4Zo7XCbjnWmWW2trf61GsCN7Jjx/bXC0F6DkQa4eZ+1KTbzKFSgYBZw/UbLdJUpQwQnJ8IXoP8eL1UNV4i1Dv3H76/vgIj0IYBBD9Gbo3PUHEB1ftsm6ALK8I8WqE8h6x5+clwEU/k1FatbrnwNhjS2y/Be8Y/+3HPIu93syOiA/gDNHZbIhrb3y4j9nLUZDwvTPPcsQJ81WSP/SRzdGCWUseRcJFDv8MIqrNlGEwv726oe2uc/SoHuTJW4Zew5L/S5+50kHLFqOMQ4kSNObqeuebxfS9mozC3aR4k9828U8Hhd0lhcs/37cDpahphXxkZx0Co=", "X-Forefront-Antispam-Report": "CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE;\n SFS:(13230031)(4636009)(39860400002)(136003)(376002)(396003)(346002)(230922051799003)(1800799012)(64100799003)(451199024)(186009)(82310400011)(40470700004)(36840700001)(46966006)(36756003)(26005)(16526019)(478600001)(426003)(6286002)(336012)(1076003)(2616005)(107886003)(41300700001)(8936002)(70586007)(83380400001)(70206006)(8676002)(6916009)(5660300002)(4326008)(54906003)(6666004)(7696005)(316002)(86362001)(82740400003)(356005)(7636003)(55016003)(2906002);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "12 Feb 2024 12:32:48.5989 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 17077c4c-a111-4a5d-5540-08dc2bc6b907", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CH1PEPF0000A349.namprd04.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DS7PR12MB6007", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Current PMD implementation validates pattern templates that will\nalways be rejected during table template creation.\n\nThe patch adds basic HWS verifications to pattern validation to\nensure that the pattern can be used in table template.\n\nPMD updates `rte_errno` if pattern template validation failed:\n\nE2BIG - pattern too big for PMD\nENOTSUP - pattern not supported by PMD\nENOMEM - PMD allocation failure\n\nSigned-off-by: Gregory Etelson <getelson@nvidia.com>\nAcked-by: Dariusz Sosnowski <dsosnowski@nvidia.com>\n---\n drivers/net/mlx5/mlx5.h | 1 +\n drivers/net/mlx5/mlx5_flow_hw.c | 116 ++++++++++++++++++++++++++++++++\n 2 files changed, 117 insertions(+)", "diff": "diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex f2e2e04429..e98db91888 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -1965,6 +1965,7 @@ struct mlx5_priv {\n \tstruct mlx5_aso_mtr_pool *hws_mpool; /* HW steering's Meter pool. */\n \tstruct mlx5_flow_hw_ctrl_rx *hw_ctrl_rx;\n \t/**< HW steering templates used to create control flow rules. */\n+\tstruct rte_flow_actions_template *action_template_drop[MLX5DR_TABLE_TYPE_MAX];\n #endif\n \tstruct rte_eth_dev *shared_host; /* Host device for HW steering. */\n \tuint16_t shared_refcnt; /* HW steering host reference counter. */\ndiff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c\nindex da873ae2e2..ebb2efb2e1 100644\n--- a/drivers/net/mlx5/mlx5_flow_hw.c\n+++ b/drivers/net/mlx5/mlx5_flow_hw.c\n@@ -6840,6 +6840,45 @@ flow_hw_pattern_has_sq_match(const struct rte_flow_item *items)\n \treturn false;\n }\n \n+static int\n+pattern_template_validate(struct rte_eth_dev *dev,\n+\t\t\t struct rte_flow_pattern_template *pt[], uint32_t pt_num)\n+{\n+\tuint32_t group = 0;\n+\tstruct rte_flow_template_table_attr tbl_attr = {\n+\t\t.nb_flows = 64,\n+\t\t.insertion_type = RTE_FLOW_TABLE_INSERTION_TYPE_PATTERN,\n+\t\t.hash_func = RTE_FLOW_TABLE_HASH_FUNC_DEFAULT,\n+\t\t.flow_attr = {\n+\t\t\t.ingress = pt[0]->attr.ingress,\n+\t\t\t.egress = pt[0]->attr.egress,\n+\t\t\t.transfer = pt[0]->attr.transfer\n+\t\t}\n+\t};\n+\tstruct mlx5_priv *priv = dev->data->dev_private;\n+\tstruct rte_flow_actions_template *action_template;\n+\n+\tif (pt[0]->attr.ingress)\n+\t\taction_template = priv->action_template_drop[MLX5DR_TABLE_TYPE_NIC_RX];\n+\telse if (pt[0]->attr.egress)\n+\t\taction_template = priv->action_template_drop[MLX5DR_TABLE_TYPE_NIC_TX];\n+\telse if (pt[0]->attr.transfer)\n+\t\taction_template = priv->action_template_drop[MLX5DR_TABLE_TYPE_FDB];\n+\telse\n+\t\treturn EINVAL;\n+\tdo {\n+\t\tstruct rte_flow_template_table *tmpl_tbl;\n+\n+\t\ttbl_attr.flow_attr.group = group;\n+\t\ttmpl_tbl = flow_hw_table_create(dev, &tbl_attr, pt, pt_num,\n+\t\t\t\t\t\t&action_template, 1, NULL);\n+\t\tif (!tmpl_tbl)\n+\t\t\treturn rte_errno;\n+\t\tflow_hw_table_destroy(dev, tmpl_tbl, NULL);\n+\t} while (++group <= 1);\n+\treturn 0;\n+}\n+\n /**\n * Create flow item template.\n *\n@@ -6975,8 +7014,19 @@ flow_hw_pattern_template_create(struct rte_eth_dev *dev,\n \t\t}\n \t}\n \t__atomic_fetch_add(&it->refcnt, 1, __ATOMIC_RELAXED);\n+\trte_errno = pattern_template_validate(dev, &it, 1);\n+\tif (rte_errno)\n+\t\tgoto error;\n \tLIST_INSERT_HEAD(&priv->flow_hw_itt, it, next);\n \treturn it;\n+error:\n+\tflow_hw_flex_item_release(dev, &it->flex_item);\n+\tclaim_zero(mlx5dr_match_template_destroy(it->mt));\n+\tmlx5_free(it);\n+\trte_flow_error_set(error, rte_errno, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,\n+\t\t\t \"Failed to create pattern template\");\n+\treturn NULL;\n+\n }\n \n /**\n@@ -9184,6 +9234,67 @@ flow_hw_compare_config(const struct mlx5_flow_hw_attr *hw_attr,\n \treturn true;\n }\n \n+/*\n+ * No need to explicitly release drop action templates on port stop.\n+ * Drop action templates release with other action templates during\n+ * mlx5_dev_close -> flow_hw_resource_release -> flow_hw_actions_template_destroy\n+ */\n+static void\n+action_template_drop_release(struct rte_eth_dev *dev)\n+{\n+\tint i;\n+\tstruct mlx5_priv *priv = dev->data->dev_private;\n+\n+\tfor (i = 0; i < MLX5DR_TABLE_TYPE_MAX; i++) {\n+\t\tif (!priv->action_template_drop[i])\n+\t\t\tcontinue;\n+\t\tflow_hw_actions_template_destroy(dev,\n+\t\t\t\t\t\t priv->action_template_drop[i],\n+\t\t\t\t\t\t NULL);\n+\t\tpriv->action_template_drop[i] = NULL;\n+\t}\n+}\n+\n+static int\n+action_template_drop_init(struct rte_eth_dev *dev,\n+\t\t\t struct rte_flow_error *error)\n+{\n+\tconst struct rte_flow_action drop[2] = {\n+\t\t[0] = { .type = RTE_FLOW_ACTION_TYPE_DROP },\n+\t\t[1] = { .type = RTE_FLOW_ACTION_TYPE_END },\n+\t};\n+\tconst struct rte_flow_action *actions = drop;\n+\tconst struct rte_flow_action *masks = drop;\n+\tconst struct rte_flow_actions_template_attr attr[MLX5DR_TABLE_TYPE_MAX] = {\n+\t\t[MLX5DR_TABLE_TYPE_NIC_RX] = { .ingress = 1 },\n+\t\t[MLX5DR_TABLE_TYPE_NIC_TX] = { .egress = 1 },\n+\t\t[MLX5DR_TABLE_TYPE_FDB] = { .transfer = 1 }\n+\t};\n+\tstruct mlx5_priv *priv = dev->data->dev_private;\n+\n+\tpriv->action_template_drop[MLX5DR_TABLE_TYPE_NIC_RX] =\n+\t\tflow_hw_actions_template_create(dev,\n+\t\t\t\t\t\t&attr[MLX5DR_TABLE_TYPE_NIC_RX],\n+\t\t\t\t\t\tactions, masks, error);\n+\tif (!priv->action_template_drop[MLX5DR_TABLE_TYPE_NIC_RX])\n+\t\treturn -1;\n+\tpriv->action_template_drop[MLX5DR_TABLE_TYPE_NIC_TX] =\n+\t\tflow_hw_actions_template_create(dev,\n+\t\t\t\t\t\t&attr[MLX5DR_TABLE_TYPE_NIC_TX],\n+\t\t\t\t\t\tactions, masks, error);\n+\tif (!priv->action_template_drop[MLX5DR_TABLE_TYPE_NIC_TX])\n+\t\treturn -1;\n+\tif (priv->sh->config.dv_esw_en && priv->master) {\n+\t\tpriv->action_template_drop[MLX5DR_TABLE_TYPE_FDB] =\n+\t\t\tflow_hw_actions_template_create(dev,\n+\t\t\t\t\t\t\t&attr[MLX5DR_TABLE_TYPE_FDB],\n+\t\t\t\t\t\t\tactions, masks, error);\n+\t\tif (!priv->action_template_drop[MLX5DR_TABLE_TYPE_FDB])\n+\t\t\treturn -1;\n+\t}\n+\treturn 0;\n+}\n+\n /**\n * Configure port HWS resources.\n *\n@@ -9426,6 +9537,9 @@ flow_hw_configure(struct rte_eth_dev *dev,\n \trte_spinlock_init(&priv->hw_ctrl_lock);\n \tLIST_INIT(&priv->hw_ctrl_flows);\n \tLIST_INIT(&priv->hw_ext_ctrl_flows);\n+\tret = action_template_drop_init(dev, error);\n+\tif (ret)\n+\t\tgoto err;\n \tret = flow_hw_create_ctrl_rx_tables(dev);\n \tif (ret) {\n \t\trte_flow_error_set(error, -ret, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,\n@@ -9559,6 +9673,7 @@ flow_hw_configure(struct rte_eth_dev *dev,\n \t\tmlx5_hws_cnt_pool_destroy(priv->sh, priv->hws_cpool);\n \t\tpriv->hws_cpool = NULL;\n \t}\n+\taction_template_drop_release(dev);\n \tmlx5_flow_quota_destroy(dev);\n \tflow_hw_destroy_send_to_kernel_action(priv);\n \tflow_hw_free_vport_actions(priv);\n@@ -9621,6 +9736,7 @@ flow_hw_resource_release(struct rte_eth_dev *dev)\n \tflow_hw_flush_all_ctrl_flows(dev);\n \tflow_hw_cleanup_tx_repr_tagging(dev);\n \tflow_hw_cleanup_ctrl_rx_tables(dev);\n+\taction_template_drop_release(dev);\n \twhile (!LIST_EMPTY(&priv->flow_hw_grp)) {\n \t\tgrp = LIST_FIRST(&priv->flow_hw_grp);\n \t\tflow_hw_group_unset_miss_group(dev, grp, NULL);\n", "prefixes": [ "v2", "2/2" ] }