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GET /api/patches/136628/?format=api
{ "id": 136628, "url": "http://patchwork.dpdk.org/api/patches/136628/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20240213095038.451299-6-igozlan@nvidia.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240213095038.451299-6-igozlan@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240213095038.451299-6-igozlan@nvidia.com", "date": "2024-02-13T09:50:34", "name": "[6/9] net/mlx5/hws: fix VLAN item handling on non relaxed mode", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "a7d5c4c65f916e89b267a41974a148b3e2aba97e", "submitter": { "id": 3118, "url": "http://patchwork.dpdk.org/api/people/3118/?format=api", "name": "Itamar Gozlan", "email": "igozlan@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patchwork.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20240213095038.451299-6-igozlan@nvidia.com/mbox/", "series": [ { "id": 31082, "url": "http://patchwork.dpdk.org/api/series/31082/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=31082", "date": "2024-02-13T09:50:29", "name": "[1/9] net/mlx5/hws: skip RTE item when inserting rules by index", "version": 1, "mbox": "http://patchwork.dpdk.org/series/31082/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/136628/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/136628/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id D07C543B05;\n\tTue, 13 Feb 2024 10:51:45 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 8DA4F427D9;\n\tTue, 13 Feb 2024 10:51:25 +0100 (CET)", "from NAM04-DM6-obe.outbound.protection.outlook.com\n (mail-dm6nam04on2070.outbound.protection.outlook.com [40.107.102.70])\n by mails.dpdk.org (Postfix) with ESMTP id DA02D427D7\n for <dev@dpdk.org>; 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helo=mail.nvidia.com; pr=C", "From": "Itamar Gozlan <igozlan@nvidia.com>", "To": "<igozlan@nvidia.com>, <erezsh@nvidia.com>, <hamdani@nvidia.com>,\n <kliteyn@nvidia.com>, <viacheslavo@nvidia.com>, <thomas@monjalon.net>,\n <suanmingm@nvidia.com>, Dariusz Sosnowski <dsosnowski@nvidia.com>, Ori Kam\n <orika@nvidia.com>, Matan Azrad <matan@nvidia.com>, Mark Bloch\n <mbloch@nvidia.com>, Alex Vesker <valex@nvidia.com>", "CC": "<dev@dpdk.org>", "Subject": "[PATCH 6/9] net/mlx5/hws: fix VLAN item handling on non relaxed mode", "Date": "Tue, 13 Feb 2024 11:50:34 +0200", "Message-ID": "<20240213095038.451299-6-igozlan@nvidia.com>", "X-Mailer": "git-send-email 2.39.3", "In-Reply-To": "<20240213095038.451299-1-igozlan@nvidia.com>", "References": "<20240213095038.451299-1-igozlan@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-NV-OnPremToCloud": "ExternallySecured", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "CH2PEPF00000099:EE_|DM4PR12MB6349:EE_", "X-MS-Office365-Filtering-Correlation-Id": "db4ed65a-f2f9-44d3-2ff0-08dc2c79557e", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n Dbfrs3c/oxqixLdEwEfiFCZ+Xz0lCWE2yMQCQx3fAkovqwvDsby1+4CzXPOUHvhM9qn+Xb3I9CNPy1ihOhaEA7HVbAkYfp2H9VhU3oJ4d4KBXw0ndLQGRfvNnIQPjqaaipwT/j8dh49ypcv13zV1e+Hq8DPuwzLLn9lBOJn1cHoOegpKXZTpU4jFGEv+b//q0Ozqr/Qw1KYQNphArx/YpJu3YHc4u6RFq7anhHnEtLXq8FYFrMbgOHsqPISv92fsC7k9kIA3p3SJ7/AuAg6b5dr18/1kvCc7qdFgwDqh3KAXxTOYAp4fSw7znPzfxcQvFsIrp+4jouOlPSWY6yYMlYw50iAWsoWILRffMeDjV4cFrdWOHMEvENTCrYpTjVEm2NOznFMcYU5A8lfR6L4xuc65OgyD2eDb1MYsdjAlAW6LHPK35MF3k6kr87+zPO1AhbRUPHePbWEKJXUHsiOmE0NxtXaZLLxY8v/0KM7bIUJi6IGpFJTn7iB52bzFOtaNCPEfHgr7XJ7DQ0whki24AB8WRUNdCIsBOaKpu57iY4f3Qs8LDuU3dIVdbr99DBxPNQGNYVIi+yja9FghCNCOhf34HxsDBINtB/ryIYXezEQX8q4tGI7EvpVNQGg840SyuAjlLISmsNcdoz/UKYXVqQ==", "X-Forefront-Antispam-Report": "CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE;\n SFS:(13230031)(4636009)(39860400002)(136003)(376002)(396003)(346002)(230922051799003)(186009)(82310400011)(1800799012)(64100799003)(451199024)(46966006)(40470700004)(36840700001)(921011)(36756003)(4326008)(110136005)(8676002)(26005)(2616005)(8936002)(41300700001)(336012)(478600001)(426003)(1076003)(6286002)(70586007)(83380400001)(70206006)(5660300002)(6636002)(7696005)(6666004)(316002)(86362001)(82740400003)(356005)(7636003)(55016003)(2906002);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "13 Feb 2024 09:51:21.5203 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n db4ed65a-f2f9-44d3-2ff0-08dc2c79557e", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CH2PEPF00000099.namprd02.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DM4PR12MB6349", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Hamdan Igbaria <hamdani@nvidia.com>\n\nIf a VLAN item was passed with null mask, the item handler would\nreturn immediately and thus won't set default values for non relax\nmode.\nAlso change the non relax default set to single-tagged (CVLAN).\n\nFixes: c55c2bf35333 (\"net/mlx5/hws: add definer layer\")\nSigned-off-by: Hamdan Igbaria <hamdani@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/net/mlx5/hws/mlx5dr_definer.c | 13 +++++++++++--\n 1 file changed, 11 insertions(+), 2 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c\nindex eb788a772a..b8a546989a 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_definer.c\n+++ b/drivers/net/mlx5/hws/mlx5dr_definer.c\n@@ -223,6 +223,7 @@ struct mlx5dr_definer_conv_data {\n \tX(SET,\t\tib_l4_opcode,\t\tv->hdr.opcode,\t\trte_flow_item_ib_bth) \\\n \tX(SET,\t\trandom_number,\t\tv->value,\t\trte_flow_item_random) \\\n \tX(SET,\t\tib_l4_bth_a,\t\tv->hdr.a,\t\trte_flow_item_ib_bth) \\\n+\tX(SET,\t\tcvlan,\t\t\tSTE_CVLAN,\t\trte_flow_item_vlan) \\\n \n /* Item set function format */\n #define X(set_type, func_name, value, item_type) \\\n@@ -864,6 +865,15 @@ mlx5dr_definer_conv_item_vlan(struct mlx5dr_definer_conv_data *cd,\n \tstruct mlx5dr_definer_fc *fc;\n \tbool inner = cd->tunnel;\n \n+\tif (!cd->relaxed) {\n+\t\t/* Mark packet as tagged (CVLAN) */\n+\t\tfc = &cd->fc[DR_CALC_FNAME(VLAN_TYPE, inner)];\n+\t\tfc->item_idx = item_idx;\n+\t\tfc->tag_mask_set = &mlx5dr_definer_ones_set;\n+\t\tfc->tag_set = &mlx5dr_definer_cvlan_set;\n+\t\tDR_CALC_SET(fc, eth_l2, first_vlan_qualifier, inner);\n+\t}\n+\n \tif (!m)\n \t\treturn 0;\n \n@@ -872,8 +882,7 @@ mlx5dr_definer_conv_item_vlan(struct mlx5dr_definer_conv_data *cd,\n \t\treturn rte_errno;\n \t}\n \n-\tif (!cd->relaxed || m->has_more_vlan) {\n-\t\t/* Mark packet as tagged (CVLAN or SVLAN) even if TCI is not specified.*/\n+\tif (m->has_more_vlan) {\n \t\tfc = &cd->fc[DR_CALC_FNAME(VLAN_TYPE, inner)];\n \t\tfc->item_idx = item_idx;\n \t\tfc->tag_mask_set = &mlx5dr_definer_ones_set;\n", "prefixes": [ "6/9" ] }