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GET /api/patches/136748/?format=api
{ "id": 136748, "url": "http://patchwork.dpdk.org/api/patches/136748/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20240214073015.2060103-4-michaelba@nvidia.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240214073015.2060103-4-michaelba@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240214073015.2060103-4-michaelba@nvidia.com", "date": "2024-02-14T07:30:15", "name": "[v5,3/3] net/mlx5/hws: add compare ESP sequence number support", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "d028a2e2b4f0fcece0005285960d2159510d5b81", "submitter": { "id": 1949, "url": "http://patchwork.dpdk.org/api/people/1949/?format=api", "name": "Michael Baum", "email": "michaelba@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patchwork.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20240214073015.2060103-4-michaelba@nvidia.com/mbox/", "series": [ { "id": 31103, "url": "http://patchwork.dpdk.org/api/series/31103/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=31103", "date": "2024-02-14T07:30:12", "name": "net/mlx5: add compare item support", "version": 5, "mbox": "http://patchwork.dpdk.org/series/31103/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/136748/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/136748/checks/", "tags": {}, "related": [], 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<viacheslavo@nvidia.com>, Ori Kam <orika@nvidia.com>, Suanming Mou\n <suanmingm@nvidia.com>", "Subject": "[PATCH v5 3/3] net/mlx5/hws: add compare ESP sequence number support", "Date": "Wed, 14 Feb 2024 09:30:15 +0200", "Message-ID": "<20240214073015.2060103-4-michaelba@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20240214073015.2060103-1-michaelba@nvidia.com>", "References": "<20240207161414.1583125-1-michaelba@nvidia.com>\n <20240214073015.2060103-1-michaelba@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-NV-OnPremToCloud": "ExternallySecured", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "DS1PEPF0001709B:EE_|SJ2PR12MB8009:EE_", "X-MS-Office365-Filtering-Correlation-Id": "c1d6fb0a-5f3e-48a3-b50f-08dc2d2ee001", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": 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SFS:(13230031)(4636009)(346002)(136003)(39860400002)(376002)(396003)(230922051799003)(82310400011)(186009)(451199024)(64100799003)(1800799012)(40470700004)(36840700001)(46966006)(6666004)(54906003)(316002)(55016003)(2906002)(5660300002)(70206006)(86362001)(426003)(4326008)(8676002)(8936002)(6916009)(70586007)(7696005)(478600001)(6286002)(26005)(41300700001)(2616005)(107886003)(36756003)(1076003)(83380400001)(7636003)(356005)(336012)(82740400003);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "14 Feb 2024 07:30:52.8159 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n c1d6fb0a-5f3e-48a3-b50f-08dc2d2ee001", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DS1PEPF0001709B.namprd05.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "SJ2PR12MB8009", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Add support for compare item with \"RTE_FLOW_FIELD_ESP_SEQ_NUM\" field.\n\nSigned-off-by: Michael Baum <michaelba@nvidia.com>\n---\n doc/guides/nics/mlx5.rst | 1 +\n drivers/net/mlx5/hws/mlx5dr_definer.c | 22 ++++++++++++++++++++--\n drivers/net/mlx5/mlx5_flow_hw.c | 3 +++\n 3 files changed, 24 insertions(+), 2 deletions(-)", "diff": "diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst\nindex 43ef8a99dc..b793f1ef58 100644\n--- a/doc/guides/nics/mlx5.rst\n+++ b/doc/guides/nics/mlx5.rst\n@@ -823,6 +823,7 @@ Limitations\n - Only single item is supported per pattern template.\n - Only 32-bit comparison is supported or 16-bits for random field.\n - Only supported for ``RTE_FLOW_FIELD_META``, ``RTE_FLOW_FIELD_TAG``,\n+ ``RTE_FLOW_FIELD_ESP_SEQ_NUM``,\n ``RTE_FLOW_FIELD_RANDOM`` and ``RTE_FLOW_FIELD_VALUE``.\n - The field type ``RTE_FLOW_FIELD_VALUE`` must be the base (``b``) field.\n - The field type ``RTE_FLOW_FIELD_RANDOM`` can only be compared with\ndiff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c\nindex 2d86175ca2..b29d7451e7 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_definer.c\n+++ b/drivers/net/mlx5/hws/mlx5dr_definer.c\n@@ -396,10 +396,20 @@ mlx5dr_definer_compare_base_value_set(const void *item_spec,\n \n \tvalue = (const uint32_t *)&b->value[0];\n \n-\tif (a->field == RTE_FLOW_FIELD_RANDOM)\n+\tswitch (a->field) {\n+\tcase RTE_FLOW_FIELD_RANDOM:\n \t\t*base = htobe32(*value << 16);\n-\telse\n+\t\tbreak;\n+\tcase RTE_FLOW_FIELD_TAG:\n+\tcase RTE_FLOW_FIELD_META:\n \t\t*base = htobe32(*value);\n+\t\tbreak;\n+\tcase RTE_FLOW_FIELD_ESP_SEQ_NUM:\n+\t\t*base = *value;\n+\t\tbreak;\n+\tdefault:\n+\t\tbreak;\n+\t}\n \n \tMLX5_SET(ste_match_4dw_range_ctrl_dw, ctrl, base0, 1);\n }\n@@ -2887,6 +2897,14 @@ mlx5dr_definer_conv_item_compare_field(const struct rte_flow_field_data *f,\n \t\tfc->compare_idx = dw_offset;\n \t\tDR_CALC_SET_HDR(fc, random_number, random_number);\n \t\tbreak;\n+\tcase RTE_FLOW_FIELD_ESP_SEQ_NUM:\n+\t\tfc = &cd->fc[MLX5DR_DEFINER_FNAME_ESP_SEQUENCE_NUMBER];\n+\t\tfc->item_idx = item_idx;\n+\t\tfc->tag_set = &mlx5dr_definer_compare_set;\n+\t\tfc->tag_mask_set = &mlx5dr_definer_ones_set;\n+\t\tfc->compare_idx = dw_offset;\n+\t\tDR_CALC_SET_HDR(fc, ipsec, sequence_number);\n+\t\tbreak;\n \tdefault:\n \t\tDR_LOG(ERR, \"%u field is not supported\", f->field);\n \t\tgoto err_notsup;\ndiff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c\nindex b5741f0817..4d6fb489b2 100644\n--- a/drivers/net/mlx5/mlx5_flow_hw.c\n+++ b/drivers/net/mlx5/mlx5_flow_hw.c\n@@ -6725,6 +6725,7 @@ flow_hw_item_compare_field_validate(enum rte_flow_field_id arg_field,\n \tswitch (arg_field) {\n \tcase RTE_FLOW_FIELD_TAG:\n \tcase RTE_FLOW_FIELD_META:\n+\tcase RTE_FLOW_FIELD_ESP_SEQ_NUM:\n \t\tbreak;\n \tcase RTE_FLOW_FIELD_RANDOM:\n \t\tif (base_field == RTE_FLOW_FIELD_VALUE)\n@@ -6743,6 +6744,7 @@ flow_hw_item_compare_field_validate(enum rte_flow_field_id arg_field,\n \tcase RTE_FLOW_FIELD_TAG:\n \tcase RTE_FLOW_FIELD_META:\n \tcase RTE_FLOW_FIELD_VALUE:\n+\tcase RTE_FLOW_FIELD_ESP_SEQ_NUM:\n \t\tbreak;\n \tdefault:\n \t\treturn rte_flow_error_set(error, ENOTSUP,\n@@ -6759,6 +6761,7 @@ flow_hw_item_compare_width_supported(enum rte_flow_field_id field)\n \tswitch (field) {\n \tcase RTE_FLOW_FIELD_TAG:\n \tcase RTE_FLOW_FIELD_META:\n+\tcase RTE_FLOW_FIELD_ESP_SEQ_NUM:\n \t\treturn 32;\n \tcase RTE_FLOW_FIELD_RANDOM:\n \t\treturn 16;\n", "prefixes": [ "v5", "3/3" ] }