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GET /api/patches/136929/?format=api
{ "id": 136929, "url": "http://patchwork.dpdk.org/api/patches/136929/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20240220141008.292641-6-bingz@nvidia.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240220141008.292641-6-bingz@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240220141008.292641-6-bingz@nvidia.com", "date": "2024-02-20T14:10:08", "name": "[v2,5/5] net/mlx5: validate the actions combination with NAT64", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "42d3c0b5714d70726a68f382f75e494d18aec401", "submitter": { "id": 1976, "url": "http://patchwork.dpdk.org/api/people/1976/?format=api", "name": "Bing Zhao", "email": "bingz@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patchwork.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20240220141008.292641-6-bingz@nvidia.com/mbox/", "series": [ { "id": 31154, "url": "http://patchwork.dpdk.org/api/series/31154/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=31154", "date": "2024-02-20T14:10:03", "name": "NAT64 support in mlx5 PMD", "version": 2, "mbox": "http://patchwork.dpdk.org/series/31154/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/136929/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/136929/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 34F0C43B54;\n\tTue, 20 Feb 2024 15:11:31 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id DC45240685;\n\tTue, 20 Feb 2024 15:11:19 +0100 (CET)", "from NAM02-SN1-obe.outbound.protection.outlook.com\n (mail-sn1nam02on2078.outbound.protection.outlook.com [40.107.96.78])\n by mails.dpdk.org (Postfix) with ESMTP id 8B8FB40DFD\n for <dev@dpdk.org>; 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helo=mail.nvidia.com; pr=C", "From": "Bing Zhao <bingz@nvidia.com>", "To": "<orika@nvidia.com>, <aman.deep.singh@intel.com>, <dsosnowski@nvidia.com>,\n <viacheslavo@nvidia.com>, <suanmingm@nvidia.com>, <matan@nvidia.com>,\n <thomas@monjalon.net>, <ferruh.yigit@amd.com>,\n <andrew.rybchenko@oktetlabs.ru>, <dev@dpdk.org>, <rasland@nvidia.com>", "Subject": "[PATCH v2 5/5] net/mlx5: validate the actions combination with NAT64", "Date": "Tue, 20 Feb 2024 16:10:08 +0200", "Message-ID": "<20240220141008.292641-6-bingz@nvidia.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20240220141008.292641-1-bingz@nvidia.com>", "References": "<20231227090731.2569427-1-bingz@nvidia.com>\n <20240220141008.292641-1-bingz@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.231.35]", "X-ClientProxiedBy": "rnnvmail203.nvidia.com (10.129.68.9) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "CO1PEPF000042A8:EE_|PH7PR12MB6836:EE_", "X-MS-Office365-Filtering-Correlation-Id": "f1ef0f7e-21d2-4dec-45b5-08dc321dccb5", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n LoqYQ59k6aTVd5omfOaN1j5Y0tEZ81JpSEQVH7ZDMX7jYrwj/I0gIGwHiDvaflgGMIPpTR5OrE/FGxfXUJNXVwOV0Yiky0YaThhpDIU5GIq9KDbt9B4+e8vpED3KbN1mSA+1i6/tpPMli1vL57C61P0254hCp9FZUQVidCFxNymDK3os3Oc/dvTGO11Ad+giEKuyiPhqAuZLislcBFtlZpQUnZHoZWCD9Jv+JyYWFJjgHFFdu+mX5dCx15MVEYOeFwMv9u+Zdu+SxkA2aVeLkZ08L07j9EaZJ7vSfrYmdqOv+WrrcL/SUJgpkjll8dw5INgahRCqOvmggI1ozj1nEYAOewvfIxv2U5HxbihMPUnafTkABHhJN+Gcxy+VwWy4u8yFT1c8j+TmNHBsPKSBc7slI4v1JHFALgJ3r4lyVD12UdkHDNd95AO9eRfs9lWrVAh1iMyHk84z5ofGkbWhKtAN2UVjXKnxaMgrTqZtFUqBApmt6cfD8UrEW2PwN6HgbIhH355q+OKAW7VnhW7Ln+gZfB5KYdzpkiwE2aeiS5+0Iir8gLn6pG3ZcY5wudLnS8zPr69s8IK4WsM2w2thFOGfBiCksFSxwQsVWg7eIs8R4XCOQCJBVRMrt77Vzj6pgnGEsRVnV3Ii1ESYd7xR7oClOCScMmWkZ16NN+rmE+M=", "X-Forefront-Antispam-Report": "CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE;\n SFS:(13230031)(36860700004)(40470700004)(46966006)(921011); DIR:OUT;\n SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "20 Feb 2024 14:11:14.8233 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n f1ef0f7e-21d2-4dec-45b5-08dc321dccb5", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CO1PEPF000042A8.namprd03.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "PH7PR12MB6836", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "NAT64 is treated as a modify header action. The action order and\nlimitation should be the same as that of modify header in each\ndomain.\n\nSince the last 2 TAG registers will be used implicitly in the\naddress backup mode, the values in these registers are no longer\nvalid after the NAT64 action. The application should not try to\nmatch these TAGs after the rule that contains NAT64 action.\n\nSigned-off-by: Bing Zhao <bingz@nvidia.com>\n---\n drivers/net/mlx5/mlx5_flow.h | 1 +\n drivers/net/mlx5/mlx5_flow_hw.c | 51 +++++++++++++++++++++++++++++++++\n 2 files changed, 52 insertions(+)", "diff": "diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h\nindex da13f1f210..c3e053d730 100644\n--- a/drivers/net/mlx5/mlx5_flow.h\n+++ b/drivers/net/mlx5/mlx5_flow.h\n@@ -382,6 +382,7 @@ enum mlx5_feature_name {\n #define MLX5_FLOW_ACTION_PORT_REPRESENTOR (1ull << 47)\n #define MLX5_FLOW_ACTION_IPV6_ROUTING_REMOVE (1ull << 48)\n #define MLX5_FLOW_ACTION_IPV6_ROUTING_PUSH (1ull << 49)\n+#define MLX5_FLOW_ACTION_NAT64 (1ull << 50)\n \n #define MLX5_FLOW_DROP_INCLUSIVE_ACTIONS \\\n \t(MLX5_FLOW_ACTION_COUNT | MLX5_FLOW_ACTION_SAMPLE | MLX5_FLOW_ACTION_AGE)\ndiff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c\nindex abe7159ad1..4d2b271210 100644\n--- a/drivers/net/mlx5/mlx5_flow_hw.c\n+++ b/drivers/net/mlx5/mlx5_flow_hw.c\n@@ -5725,6 +5725,50 @@ flow_hw_validate_action_default_miss(struct rte_eth_dev *dev,\n \treturn 0;\n }\n \n+static int\n+flow_hw_validate_action_nat64(struct rte_eth_dev *dev,\n+\t\t\t const struct rte_flow_actions_template_attr *attr,\n+\t\t\t const struct rte_flow_action *action,\n+\t\t\t const struct rte_flow_action *mask,\n+\t\t\t uint64_t action_flags,\n+\t\t\t struct rte_flow_error *error)\n+{\n+\tstruct mlx5_priv *priv = dev->data->dev_private;\n+\tconst struct rte_flow_action_nat64 *nat64_c;\n+\tenum rte_flow_nat64_type cov_type;\n+\n+\tRTE_SET_USED(action_flags);\n+\tif (mask->conf && ((const struct rte_flow_action_nat64 *)mask->conf)->type) {\n+\t\tnat64_c = (const struct rte_flow_action_nat64 *)action->conf;\n+\t\tcov_type = nat64_c->type;\n+\t\tif ((attr->ingress && !priv->action_nat64[MLX5DR_TABLE_TYPE_NIC_RX][cov_type]) ||\n+\t\t (attr->egress && !priv->action_nat64[MLX5DR_TABLE_TYPE_NIC_TX][cov_type]) ||\n+\t\t (attr->transfer && !priv->action_nat64[MLX5DR_TABLE_TYPE_FDB][cov_type]))\n+\t\t\tgoto err_out;\n+\t} else {\n+\t\t/*\n+\t\t * Usually, the actions will be used on both directions. For non-masked actions,\n+\t\t * both directions' actions will be checked.\n+\t\t */\n+\t\tif (attr->ingress)\n+\t\t\tif (!priv->action_nat64[MLX5DR_TABLE_TYPE_NIC_RX][RTE_FLOW_NAT64_6TO4] ||\n+\t\t\t !priv->action_nat64[MLX5DR_TABLE_TYPE_NIC_RX][RTE_FLOW_NAT64_4TO6])\n+\t\t\t\tgoto err_out;\n+\t\tif (attr->egress)\n+\t\t\tif (!priv->action_nat64[MLX5DR_TABLE_TYPE_NIC_TX][RTE_FLOW_NAT64_6TO4] ||\n+\t\t\t !priv->action_nat64[MLX5DR_TABLE_TYPE_NIC_TX][RTE_FLOW_NAT64_4TO6])\n+\t\t\t\tgoto err_out;\n+\t\tif (attr->transfer)\n+\t\t\tif (!priv->action_nat64[MLX5DR_TABLE_TYPE_FDB][RTE_FLOW_NAT64_6TO4] ||\n+\t\t\t !priv->action_nat64[MLX5DR_TABLE_TYPE_FDB][RTE_FLOW_NAT64_4TO6])\n+\t\t\t\tgoto err_out;\n+\t}\n+\treturn 0;\n+err_out:\n+\treturn rte_flow_error_set(error, EOPNOTSUPP, RTE_FLOW_ERROR_TYPE_ACTION,\n+\t\t\t\t NULL, \"NAT64 action is not supported.\");\n+}\n+\n static int\n mlx5_flow_hw_actions_validate(struct rte_eth_dev *dev,\n \t\t\t const struct rte_flow_actions_template_attr *attr,\n@@ -5926,6 +5970,13 @@ mlx5_flow_hw_actions_validate(struct rte_eth_dev *dev,\n \t\t\t\tMLX5_HW_VLAN_PUSH_VID_IDX;\n \t\t\taction_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;\n \t\t\tbreak;\n+\t\tcase RTE_FLOW_ACTION_TYPE_NAT64:\n+\t\t\tret = flow_hw_validate_action_nat64(dev, attr, action, mask,\n+\t\t\t\t\t\t\t action_flags, error);\n+\t\t\tif (ret != 0)\n+\t\t\t\treturn ret;\n+\t\t\taction_flags |= MLX5_FLOW_ACTION_NAT64;\n+\t\t\tbreak;\n \t\tcase RTE_FLOW_ACTION_TYPE_END:\n \t\t\tactions_end = true;\n \t\t\tbreak;\n", "prefixes": [ "v2", "5/5" ] }