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GET /api/patches/137206/?format=api
{ "id": 137206, "url": "http://patchwork.dpdk.org/api/patches/137206/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20240226130324.2981025-3-michaelba@nvidia.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240226130324.2981025-3-michaelba@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240226130324.2981025-3-michaelba@nvidia.com", "date": "2024-02-26T13:03:23", "name": "[v6,2/3] net/mlx5: add support to compare random value", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "896989302338b25b9db5e623776d789ebde0319f", "submitter": { "id": 1949, "url": "http://patchwork.dpdk.org/api/people/1949/?format=api", "name": "Michael Baum", "email": "michaelba@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patchwork.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20240226130324.2981025-3-michaelba@nvidia.com/mbox/", "series": [ { "id": 31222, "url": "http://patchwork.dpdk.org/api/series/31222/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=31222", "date": "2024-02-26T13:03:22", "name": "net/mlx5: add compare item support", "version": 6, "mbox": "http://patchwork.dpdk.org/series/31222/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/137206/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/137206/checks/", "tags": {}, "related": [], "headers": { "Return-Path": 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<viacheslavo@nvidia.com>, Ori Kam <orika@nvidia.com>, Suanming Mou\n <suanmingm@nvidia.com>", "Subject": "[PATCH v6 2/3] net/mlx5: add support to compare random value", "Date": "Mon, 26 Feb 2024 15:03:23 +0200", "Message-ID": "<20240226130324.2981025-3-michaelba@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20240226130324.2981025-1-michaelba@nvidia.com>", "References": "<20240214073015.2060103-1-michaelba@nvidia.com>\n <20240226130324.2981025-1-michaelba@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-NV-OnPremToCloud": "ExternallySecured", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "CY4PEPF0000EE36:EE_|CH0PR12MB5106:EE_", "X-MS-Office365-Filtering-Correlation-Id": "2bee9a4e-52d6-44f5-f740-08dc36cb64ae", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n vvzNpBsk4bqE8ZKjG6ccRPUBsM3eNyIFJMRgv6Urp7zeTqxw7tjvmHf6UuiVE3Q3Ymo2sHdRlXsDTEHNJEI9O7uqQEuWE99Tpe8fPRWp/JW8FILWpBpywgkJGZrMTE3WZViCgpHWZLGSh8IysAh4le2RIM3IloH274JQlOBZNuk9i2/9Pz8qeO6m0RSnAnadPQxx4wYhet0CqiCVjknOfL8xiGSVciX0V0YnVSwfn3bAAjsdaHrYblGWMlfvbfTB1eN878D4ulrzr9LoTdmBLYTAYv8wupWBrhUZ7UxvyUpobLQQtjB6AyCFUdsJ7nNq8l5hQeoukQfbkvtYafm+V7Whh+PIfXeHHnhVElfVdXN1EpR3/4T6Vj6VQeVMUjVAdeLH4FiaTXeNdawVt4DJ+uBC+NRHQE67SeAY8YGsHYKXx5Q/XgyUdj9KFNio99pgTeTeT+joVci8UGz1oZCw21VZDhwEAfUpN6SvkIlpaGNUC7MhK+hsxEcx1fHtXj0esLb/MkG6ZB7Jrk6XHl2pksUJt5qM2yMkdIS5iJw19dBmcUKlnI1rz5pys8z2ZAJoTBPKhiD66jwCgGnH52tARIqTv4dJYXCfdoHbWqqxifmf3pNBRJr8U+E5zN2p5uVSCk6Bu2DLHsQCefWhWI4d9RhHcg61LtZzuNITrABymkzb9sJGyF4A1rlXpZoVow4jmYCYGLblz4OuIb1t+oDeRREfLrSzv0oQyryKEkdqn5URmKFMxCi3yL2KkOvBTJGk", "X-Forefront-Antispam-Report": "CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE;\n SFS:(13230031)(36860700004); DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "26 Feb 2024 13:03:57.3341 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 2bee9a4e-52d6-44f5-f740-08dc36cb64ae", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CY4PEPF0000EE36.namprd05.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "CH0PR12MB5106", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Add support to use \"RTE_FLOW_ITEM_TYPE_COMPARE\" with\n\"RTE_FLOW_FIELD_RAMDOM\" as an argument.\nThe random field is supported only when base is an immediate value,\nrandom field cannot be compared with enother field.\n\nSigned-off-by: Michael Baum <michaelba@nvidia.com>\nAcked-by: Suanming Mou <suanmingm@nvidia.com>\n---\n doc/guides/nics/mlx5.rst | 9 ++++-\n drivers/net/mlx5/mlx5_flow_hw.c | 70 ++++++++++++++++++++++++---------\n 2 files changed, 59 insertions(+), 20 deletions(-)", "diff": "diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst\nindex 0d2213497a..c0a5768117 100644\n--- a/doc/guides/nics/mlx5.rst\n+++ b/doc/guides/nics/mlx5.rst\n@@ -431,8 +431,13 @@ Limitations\n \n - Only supported in HW steering(``dv_flow_en`` = 2) mode.\n - Only single flow is supported to the flow table.\n- - Only 32-bit comparison is supported.\n- - Only match with compare result between packet fields is supported.\n+ - Only single item is supported per pattern template.\n+ - Only 32-bit comparison is supported or 16-bits for random field.\n+ - Only supported for ``RTE_FLOW_FIELD_META``, ``RTE_FLOW_FIELD_TAG``,\n+ ``RTE_FLOW_FIELD_RANDOM`` and ``RTE_FLOW_FIELD_VALUE``.\n+ - The field type ``RTE_FLOW_FIELD_VALUE`` must be the base (``b``) field.\n+ - The field type ``RTE_FLOW_FIELD_RANDOM`` can only be compared with\n+ ``RTE_FLOW_FIELD_VALUE``.\n \n - No Tx metadata go to the E-Switch steering domain for the Flow group 0.\n The flows within group 0 and set metadata action are rejected by hardware.\ndiff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c\nindex 0d09c220df..b0e93baaf2 100644\n--- a/drivers/net/mlx5/mlx5_flow_hw.c\n+++ b/drivers/net/mlx5/mlx5_flow_hw.c\n@@ -6721,18 +6721,55 @@ flow_hw_prepend_item(const struct rte_flow_item *items,\n \treturn copied_items;\n }\n \n-static inline bool\n-flow_hw_item_compare_field_supported(enum rte_flow_field_id field)\n+static int\n+flow_hw_item_compare_field_validate(enum rte_flow_field_id arg_field,\n+\t\t\t\t enum rte_flow_field_id base_field,\n+\t\t\t\t struct rte_flow_error *error)\n {\n-\tswitch (field) {\n+\tswitch (arg_field) {\n+\tcase RTE_FLOW_FIELD_TAG:\n+\tcase RTE_FLOW_FIELD_META:\n+\t\tbreak;\n+\tcase RTE_FLOW_FIELD_RANDOM:\n+\t\tif (base_field == RTE_FLOW_FIELD_VALUE)\n+\t\t\treturn 0;\n+\t\treturn rte_flow_error_set(error, EINVAL,\n+\t\t\t\t\t RTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n+\t\t\t\t\t NULL,\n+\t\t\t\t\t \"compare random is supported only with immediate value\");\n+\tdefault:\n+\t\treturn rte_flow_error_set(error, ENOTSUP,\n+\t\t\t\t\t RTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n+\t\t\t\t\t NULL,\n+\t\t\t\t\t \"compare item argument field is not supported\");\n+\t}\n+\tswitch (base_field) {\n \tcase RTE_FLOW_FIELD_TAG:\n \tcase RTE_FLOW_FIELD_META:\n \tcase RTE_FLOW_FIELD_VALUE:\n-\t\treturn true;\n+\t\tbreak;\n+\tdefault:\n+\t\treturn rte_flow_error_set(error, ENOTSUP,\n+\t\t\t\t\t RTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n+\t\t\t\t\t NULL,\n+\t\t\t\t\t \"compare item base field is not supported\");\n+\t}\n+\treturn 0;\n+}\n+\n+static inline uint32_t\n+flow_hw_item_compare_width_supported(enum rte_flow_field_id field)\n+{\n+\tswitch (field) {\n+\tcase RTE_FLOW_FIELD_TAG:\n+\tcase RTE_FLOW_FIELD_META:\n+\t\treturn 32;\n+\tcase RTE_FLOW_FIELD_RANDOM:\n+\t\treturn 16;\n \tdefault:\n \t\tbreak;\n \t}\n-\treturn false;\n+\treturn 0;\n }\n \n static int\n@@ -6741,6 +6778,7 @@ flow_hw_validate_item_compare(const struct rte_flow_item *item,\n {\n \tconst struct rte_flow_item_compare *comp_m = item->mask;\n \tconst struct rte_flow_item_compare *comp_v = item->spec;\n+\tint ret;\n \n \tif (unlikely(!comp_m))\n \t\treturn rte_flow_error_set(error, EINVAL,\n@@ -6752,19 +6790,13 @@ flow_hw_validate_item_compare(const struct rte_flow_item *item,\n \t\t\t\t RTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n \t\t\t\t NULL,\n \t\t\t\t \"compare item only support full mask\");\n-\tif (!flow_hw_item_compare_field_supported(comp_m->a.field) ||\n-\t !flow_hw_item_compare_field_supported(comp_m->b.field))\n-\t\treturn rte_flow_error_set(error, ENOTSUP,\n-\t\t\t\t RTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n-\t\t\t\t NULL,\n-\t\t\t\t \"compare item field not support\");\n-\tif (comp_m->a.field == RTE_FLOW_FIELD_VALUE &&\n-\t comp_m->b.field == RTE_FLOW_FIELD_VALUE)\n-\t\treturn rte_flow_error_set(error, EINVAL,\n-\t\t\t\t RTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n-\t\t\t\t NULL,\n-\t\t\t\t \"compare between value is not valid\");\n+\tret = flow_hw_item_compare_field_validate(comp_m->a.field,\n+\t\t\t\t\t\t comp_m->b.field, error);\n+\tif (ret < 0)\n+\t\treturn ret;\n \tif (comp_v) {\n+\t\tuint32_t width;\n+\n \t\tif (comp_v->operation != comp_m->operation ||\n \t\t comp_v->a.field != comp_m->a.field ||\n \t\t comp_v->b.field != comp_m->b.field)\n@@ -6772,7 +6804,9 @@ flow_hw_validate_item_compare(const struct rte_flow_item *item,\n \t\t\t\t\t RTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n \t\t\t\t\t NULL,\n \t\t\t\t\t \"compare item spec/mask not matching\");\n-\t\tif ((comp_v->width & comp_m->width) != 32)\n+\t\twidth = flow_hw_item_compare_width_supported(comp_v->a.field);\n+\t\tMLX5_ASSERT(width > 0);\n+\t\tif ((comp_v->width & comp_m->width) != width)\n \t\t\treturn rte_flow_error_set(error, EINVAL,\n \t\t\t\t\t RTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n \t\t\t\t\t NULL,\n", "prefixes": [ "v6", "2/3" ] }