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GET /api/patches/137207/?format=api
{ "id": 137207, "url": "http://patchwork.dpdk.org/api/patches/137207/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20240226130324.2981025-4-michaelba@nvidia.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240226130324.2981025-4-michaelba@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240226130324.2981025-4-michaelba@nvidia.com", "date": "2024-02-26T13:03:24", "name": "[v6,3/3] net/mlx5/hws: add compare ESP sequence number support", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "d028a2e2b4f0fcece0005285960d2159510d5b81", "submitter": { "id": 1949, "url": "http://patchwork.dpdk.org/api/people/1949/?format=api", "name": "Michael Baum", "email": "michaelba@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patchwork.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20240226130324.2981025-4-michaelba@nvidia.com/mbox/", "series": [ { "id": 31222, "url": "http://patchwork.dpdk.org/api/series/31222/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=31222", "date": "2024-02-26T13:03:22", "name": "net/mlx5: add compare item support", "version": 6, "mbox": "http://patchwork.dpdk.org/series/31222/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/137207/comments/", "check": "warning", "checks": "http://patchwork.dpdk.org/api/patches/137207/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 7DB1D43BEF;\n\tMon, 26 Feb 2024 14:04:50 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 0477242E5A;\n\tMon, 26 Feb 2024 14:04:12 +0100 (CET)", "from NAM10-MW2-obe.outbound.protection.outlook.com\n (mail-mw2nam10on2055.outbound.protection.outlook.com [40.107.94.55])\n by mails.dpdk.org (Postfix) with ESMTP id C17FE42E5F\n for <dev@dpdk.org>; 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helo=mail.nvidia.com; pr=C", "From": "Michael Baum <michaelba@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "Matan Azrad <matan@nvidia.com>, Dariusz Sosnowski <dsosnowski@nvidia.com>,\n Raslan Darawsheh <rasland@nvidia.com>, Viacheslav Ovsiienko\n <viacheslavo@nvidia.com>, Ori Kam <orika@nvidia.com>, Suanming Mou\n <suanmingm@nvidia.com>", "Subject": "[PATCH v6 3/3] net/mlx5/hws: add compare ESP sequence number support", "Date": "Mon, 26 Feb 2024 15:03:24 +0200", "Message-ID": "<20240226130324.2981025-4-michaelba@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20240226130324.2981025-1-michaelba@nvidia.com>", "References": "<20240214073015.2060103-1-michaelba@nvidia.com>\n <20240226130324.2981025-1-michaelba@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-NV-OnPremToCloud": "ExternallySecured", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "BL02EPF0001A100:EE_|DM6PR12MB4313:EE_", "X-MS-Office365-Filtering-Correlation-Id": "ff80e11a-1a96-4b50-b46d-08dc36cb69af", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n WbGncPGZ6y3QAE24qSqX3sbKQRvidwRGCkVT0kUD5WwXm52eAYI9DTNHa8WCsx6bc4qbuM/bq9vYIpFIIuXSfErpY/ZpJyjtavGFeD9rzhZ//izPcJs05MQSiM1lwS6R+wENfSGDOcByZ0ABCdGtDIfCO0KmjFg1NUJHoVYb5Z4B6KqUNb5bZdPXMgcwCjc5L77StCE+kK62PQnghFAdtpuwRG4Rrp4oC/GC+adrms7BdKmfyyWXs2OX/eWnmhnZlYw7RC4H4cnWVZpx+JF5vcEO67FB04sWbxFuwyPpTvw+kZGri6tSR22pHl8eeqg04hztbxJvTPSNcP3r8f9CCdtZTKbfnHGl+V9jxIMZaPEyv3VEZZhPnXNKqhH3gS9YG1bcY71T7OrYj2H++5VZonlB4dvlylqy/3Jl5O/nAcA2kMxXSosSZ23ryVVsRV6yTfMxaejvTjHfDh9RQLsWqbKCRV577fgSnfIzoMxTS+o1UzYaKazELEABukkqGHWYY9WW04YO0+mxkPgvHim6RKK2JFfPzPkLDdH+P/s3SCaBvHZjagCr1DF3QFB/O70wE+n42iu8WNWOBjL06unvmZgbWPp4VL45fCPYQQRTeEerMKWFOvO0yU5LnmxvxXlp7s9FliXxKkESH5keOcnEJxrephUC9JoIksP4vofz0+Osj+7la4hkI0tta4UwgfbUMaXQ8Qm41h8YQ9+vAWbTV92x4RFNsqCGFatbALAVQ2Vle18hOwshhRZM4xfS9u5v", "X-Forefront-Antispam-Report": "CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE;\n SFS:(13230031)(36860700004); DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "26 Feb 2024 13:04:05.6026 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n ff80e11a-1a96-4b50-b46d-08dc36cb69af", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BL02EPF0001A100.namprd03.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DM6PR12MB4313", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Add support for compare item with \"RTE_FLOW_FIELD_ESP_SEQ_NUM\" field.\n\nSigned-off-by: Michael Baum <michaelba@nvidia.com>\nAcked-by: Suanming Mou <suanmingm@nvidia.com>\n---\n doc/guides/nics/mlx5.rst | 1 +\n drivers/net/mlx5/hws/mlx5dr_definer.c | 22 ++++++++++++++++++++--\n drivers/net/mlx5/mlx5_flow_hw.c | 3 +++\n 3 files changed, 24 insertions(+), 2 deletions(-)", "diff": "diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst\nindex c0a5768117..d7bf81161e 100644\n--- a/doc/guides/nics/mlx5.rst\n+++ b/doc/guides/nics/mlx5.rst\n@@ -434,6 +434,7 @@ Limitations\n - Only single item is supported per pattern template.\n - Only 32-bit comparison is supported or 16-bits for random field.\n - Only supported for ``RTE_FLOW_FIELD_META``, ``RTE_FLOW_FIELD_TAG``,\n+ ``RTE_FLOW_FIELD_ESP_SEQ_NUM``,\n ``RTE_FLOW_FIELD_RANDOM`` and ``RTE_FLOW_FIELD_VALUE``.\n - The field type ``RTE_FLOW_FIELD_VALUE`` must be the base (``b``) field.\n - The field type ``RTE_FLOW_FIELD_RANDOM`` can only be compared with\ndiff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c\nindex da50b64fb4..39269b4ede 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_definer.c\n+++ b/drivers/net/mlx5/hws/mlx5dr_definer.c\n@@ -424,10 +424,20 @@ mlx5dr_definer_compare_base_value_set(const void *item_spec,\n \n \tvalue = (const uint32_t *)&b->value[0];\n \n-\tif (a->field == RTE_FLOW_FIELD_RANDOM)\n+\tswitch (a->field) {\n+\tcase RTE_FLOW_FIELD_RANDOM:\n \t\t*base = htobe32(*value << 16);\n-\telse\n+\t\tbreak;\n+\tcase RTE_FLOW_FIELD_TAG:\n+\tcase RTE_FLOW_FIELD_META:\n \t\t*base = htobe32(*value);\n+\t\tbreak;\n+\tcase RTE_FLOW_FIELD_ESP_SEQ_NUM:\n+\t\t*base = *value;\n+\t\tbreak;\n+\tdefault:\n+\t\tbreak;\n+\t}\n \n \tMLX5_SET(ste_match_4dw_range_ctrl_dw, ctrl, base0, 1);\n }\n@@ -2930,6 +2940,14 @@ mlx5dr_definer_conv_item_compare_field(const struct rte_flow_field_data *f,\n \t\tfc->compare_idx = dw_offset;\n \t\tDR_CALC_SET_HDR(fc, random_number, random_number);\n \t\tbreak;\n+\tcase RTE_FLOW_FIELD_ESP_SEQ_NUM:\n+\t\tfc = &cd->fc[MLX5DR_DEFINER_FNAME_ESP_SEQUENCE_NUMBER];\n+\t\tfc->item_idx = item_idx;\n+\t\tfc->tag_set = &mlx5dr_definer_compare_set;\n+\t\tfc->tag_mask_set = &mlx5dr_definer_ones_set;\n+\t\tfc->compare_idx = dw_offset;\n+\t\tDR_CALC_SET_HDR(fc, ipsec, sequence_number);\n+\t\tbreak;\n \tdefault:\n \t\tDR_LOG(ERR, \"%u field is not supported\", f->field);\n \t\tgoto err_notsup;\ndiff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c\nindex b0e93baaf2..33922bddff 100644\n--- a/drivers/net/mlx5/mlx5_flow_hw.c\n+++ b/drivers/net/mlx5/mlx5_flow_hw.c\n@@ -6729,6 +6729,7 @@ flow_hw_item_compare_field_validate(enum rte_flow_field_id arg_field,\n \tswitch (arg_field) {\n \tcase RTE_FLOW_FIELD_TAG:\n \tcase RTE_FLOW_FIELD_META:\n+\tcase RTE_FLOW_FIELD_ESP_SEQ_NUM:\n \t\tbreak;\n \tcase RTE_FLOW_FIELD_RANDOM:\n \t\tif (base_field == RTE_FLOW_FIELD_VALUE)\n@@ -6747,6 +6748,7 @@ flow_hw_item_compare_field_validate(enum rte_flow_field_id arg_field,\n \tcase RTE_FLOW_FIELD_TAG:\n \tcase RTE_FLOW_FIELD_META:\n \tcase RTE_FLOW_FIELD_VALUE:\n+\tcase RTE_FLOW_FIELD_ESP_SEQ_NUM:\n \t\tbreak;\n \tdefault:\n \t\treturn rte_flow_error_set(error, ENOTSUP,\n@@ -6763,6 +6765,7 @@ flow_hw_item_compare_width_supported(enum rte_flow_field_id field)\n \tswitch (field) {\n \tcase RTE_FLOW_FIELD_TAG:\n \tcase RTE_FLOW_FIELD_META:\n+\tcase RTE_FLOW_FIELD_ESP_SEQ_NUM:\n \t\treturn 32;\n \tcase RTE_FLOW_FIELD_RANDOM:\n \t\treturn 16;\n", "prefixes": [ "v6", "3/3" ] }