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GET /api/patches/138660/?format=api
{ "id": 138660, "url": "http://patchwork.dpdk.org/api/patches/138660/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20240321142414.1573453-1-kliteyn@nvidia.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240321142414.1573453-1-kliteyn@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240321142414.1573453-1-kliteyn@nvidia.com", "date": "2024-03-21T14:24:13", "name": "[1/2] net/mlx5/hws: fix rule resize status check", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "2ac6ebb3152bc92a09106a2aed1447eb9defa7e5", "submitter": { "id": 2925, "url": "http://patchwork.dpdk.org/api/people/2925/?format=api", "name": "Yevgeny Kliteynik", "email": "kliteyn@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patchwork.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20240321142414.1573453-1-kliteyn@nvidia.com/mbox/", "series": [ { "id": 31587, "url": "http://patchwork.dpdk.org/api/series/31587/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=31587", "date": "2024-03-21T14:24:13", "name": "[1/2] net/mlx5/hws: fix rule resize status check", "version": 1, "mbox": "http://patchwork.dpdk.org/series/31587/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/138660/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/138660/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 31E5E43D16;\n\tThu, 21 Mar 2024 15:24:56 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 01231427E1;\n\tThu, 21 Mar 2024 15:24:56 +0100 (CET)", "from NAM11-BN8-obe.outbound.protection.outlook.com\n (mail-bn8nam11on2041.outbound.protection.outlook.com [40.107.236.41])\n by mails.dpdk.org (Postfix) with ESMTP id 71209402F2\n for <dev@dpdk.org>; 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helo=mail.nvidia.com; pr=C", "From": "Yevgeny Kliteynik <kliteyn@nvidia.com>", "To": "<kliteyn@nvidia.com>, <viacheslavo@nvidia.com>, <thomas@monjalon.net>,\n <suanmingm@nvidia.com>, Dariusz Sosnowski <dsosnowski@nvidia.com>, Ori Kam\n <orika@nvidia.com>, Matan Azrad <matan@nvidia.com>", "CC": "<dev@dpdk.org>, <valex@nvidia.com>, <igozlan@nvidia.com>,\n <erezsh@nvidia.com>", "Subject": "[PATCH 1/2] net/mlx5/hws: fix rule resize status check", "Date": "Thu, 21 Mar 2024 16:24:13 +0200", "Message-ID": "<20240321142414.1573453-1-kliteyn@nvidia.com>", "X-Mailer": "git-send-email 2.27.0", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.35]", "X-ClientProxiedBy": "rnnvmail202.nvidia.com (10.129.68.7) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "BN1PEPF0000468C:EE_|SA1PR12MB5657:EE_", "X-MS-Office365-Filtering-Correlation-Id": "ac2b0412-28f4-4279-f61c-08dc49b2aab1", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n T2KPFoSUemUXcoTzaeKFhgepBGJbj9OvmLEkc0CaXzv3NoOdLp4oLhL0RxTK0LJQ+oFUbzazXrqAXCiTDDkF1a6+tYyVyEzLhfOzV0obJ0Aymf3fFi8wsCgOb+5szCJRM3FtCDTZ75DEO5C8gEIjSA2YVRLrUqmOkAxBIJ8hxpYyZ3f8Id14inN7VKmFhzh4V4b8PXMEXgxBcMupJLDdV+aM/6Xz3P3iy4RQmWC3gL4Dmn3VGzG1eQNE/pBqLM8kg7ZP/szp48WEfHlL+PbrhLvsWkgHpmEfSHDoLaF3A9dqWM4NJ22xMRyRVpRfhK5LatPmFCkIby1LgBX0HHI6mxKbt87dRUAakrDLJ7jM/WWr034qrvX313FyKYD2hx5L5kAXayWPqBuEsM7/kM09CE6CAVRBGpTbLO31KvYy9P5vPXPgxnC7eEu9pj5AbW+lMn9TX74ql0K5Vs+AYCoOMjGc6Nu4Im5pxibu7XEb2G+5tyNpId7sqaAnJ2+DCJboUhE0Pdjt1w6fr+SP1GxWb9qLP29AuXbs9Dz83CN9y/oOjfQkZMzjjMdj/RmHhv87sYgHI317UEC/9a4MvnI9iST28dzYkrCg6TU6zZTNVBG4UF69NVo6VUF/52WBiu8eoNYE/V/chvv1KvZr50AfpUKfwV7NLVHZb/xf/qaLIgyUc50LwazsnVWbxT1Emj9QjnGiDFV28SuNAW1oVh0zKOoUEE3we8ajRk5KUO4aC8CoW0Aj+eqYP39i10gBQhr+", "X-Forefront-Antispam-Report": "CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE;\n SFS:(13230031)(1800799015)(376005)(36860700004)(82310400014); DIR:OUT;\n SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "21 Mar 2024 14:24:49.4532 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n ac2b0412-28f4-4279-f61c-08dc49b2aab1", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BN1PEPF0000468C.namprd05.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "SA1PR12MB5657", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "The check to detect if a rule is in resize was done incorrectly,\nthis can lead to an incorrect function call upon completion for\nrules which are not in resize (move).\nSince the resize_info is in a union we cannot rely only on the\npointer value but also need to make sure the matcher is in resize\nprocess, this assures us the resize info is valid.\n\nFixes: 762feceb8294 (\"net/mlx5/hws: support resizable matchers\")\n\nSigned-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com>\nSigned-off-by: Alex Vesker <valex@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/net/mlx5/hws/mlx5dr_rule.c | 7 +++++++\n drivers/net/mlx5/hws/mlx5dr_rule.h | 6 +-----\n 2 files changed, 8 insertions(+), 5 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/hws/mlx5dr_rule.c b/drivers/net/mlx5/hws/mlx5dr_rule.c\nindex f14e1e6ecd..784f614d87 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_rule.c\n+++ b/drivers/net/mlx5/hws/mlx5dr_rule.c\n@@ -350,6 +350,13 @@ static void mlx5dr_rule_move_init(struct mlx5dr_rule *rule,\n \trule->resize_info->state = MLX5DR_RULE_RESIZE_STATE_WRITING;\n }\n \n+bool mlx5dr_rule_move_in_progress(struct mlx5dr_rule *rule)\n+{\n+\treturn mlx5dr_matcher_is_in_resize(rule->matcher) &&\n+\t rule->resize_info &&\n+\t rule->resize_info->state != MLX5DR_RULE_RESIZE_STATE_IDLE;\n+}\n+\n static int mlx5dr_rule_create_hws_fw_wqe(struct mlx5dr_rule *rule,\n \t\t\t\t\t struct mlx5dr_rule_attr *attr,\n \t\t\t\t\t uint8_t mt_idx,\ndiff --git a/drivers/net/mlx5/hws/mlx5dr_rule.h b/drivers/net/mlx5/hws/mlx5dr_rule.h\nindex 07adf9c5ad..dffaec1c0f 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_rule.h\n+++ b/drivers/net/mlx5/hws/mlx5dr_rule.h\n@@ -72,10 +72,6 @@ int mlx5dr_rule_move_hws_remove(struct mlx5dr_rule *rule,\n int mlx5dr_rule_move_hws_add(struct mlx5dr_rule *rule,\n \t\t\t struct mlx5dr_rule_attr *attr);\n \n-static inline bool mlx5dr_rule_move_in_progress(struct mlx5dr_rule *rule)\n-{\n-\treturn rule->resize_info &&\n-\t rule->resize_info->state != MLX5DR_RULE_RESIZE_STATE_IDLE;\n-}\n+bool mlx5dr_rule_move_in_progress(struct mlx5dr_rule *rule);\n \n #endif /* MLX5DR_RULE_H_ */\n", "prefixes": [ "1/2" ] }