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GET /api/patches/138661/?format=api
{ "id": 138661, "url": "http://patchwork.dpdk.org/api/patches/138661/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20240321142414.1573453-2-kliteyn@nvidia.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240321142414.1573453-2-kliteyn@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240321142414.1573453-2-kliteyn@nvidia.com", "date": "2024-03-21T14:24:14", "name": "[2/2] net/mlx5/hws: fix port ID for root table", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "2f1032794b2c096c9f2db81c5fe4f407551a752d", "submitter": { "id": 2925, "url": "http://patchwork.dpdk.org/api/people/2925/?format=api", "name": "Yevgeny Kliteynik", "email": "kliteyn@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patchwork.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20240321142414.1573453-2-kliteyn@nvidia.com/mbox/", "series": [ { "id": 31587, "url": "http://patchwork.dpdk.org/api/series/31587/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=31587", "date": "2024-03-21T14:24:13", "name": "[1/2] net/mlx5/hws: fix rule resize status check", "version": 1, "mbox": "http://patchwork.dpdk.org/series/31587/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/138661/comments/", "check": "warning", "checks": "http://patchwork.dpdk.org/api/patches/138661/checks/", "tags": {}, "related": [], "headers": { "Return-Path": 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Azrad <matan@nvidia.com>, Erez Shitrit\n <erezsh@nvidia.com>, Alex Vesker <valex@nvidia.com>", "CC": "<dev@dpdk.org>, <igozlan@nvidia.com>, <stable@dpdk.org>", "Subject": "[PATCH 2/2] net/mlx5/hws: fix port ID for root table", "Date": "Thu, 21 Mar 2024 16:24:14 +0200", "Message-ID": "<20240321142414.1573453-2-kliteyn@nvidia.com>", "X-Mailer": "git-send-email 2.27.0", "In-Reply-To": "<20240321142414.1573453-1-kliteyn@nvidia.com>", "References": "<20240321142414.1573453-1-kliteyn@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.35]", "X-ClientProxiedBy": "rnnvmail202.nvidia.com (10.129.68.7) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "BN1PEPF00004689:EE_|DM4PR12MB6109:EE_", "X-MS-Office365-Filtering-Correlation-Id": "c5a15ada-8904-40ce-3a60-08dc49b2b552", "X-LD-Processed": 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"CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE;\n SFS:(13230031)(1800799015)(82310400014)(376005)(36860700004); DIR:OUT;\n SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "21 Mar 2024 14:25:07.2651 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n c5a15ada-8904-40ce-3a60-08dc49b2b552", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BN1PEPF00004689.namprd05.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DM4PR12MB6109", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Erez Shitrit <erezsh@nvidia.com>\n\nIn root tables matcher and rule need to have their port-id, otherwise\nthe translate function that done in dpdk layer will not get the right\nattributes.\nFor that whenever the matcher is matching the source-port we need to get\nthe relevant port-id before calling the translate function.\n\nFixes: 405242c52dd5 (\"net/mlx5/hws: add rule object\")\nCc: stable@dpdk.org\n\nSigned-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com>\nSigned-off-by: Erez Shitrit <erezsh@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\nSigned-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com>\n---\n drivers/net/mlx5/hws/mlx5dr_matcher.c | 17 +++++++++++++++++\n drivers/net/mlx5/hws/mlx5dr_rule.c | 18 ++++++++++++++++++\n drivers/net/mlx5/mlx5_flow.h | 22 ++++++++++++++++++++++\n 3 files changed, 57 insertions(+)", "diff": "diff --git a/drivers/net/mlx5/hws/mlx5dr_matcher.c b/drivers/net/mlx5/hws/mlx5dr_matcher.c\nindex 1c64abfa57..aeff300467 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_matcher.c\n+++ b/drivers/net/mlx5/hws/mlx5dr_matcher.c\n@@ -1220,6 +1220,7 @@ static int mlx5dr_matcher_init_root(struct mlx5dr_matcher *matcher)\n \tstruct mlx5dv_flow_match_parameters *mask;\n \tstruct mlx5_flow_attr flow_attr = {0};\n \tstruct rte_flow_error rte_error;\n+\tstruct rte_flow_item *item;\n \tuint8_t match_criteria;\n \tint ret;\n \n@@ -1248,6 +1249,22 @@ static int mlx5dr_matcher_init_root(struct mlx5dr_matcher *matcher)\n \t\treturn rte_errno;\n \t}\n \n+\t/* We need the port id in case of matching representor */\n+\titem = matcher->mt[0].items;\n+\twhile (item->type != RTE_FLOW_ITEM_TYPE_END) {\n+\t\tif (item->type == RTE_FLOW_ITEM_TYPE_PORT_REPRESENTOR ||\n+\t\t item->type == RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT) {\n+\t\t\tret = flow_hw_get_port_id_from_ctx(ctx, &flow_attr.port_id);\n+\t\t\tif (ret) {\n+\t\t\t\tDR_LOG(ERR, \"Failed to get port id for dev %s\",\n+\t\t\t\t ctx->ibv_ctx->device->name);\n+\t\t\t\trte_errno = EINVAL;\n+\t\t\t\treturn rte_errno;\n+\t\t\t}\n+\t\t}\n+\t\t++item;\n+\t}\n+\n \tmask = simple_calloc(1, MLX5_ST_SZ_BYTES(fte_match_param) +\n \t\t\t offsetof(struct mlx5dv_flow_match_parameters, match_buf));\n \tif (!mask) {\ndiff --git a/drivers/net/mlx5/hws/mlx5dr_rule.c b/drivers/net/mlx5/hws/mlx5dr_rule.c\nindex 784f614d87..022263eb1d 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_rule.c\n+++ b/drivers/net/mlx5/hws/mlx5dr_rule.c\n@@ -687,10 +687,28 @@ static int mlx5dr_rule_create_root(struct mlx5dr_rule *rule,\n \tstruct mlx5dv_flow_match_parameters *value;\n \tstruct mlx5_flow_attr flow_attr = {0};\n \tstruct mlx5dv_flow_action_attr *attr;\n+\tconst struct rte_flow_item *cur_item;\n \tstruct rte_flow_error error;\n \tuint8_t match_criteria;\n \tint ret;\n \n+\t/* We need the port id in case of matching representor */\n+\tcur_item = items;\n+\twhile (cur_item->type != RTE_FLOW_ITEM_TYPE_END) {\n+\t\tif (cur_item->type == RTE_FLOW_ITEM_TYPE_PORT_REPRESENTOR ||\n+\t\t cur_item->type == RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT) {\n+\t\t\tret = flow_hw_get_port_id_from_ctx(rule->matcher->tbl->ctx,\n+\t\t\t\t\t\t\t &flow_attr.port_id);\n+\t\t\tif (ret) {\n+\t\t\t\tDR_LOG(ERR, \"Failed to get port id for dev %s\",\n+\t\t\t\t rule->matcher->tbl->ctx->ibv_ctx->device->name);\n+\t\t\t\trte_errno = EINVAL;\n+\t\t\t\treturn rte_errno;\n+\t\t\t}\n+\t\t}\n+\t\t++cur_item;\n+\t}\n+\n \tattr = simple_calloc(num_actions, sizeof(*attr));\n \tif (!attr) {\n \t\trte_errno = ENOMEM;\ndiff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h\nindex 34b5e0f45b..0065727a67 100644\n--- a/drivers/net/mlx5/mlx5_flow.h\n+++ b/drivers/net/mlx5/mlx5_flow.h\n@@ -2001,6 +2001,28 @@ flow_hw_get_reg_id(struct rte_eth_dev *dev,\n #endif\n }\n \n+static __rte_always_inline int\n+flow_hw_get_port_id_from_ctx(void *dr_ctx, uint32_t *port_val)\n+{\n+#if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)\n+\tuint32_t port;\n+\n+\tMLX5_ETH_FOREACH_DEV(port, NULL) {\n+\t\tstruct mlx5_priv *priv;\n+\t\tpriv = rte_eth_devices[port].data->dev_private;\n+\n+\t\tif (priv->dr_ctx == dr_ctx) {\n+\t\t\t*port_val = port;\n+\t\t\treturn 0;\n+\t\t}\n+\t}\n+#else\n+\tRTE_SET_USED(dr_ctx);\n+\tRTE_SET_USED(port_val);\n+#endif\n+\treturn -EINVAL;\n+}\n+\n /**\n * Get GENEVE TLV option FW information according type and class.\n *\n", "prefixes": [ "2/2" ] }