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GET /api/patches/138738/?format=api
{ "id": 138738, "url": "http://patchwork.dpdk.org/api/patches/138738/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20240322070923.244417-6-huangdengdui@huawei.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240322070923.244417-6-huangdengdui@huawei.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240322070923.244417-6-huangdengdui@huawei.com", "date": "2024-03-22T07:09:22", "name": "[v2,5/6] net/hns3: support setting lanes", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "6f2d8971c21f588d8bd63eb97e353eed545e9d1e", "submitter": { "id": 3066, "url": "http://patchwork.dpdk.org/api/people/3066/?format=api", "name": "huangdengdui", "email": "huangdengdui@huawei.com" }, "delegate": { "id": 319, "url": "http://patchwork.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20240322070923.244417-6-huangdengdui@huawei.com/mbox/", "series": [ { "id": 31593, "url": "http://patchwork.dpdk.org/api/series/31593/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=31593", "date": "2024-03-22T07:09:17", "name": "support setting lanes", "version": 2, "mbox": "http://patchwork.dpdk.org/series/31593/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/138738/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/138738/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 0585D43D1E;\n\tFri, 22 Mar 2024 08:10:09 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 867B042EB6;\n\tFri, 22 Mar 2024 08:09:39 +0100 (CET)", "from szxga06-in.huawei.com (szxga06-in.huawei.com [45.249.212.32])\n by mails.dpdk.org (Postfix) with ESMTP id 3102F42DE9\n for <dev@dpdk.org>; Fri, 22 Mar 2024 08:09:28 +0100 (CET)", "from mail.maildlp.com (unknown [172.19.88.234])\n by szxga06-in.huawei.com (SkyGuard) with ESMTP id 4V1D2G1zcKz1vx5R;\n Fri, 22 Mar 2024 15:08:38 +0800 (CST)", "from dggpeml500011.china.huawei.com (unknown [7.185.36.84])\n by mail.maildlp.com (Postfix) with ESMTPS id 572C3140384;\n Fri, 22 Mar 2024 15:09:25 +0800 (CST)", "from localhost.huawei.com (10.50.165.33) by\n dggpeml500011.china.huawei.com (7.185.36.84) with Microsoft SMTP Server\n (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.1.2507.35; Fri, 22 Mar 2024 15:09:25 +0800" ], "From": "Dengdui Huang <huangdengdui@huawei.com>", "To": "<dev@dpdk.org>", "CC": "<ferruh.yigit@amd.com>, <aman.deep.singh@intel.com>,\n <yuying.zhang@intel.com>, <thomas@monjalon.net>,\n <andrew.rybchenko@oktetlabs.ru>, <damodharam.ammepalli@broadcom.com>,\n <stephen@networkplumber.org>, <jerinjacobk@gmail.com>,\n <ajit.khaparde@broadcom.com>, <liuyonglong@huawei.com>,\n <fengchengwen@huawei.com>, <haijie1@huawei.com>, <lihuisong@huawei.com>", "Subject": "[PATCH v2 5/6] net/hns3: support setting lanes", "Date": "Fri, 22 Mar 2024 15:09:22 +0800", "Message-ID": "<20240322070923.244417-6-huangdengdui@huawei.com>", "X-Mailer": "git-send-email 2.33.0", "In-Reply-To": "<20240322070923.244417-1-huangdengdui@huawei.com>", "References": "<20240312075238.3319480-4-huangdengdui@huawei.com>\n <20240322070923.244417-1-huangdengdui@huawei.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.50.165.33]", "X-ClientProxiedBy": "dggems706-chm.china.huawei.com (10.3.19.183) To\n dggpeml500011.china.huawei.com (7.185.36.84)", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Some speeds can be achieved with different number of lanes. For example,\n100Gbps can be achieved using two lanes of 50Gbps or four lanes of 25Gbps.\nWhen use different lanes, the port cannot be up. This patch add support\nfor setting lanes and report lanes.\n\nIn addition, when reporting FEC capability, it is incorrect to calculate\nspeed_num from the speed function when one speed supports a different\nnumber of lanes. This patch modifies it together.\n\nSigned-off-by: Dengdui Huang <huangdengdui@huawei.com>\n---\n doc/guides/rel_notes/release_24_03.rst | 2 +\n drivers/net/hns3/hns3_cmd.h | 15 ++-\n drivers/net/hns3/hns3_common.c | 2 +\n drivers/net/hns3/hns3_ethdev.c | 158 ++++++++++++++++++-------\n drivers/net/hns3/hns3_ethdev.h | 2 +\n 5 files changed, 134 insertions(+), 45 deletions(-)", "diff": "diff --git a/doc/guides/rel_notes/release_24_03.rst b/doc/guides/rel_notes/release_24_03.rst\nindex b41b0028b2..c9b8740323 100644\n--- a/doc/guides/rel_notes/release_24_03.rst\n+++ b/doc/guides/rel_notes/release_24_03.rst\n@@ -193,6 +193,8 @@ New Features\n * Added power-saving during polling within the ``rte_event_dequeue_burst()`` API.\n * Added support for DMA adapter.\n \n+* **Added setting lanes for hns3 PF driver.**\n+ * This feature add support for setting lanes and report lanes.\n \n Removed Items\n -------------\ndiff --git a/drivers/net/hns3/hns3_cmd.h b/drivers/net/hns3/hns3_cmd.h\nindex 79a8c1edad..31ff7b35d8 100644\n--- a/drivers/net/hns3/hns3_cmd.h\n+++ b/drivers/net/hns3/hns3_cmd.h\n@@ -753,7 +753,9 @@ struct hns3_config_mac_mode_cmd {\n struct hns3_config_mac_speed_dup_cmd {\n \tuint8_t speed_dup;\n \tuint8_t mac_change_fec_en;\n-\tuint8_t rsv[22];\n+\tuint8_t rsv[4];\n+\tuint8_t lanes;\n+\tuint8_t rsv1[17];\n };\n \n #define HNS3_TQP_ENABLE_B\t\t0\n@@ -789,12 +791,15 @@ struct hns3_sfp_type {\n #define HNS3_FIBER_LINK_SPEED_1G_BIT\t\tBIT(0)\n #define HNS3_FIBER_LINK_SPEED_10G_BIT\t\tBIT(1)\n #define HNS3_FIBER_LINK_SPEED_25G_BIT\t\tBIT(2)\n-#define HNS3_FIBER_LINK_SPEED_50G_BIT\t\tBIT(3)\n-#define HNS3_FIBER_LINK_SPEED_100G_BIT\t\tBIT(4)\n+#define HNS3_FIBER_LINK_SPEED_50G_R2_BIT\tBIT(3)\n+#define HNS3_FIBER_LINK_SPEED_100G_R4_BIT\tBIT(4)\n #define HNS3_FIBER_LINK_SPEED_40G_BIT\t\tBIT(5)\n #define HNS3_FIBER_LINK_SPEED_100M_BIT\t\tBIT(6)\n #define HNS3_FIBER_LINK_SPEED_10M_BIT\t\tBIT(7)\n-#define HNS3_FIBER_LINK_SPEED_200G_BIT\t\tBIT(8)\n+#define HNS3_FIBER_LINK_SPEED_200G_EXT_BIT\tBIT(8)\n+#define HNS3_FIBER_LINK_SPEED_50G_R1_BIT\tBIT(9)\n+#define HNS3_FIBER_LINK_SPEED_100G_R2_BIT\tBIT(10)\n+#define HNS3_FIBER_LINK_SPEED_200G_R4_BIT\tBIT(11)\n \n #define HNS3_FIBER_FEC_AUTO_BIT\t\tBIT(0)\n #define HNS3_FIBER_FEC_BASER_BIT\tBIT(1)\n@@ -823,7 +828,7 @@ struct hns3_sfp_info_cmd {\n \tuint32_t supported_speed; /* speed supported by current media */\n \tuint32_t module_type;\n \tuint8_t fec_ability; /* supported fec modes, see HNS3_FIBER_FEC_XXX_BIT */\n-\tuint8_t rsv0;\n+\tuint8_t lanes;\n \tuint8_t pause_status;\n \tuint8_t rsv1[5];\n };\ndiff --git a/drivers/net/hns3/hns3_common.c b/drivers/net/hns3/hns3_common.c\nindex 28c26b049c..b6db012993 100644\n--- a/drivers/net/hns3/hns3_common.c\n+++ b/drivers/net/hns3/hns3_common.c\n@@ -93,6 +93,8 @@ hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)\n \n \tinfo->dev_capa = RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP |\n \t\t\t RTE_ETH_DEV_CAPA_FLOW_SHARED_OBJECT_KEEP;\n+\tif (!hns->is_vf)\n+\t\tinfo->dev_capa |= RTE_ETH_DEV_CAPA_SETTING_LANES;\n \tif (hns3_dev_get_support(hw, INDEP_TXRX))\n \t\tinfo->dev_capa |= RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |\n \t\t\t\t RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;\ndiff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c\nindex 1b380ac75f..7f36c193a6 100644\n--- a/drivers/net/hns3/hns3_ethdev.c\n+++ b/drivers/net/hns3/hns3_ethdev.c\n@@ -63,12 +63,12 @@ struct hns3_intr_state {\n \tuint32_t hw_err_state;\n };\n \n-#define HNS3_SPEEDS_SUPP_FEC (RTE_ETH_LINK_SPEED_10G | \\\n-\t\t\t RTE_ETH_LINK_SPEED_25G | \\\n-\t\t\t RTE_ETH_LINK_SPEED_40G | \\\n-\t\t\t RTE_ETH_LINK_SPEED_50G | \\\n-\t\t\t RTE_ETH_LINK_SPEED_100G | \\\n-\t\t\t RTE_ETH_LINK_SPEED_200G)\n+#define HNS3_SPEED_NUM_10G_BIT\tRTE_BIT32(1)\n+#define HNS3_SPEED_NUM_25G_BIT\tRTE_BIT32(2)\n+#define HNS3_SPEED_NUM_40G_BIT\tRTE_BIT32(3)\n+#define HNS3_SPEED_NUM_50G_BIT\tRTE_BIT32(4)\n+#define HNS3_SPEED_NUM_100G_BIT\tRTE_BIT32(5)\n+#define HNS3_SPEED_NUM_200G_BIT\tRTE_BIT32(6)\n \n static const struct rte_eth_fec_capa speed_fec_capa_tbl[] = {\n \t{ RTE_ETH_SPEED_NUM_10G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |\n@@ -2234,13 +2234,17 @@ hns3_get_firber_port_speed_capa(uint32_t supported_speed)\n \tif (supported_speed & HNS3_FIBER_LINK_SPEED_25G_BIT)\n \t\tspeed_capa |= RTE_ETH_LINK_SPEED_25G;\n \tif (supported_speed & HNS3_FIBER_LINK_SPEED_40G_BIT)\n-\t\tspeed_capa |= RTE_ETH_LINK_SPEED_40G;\n-\tif (supported_speed & HNS3_FIBER_LINK_SPEED_50G_BIT)\n+\t\tspeed_capa |= RTE_ETH_LINK_SPEED_40G_4LANES;\n+\tif (supported_speed & HNS3_FIBER_LINK_SPEED_50G_R1_BIT)\n \t\tspeed_capa |= RTE_ETH_LINK_SPEED_50G;\n-\tif (supported_speed & HNS3_FIBER_LINK_SPEED_100G_BIT)\n-\t\tspeed_capa |= RTE_ETH_LINK_SPEED_100G;\n-\tif (supported_speed & HNS3_FIBER_LINK_SPEED_200G_BIT)\n-\t\tspeed_capa |= RTE_ETH_LINK_SPEED_200G;\n+\tif (supported_speed & HNS3_FIBER_LINK_SPEED_50G_R2_BIT)\n+\t\tspeed_capa |= RTE_ETH_LINK_SPEED_50G_2LANES;\n+\tif (supported_speed & HNS3_FIBER_LINK_SPEED_100G_R4_BIT)\n+\t\tspeed_capa |= RTE_ETH_LINK_SPEED_100G_4LANES;\n+\tif (supported_speed & HNS3_FIBER_LINK_SPEED_100G_R2_BIT)\n+\t\tspeed_capa |= RTE_ETH_LINK_SPEED_100G_2LANES;\n+\tif (supported_speed & HNS3_FIBER_LINK_SPEED_200G_R4_BIT)\n+\t\tspeed_capa |= RTE_ETH_LINK_SPEED_200G_4LANES;\n \n \treturn speed_capa;\n }\n@@ -2308,6 +2312,7 @@ hns3_setup_linkstatus(struct rte_eth_dev *eth_dev,\n \tif (!mac->link_status)\n \t\tnew_link->link_speed = RTE_ETH_SPEED_NUM_NONE;\n \n+\tnew_link->link_lanes = mac->link_lanes;\n \tnew_link->link_duplex = mac->link_duplex;\n \tnew_link->link_status = mac->link_status ? RTE_ETH_LINK_UP : RTE_ETH_LINK_DOWN;\n \tnew_link->link_autoneg = mac->link_autoneg;\n@@ -2934,7 +2939,8 @@ hns3_map_tqp(struct hns3_hw *hw)\n }\n \n static int\n-hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)\n+hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t lanes,\n+\t\t\t uint8_t duplex)\n {\n \tstruct hns3_config_mac_speed_dup_cmd *req;\n \tstruct hns3_cmd_desc desc;\n@@ -2989,6 +2995,7 @@ hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)\n \t}\n \n \thns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1);\n+\treq->lanes = lanes;\n \n \tret = hns3_cmd_send(hw, &desc, 1);\n \tif (ret)\n@@ -3643,7 +3650,10 @@ hns3_mac_init(struct hns3_hw *hw)\n \n \tpf->support_sfp_query = true;\n \tmac->link_duplex = RTE_ETH_LINK_FULL_DUPLEX;\n-\tret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex);\n+\t/* If lane is set to 0, the firmware selects the default lane. */\n+\tmac->link_lanes = RTE_ETH_LANES_UNKNOWN;\n+\tret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_lanes,\n+\t\t\t\t\tmac->link_duplex);\n \tif (ret) {\n \t\tPMD_INIT_LOG(ERR, \"Config mac speed dup fail ret = %d\", ret);\n \t\treturn ret;\n@@ -4052,6 +4062,7 @@ hns3_get_sfp_info(struct hns3_hw *hw, struct hns3_mac *mac_info)\n \t\treturn 0;\n \n \tmac_info->link_speed = rte_le_to_cpu_32(resp->sfp_speed);\n+\tmac_info->link_lanes = resp->lanes;\n \t/*\n \t * if resp->supported_speed is 0, it means it's an old version\n \t * firmware, do not update these params.\n@@ -4088,16 +4099,18 @@ hns3_check_speed_dup(uint8_t duplex, uint32_t speed)\n }\n \n static int\n-hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)\n+hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t lanes,\n+\t\t uint8_t duplex)\n {\n \tstruct hns3_mac *mac = &hw->mac;\n \tint ret;\n \n \tduplex = hns3_check_speed_dup(duplex, speed);\n-\tif (mac->link_speed == speed && mac->link_duplex == duplex)\n+\tif (mac->link_speed == speed && mac->link_lanes == lanes &&\n+\t mac->link_duplex == duplex)\n \t\treturn 0;\n \n-\tret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex);\n+\tret = hns3_cfg_mac_speed_dup_hw(hw, speed, lanes, duplex);\n \tif (ret)\n \t\treturn ret;\n \n@@ -4106,6 +4119,7 @@ hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)\n \t\treturn ret;\n \n \tmac->link_speed = speed;\n+\tmac->link_lanes = lanes;\n \tmac->link_duplex = duplex;\n \n \treturn 0;\n@@ -4150,6 +4164,7 @@ hns3_update_fiber_link_info(struct hns3_hw *hw)\n \t\t}\n \n \t\tmac->link_speed = mac_info.link_speed;\n+\t\tmac->link_lanes = mac_info.link_lanes;\n \t\tmac->supported_speed = mac_info.supported_speed;\n \t\tmac->support_autoneg = mac_info.support_autoneg;\n \t\tmac->link_autoneg = mac_info.link_autoneg;\n@@ -4161,7 +4176,7 @@ hns3_update_fiber_link_info(struct hns3_hw *hw)\n \t}\n \n \t/* Config full duplex for SFP */\n-\treturn hns3_cfg_mac_speed_dup(hw, mac_info.link_speed,\n+\treturn hns3_cfg_mac_speed_dup(hw, mac_info.link_speed, mac_info.link_lanes,\n \t\t\t\t RTE_ETH_LINK_FULL_DUPLEX);\n }\n \n@@ -4512,11 +4527,11 @@ hns3_set_firber_default_support_speed(struct hns3_hw *hw)\n \tcase RTE_ETH_SPEED_NUM_40G:\n \t\treturn HNS3_FIBER_LINK_SPEED_40G_BIT;\n \tcase RTE_ETH_SPEED_NUM_50G:\n-\t\treturn HNS3_FIBER_LINK_SPEED_50G_BIT;\n+\t\treturn HNS3_FIBER_LINK_SPEED_50G_R2_BIT;\n \tcase RTE_ETH_SPEED_NUM_100G:\n-\t\treturn HNS3_FIBER_LINK_SPEED_100G_BIT;\n+\t\treturn HNS3_FIBER_LINK_SPEED_100G_R4_BIT;\n \tcase RTE_ETH_SPEED_NUM_200G:\n-\t\treturn HNS3_FIBER_LINK_SPEED_200G_BIT;\n+\t\treturn HNS3_FIBER_LINK_SPEED_200G_R4_BIT;\n \tdefault:\n \t\thns3_warn(hw, \"invalid speed %u Mbps.\", mac->link_speed);\n \t\treturn 0;\n@@ -4769,17 +4784,23 @@ hns3_convert_link_speeds2bitmap_fiber(uint32_t link_speeds)\n \tcase RTE_ETH_LINK_SPEED_25G:\n \t\tspeed_bit = HNS3_FIBER_LINK_SPEED_25G_BIT;\n \t\tbreak;\n-\tcase RTE_ETH_LINK_SPEED_40G:\n+\tcase RTE_ETH_LINK_SPEED_40G_4LANES:\n \t\tspeed_bit = HNS3_FIBER_LINK_SPEED_40G_BIT;\n \t\tbreak;\n \tcase RTE_ETH_LINK_SPEED_50G:\n-\t\tspeed_bit = HNS3_FIBER_LINK_SPEED_50G_BIT;\n+\t\tspeed_bit = HNS3_FIBER_LINK_SPEED_50G_R1_BIT;\n \t\tbreak;\n-\tcase RTE_ETH_LINK_SPEED_100G:\n-\t\tspeed_bit = HNS3_FIBER_LINK_SPEED_100G_BIT;\n+\tcase RTE_ETH_LINK_SPEED_50G_2LANES:\n+\t\tspeed_bit = HNS3_FIBER_LINK_SPEED_50G_R2_BIT;\n \t\tbreak;\n-\tcase RTE_ETH_LINK_SPEED_200G:\n-\t\tspeed_bit = HNS3_FIBER_LINK_SPEED_200G_BIT;\n+\tcase RTE_ETH_LINK_SPEED_100G_4LANES:\n+\t\tspeed_bit = HNS3_FIBER_LINK_SPEED_100G_R4_BIT;\n+\t\tbreak;\n+\tcase RTE_ETH_LINK_SPEED_100G_2LANES:\n+\t\tspeed_bit = HNS3_FIBER_LINK_SPEED_100G_R2_BIT;\n+\t\tbreak;\n+\tcase RTE_ETH_LINK_SPEED_200G_4LANES:\n+\t\tspeed_bit = HNS3_FIBER_LINK_SPEED_200G_R4_BIT;\n \t\tbreak;\n \tdefault:\n \t\tspeed_bit = 0;\n@@ -4900,7 +4921,7 @@ hns3_set_fiber_port_link_speed(struct hns3_hw *hw,\n \t\treturn 0;\n \t}\n \n-\treturn hns3_cfg_mac_speed_dup(hw, cfg->speed, cfg->duplex);\n+\treturn hns3_cfg_mac_speed_dup(hw, cfg->speed, cfg->lanes, cfg->duplex);\n }\n \n const char *\n@@ -4954,7 +4975,7 @@ hns3_apply_link_speed(struct hns3_hw *hw)\n \t\t\thns3_err(hw, \"failed to parse link mode, ret = %d\", ret);\n \t\t\treturn ret;\n \t\t}\n-\t\tcfg.speed = mode_onfo.speed_num;\n+\t\tcfg.lanes = mode_info.lanes;\n \t\tcfg.speed = mode_info.speed_num;\n \t\tcfg.duplex = mode_info.duplex;\n \t}\n@@ -5927,20 +5948,49 @@ hns3_reset_service(void *param)\n \t\thns3_msix_process(hns, reset_level);\n }\n \n+static uint32_t\n+hns3_speed_num_capa_bit(uint32_t speed_num)\n+{\n+\tuint32_t speed_bit;\n+\n+\tswitch (speed_num) {\n+\tcase RTE_ETH_SPEED_NUM_10G:\n+\t\tspeed_bit = HNS3_SPEED_NUM_10G_BIT;\n+\t\tbreak;\n+\tcase RTE_ETH_SPEED_NUM_25G:\n+\t\tspeed_bit = HNS3_SPEED_NUM_25G_BIT;\n+\t\tbreak;\n+\tcase RTE_ETH_SPEED_NUM_40G:\n+\t\tspeed_bit = HNS3_SPEED_NUM_40G_BIT;\n+\t\tbreak;\n+\tcase RTE_ETH_SPEED_NUM_50G:\n+\t\tspeed_bit = HNS3_SPEED_NUM_50G_BIT;\n+\t\tbreak;\n+\tcase RTE_ETH_SPEED_NUM_100G:\n+\t\tspeed_bit = HNS3_SPEED_NUM_100G_BIT;\n+\t\tbreak;\n+\tcase RTE_ETH_SPEED_NUM_200G:\n+\t\tspeed_bit = HNS3_SPEED_NUM_200G_BIT;\n+\t\tbreak;\n+\tdefault:\n+\t\tspeed_bit = 0;\n+\t\tbreak;\n+\t}\n+\n+\treturn speed_bit;\n+}\n+\n static uint32_t\n hns3_get_speed_fec_capa(struct rte_eth_fec_capa *speed_fec_capa,\n-\t\t\tuint32_t speed_capa)\n+\t\t\tuint32_t speed_num_capa)\n {\n \tuint32_t speed_bit;\n \tuint32_t num = 0;\n \tuint32_t i;\n \n \tfor (i = 0; i < RTE_DIM(speed_fec_capa_tbl); i++) {\n-\t\tspeed_bit =\n-\t\t\trte_eth_speed_bitflag(speed_fec_capa_tbl[i].speed,\n-\t\t\t\t\t RTE_ETH_LANES_UNKNOWN,\n-\t\t\t\t\t RTE_ETH_LINK_FULL_DUPLEX);\n-\t\tif ((speed_capa & speed_bit) == 0)\n+\t\tspeed_bit = hns3_speed_num_capa_bit(speed_fec_capa_tbl[i].speed);\n+\t\tif ((speed_num_capa & speed_bit) == 0)\n \t\t\tcontinue;\n \n \t\tspeed_fec_capa[num].speed = speed_fec_capa_tbl[i].speed;\n@@ -5951,6 +6001,34 @@ hns3_get_speed_fec_capa(struct rte_eth_fec_capa *speed_fec_capa,\n \treturn num;\n }\n \n+static uint32_t\n+hns3_get_speed_num_capa(struct hns3_hw *hw)\n+{\n+\tuint32_t speed_num_capa = 0;\n+\tuint32_t speed_capa;\n+\n+\tspeed_capa = hns3_get_speed_capa(hw);\n+\n+\tif (speed_capa & RTE_ETH_LINK_SPEED_10G)\n+\t\tspeed_num_capa |= HNS3_SPEED_NUM_10G_BIT;\n+\tif (speed_capa & RTE_ETH_LINK_SPEED_25G)\n+\t\tspeed_num_capa |= HNS3_SPEED_NUM_25G_BIT;\n+\tif (speed_capa & RTE_ETH_LINK_SPEED_40G_4LANES)\n+\t\tspeed_num_capa |= HNS3_SPEED_NUM_40G_BIT;\n+\tif (speed_capa & RTE_ETH_LINK_SPEED_50G)\n+\t\tspeed_num_capa |= HNS3_SPEED_NUM_50G_BIT;\n+\tif (speed_capa & RTE_ETH_LINK_SPEED_50G_2LANES)\n+\t\tspeed_num_capa |= HNS3_SPEED_NUM_50G_BIT;\n+\tif (speed_capa & RTE_ETH_LINK_SPEED_100G_4LANES)\n+\t\tspeed_num_capa |= HNS3_SPEED_NUM_100G_BIT;\n+\tif (speed_capa & RTE_ETH_LINK_SPEED_100G_2LANES)\n+\t\tspeed_num_capa |= HNS3_SPEED_NUM_100G_BIT;\n+\tif (speed_capa & RTE_ETH_LINK_SPEED_200G_4LANES)\n+\t\tspeed_num_capa |= HNS3_SPEED_NUM_200G_BIT;\n+\n+\treturn speed_num_capa;\n+}\n+\n static int\n hns3_fec_get_capability(struct rte_eth_dev *dev,\n \t\t\tstruct rte_eth_fec_capa *speed_fec_capa,\n@@ -5958,11 +6036,11 @@ hns3_fec_get_capability(struct rte_eth_dev *dev,\n {\n \tstruct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n \tunsigned int speed_num;\n-\tuint32_t speed_capa;\n+\tuint32_t speed_num_capa;\n \n-\tspeed_capa = hns3_get_speed_capa(hw);\n-\t/* speed_num counts number of speed capabilities */\n-\tspeed_num = rte_popcount32(speed_capa & HNS3_SPEEDS_SUPP_FEC);\n+\tspeed_num_capa = hns3_get_speed_num_capa(hw);\n+\t/* speed_num counts number of speed number capabilities */\n+\tspeed_num = rte_popcount32(speed_num_capa);\n \tif (speed_num == 0)\n \t\treturn -ENOTSUP;\n \n@@ -5975,7 +6053,7 @@ hns3_fec_get_capability(struct rte_eth_dev *dev,\n \t\treturn -EINVAL;\n \t}\n \n-\treturn hns3_get_speed_fec_capa(speed_fec_capa, speed_capa);\n+\treturn hns3_get_speed_fec_capa(speed_fec_capa, speed_num_capa);\n }\n \n \ndiff --git a/drivers/net/hns3/hns3_ethdev.h b/drivers/net/hns3/hns3_ethdev.h\nindex 12d8299def..070fc76420 100644\n--- a/drivers/net/hns3/hns3_ethdev.h\n+++ b/drivers/net/hns3/hns3_ethdev.h\n@@ -168,6 +168,7 @@ struct hns3_set_link_speed_cfg {\n \tuint32_t speed;\n \tuint8_t duplex : 1;\n \tuint8_t autoneg : 1;\n+\tuint8_t lanes : 4;\n };\n \n /* mac media type */\n@@ -190,6 +191,7 @@ struct hns3_mac {\n \tuint8_t link_autoneg : 1; /* RTE_ETH_LINK_[AUTONEG/FIXED] */\n \tuint8_t link_status : 1; /* RTE_ETH_LINK_[DOWN/UP] */\n \tuint32_t link_speed; /* RTE_ETH_SPEED_NUM_ */\n+\tuint8_t link_lanes; /* RTE_ETH_LANES_ */\n \t/*\n \t * Some firmware versions support only the SFP speed query. In addition\n \t * to the SFP speed query, some firmware supports the query of the speed\n", "prefixes": [ "v2", "5/6" ] }