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GET /api/patches/139721/?format=api
{ "id": 139721, "url": "http://patchwork.dpdk.org/api/patches/139721/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20240429095138.106849-6-mattias.ronnblom@ericsson.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240429095138.106849-6-mattias.ronnblom@ericsson.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240429095138.106849-6-mattias.ronnblom@ericsson.com", "date": "2024-04-29T09:51:37", "name": "[RFC,v3,5/6] eal: add atomic bit operations", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "204c1dc2d02a0beeab53d2176b763a0368318eba", "submitter": { "id": 1077, "url": "http://patchwork.dpdk.org/api/people/1077/?format=api", "name": "Mattias Rönnblom", "email": "mattias.ronnblom@ericsson.com" }, "delegate": { "id": 1, "url": "http://patchwork.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20240429095138.106849-6-mattias.ronnblom@ericsson.com/mbox/", "series": [ { "id": 31838, "url": "http://patchwork.dpdk.org/api/series/31838/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=31838", "date": "2024-04-29T09:51:32", "name": "Improve EAL bit operations API", "version": 3, "mbox": "http://patchwork.dpdk.org/series/31838/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/139721/comments/", "check": "pending", "checks": "http://patchwork.dpdk.org/api/patches/139721/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 4214243F49;\n\tMon, 29 Apr 2024 12:02:35 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id E5013402F0;\n\tMon, 29 Apr 2024 12:02:14 +0200 (CEST)", "from EUR01-DB5-obe.outbound.protection.outlook.com\n (mail-db5eur01on2057.outbound.protection.outlook.com [40.107.15.57])\n by mails.dpdk.org (Postfix) with ESMTP id 72F7C402D0\n for <dev@dpdk.org>; Mon, 29 Apr 2024 12:02:10 +0200 (CEST)", "from DU2PR04CA0257.eurprd04.prod.outlook.com (2603:10a6:10:28e::22)\n by DB5PR07MB9516.eurprd07.prod.outlook.com (2603:10a6:10:48e::6) with\n Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7519.34; Mon, 29 Apr\n 2024 10:02:09 +0000", "from DB5PEPF00014B90.eurprd02.prod.outlook.com\n (2603:10a6:10:28e:cafe::66) by DU2PR04CA0257.outlook.office365.com\n (2603:10a6:10:28e::22) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7519.34 via Frontend\n Transport; Mon, 29 Apr 2024 10:02:09 +0000", "from oa.msg.ericsson.com (192.176.1.74) by\n DB5PEPF00014B90.mail.protection.outlook.com (10.167.8.228) with Microsoft\n SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.20.7544.18 via Frontend Transport; Mon, 29 Apr 2024 10:02:09 +0000", "from seliicinfr00050.seli.gic.ericsson.se (153.88.142.248) by\n smtp-central.internal.ericsson.com (100.87.178.66) with Microsoft SMTP Server\n id 15.2.1544.9; Mon, 29 Apr 2024 12:02:08 +0200", "from breslau.. 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helo=oa.msg.ericsson.com; pr=C", "From": "=?utf-8?q?Mattias_R=C3=B6nnblom?= <mattias.ronnblom@ericsson.com>", "To": "<dev@dpdk.org>", "CC": "<hofors@lysator.liu.se>, Heng Wang <heng.wang@ericsson.com>,\n \"Stephen Hemminger\" <stephen@networkplumber.org>,\n Tyler Retzlaff <roretzla@linux.microsoft.com>,\n =?utf-8?q?Morten_Br=C3=B8rup?= <mb@smartsharesystems.com>, =?utf-8?q?Mattia?=\n\t=?utf-8?q?s_R=C3=B6nnblom?= <mattias.ronnblom@ericsson.com>", "Subject": "[RFC v3 5/6] eal: add atomic bit operations", "Date": "Mon, 29 Apr 2024 11:51:37 +0200", "Message-ID": "<20240429095138.106849-6-mattias.ronnblom@ericsson.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20240429095138.106849-1-mattias.ronnblom@ericsson.com>", "References": "<20240425085853.97888-2-mattias.ronnblom@ericsson.com>\n <20240429095138.106849-1-mattias.ronnblom@ericsson.com>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"UTF-8\"", "Content-Transfer-Encoding": "8bit", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "DB5PEPF00014B90:EE_|DB5PR07MB9516:EE_", "X-MS-Office365-Filtering-Correlation-Id": "a83bbca3-81e8-47c6-20d9-08dc68336ed5", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;\n ARA:13230031|82310400014|36860700004|1800799015|376005;", "X-Microsoft-Antispam-Message-Info": "=?utf-8?q?DTxfzCQPNMUnAKJcaXdeu1YA/LKmvHz?=\n\t=?utf-8?q?ds8nFa0Aa+R8dPFArARJYyv45mgomBqiF72/QuAJMMEYEgPcK/rnDg5ffTKVWUKJE?=\n\t=?utf-8?q?xVfpefouKGhKYffUdj3kWvMTYgHYmPMaqCQy23/Oy775ErrlMW/MzNEK0Y1bulJFo?=\n\t=?utf-8?q?fm+60PunVecyA5btGEA3BKkqBESlbzfEjSksZciu1Rvef908/cdqVX+0PwNHRDxn1?=\n\t=?utf-8?q?J81eCBYYp2rtu99sJltIbkoRMIZlsXBvwahJ7V57TJxYqHANL8kro5c4lD3IDt+Pv?=\n\t=?utf-8?q?83xIQKept87fr5wTE4MNxhYFWYhy9u+QJiTF9gEE848/S2YBQuPEXfcJRqIO7Oy+d?=\n\t=?utf-8?q?VNEi3qK9eGa0uMOuYTIs9mSp4TI+RhsvwXlxvDjt1fb1/tt7fIcbQGROE33TpT2x3?=\n\t=?utf-8?q?lH4iqObyVT9fonppnzhvcvQVwMdwsJsFRSM+AYXXQ+5OL/AIqmHU1rj99NJ9XteKR?=\n\t=?utf-8?q?IDtJpYGrFanRUDrsJlshlpGCkreihMtPR+iAon0zca54OsKmHKeVqbJhZk/LdOdoX?=\n\t=?utf-8?q?vVwwJn72HQgFIgF9UTjyZcL8qCxvvnDF2uClKpuoXgHcE+sqHCJp3tXgd9oxVHxpg?=\n\t=?utf-8?q?DIPDmV64ToxRdDsb6hIDL54CvFT2zY7JA2oAmznZQKTlCU5SA0Q329od6HNnuLuhl?=\n\t=?utf-8?q?d36bTTXlUgId3raCTABVPRdR47tayTQOysylhZK0tPn20KYXG+eNdNeTX0Y5EOBTu?=\n\t=?utf-8?q?X07qWQX6dnLSiknNBIGCFuAt/zhKHZ3AC5QJYx0d35y7xJQknNlkLTpYMlf61ZCYW?=\n\t=?utf-8?q?V9sNHCEIhQvRYwVnQ6E/ljVH72SCfefId+oMPoqpF+xQwOvoIAALuo9Bp4Fx+BMu8?=\n\t=?utf-8?q?P1lSWqmFIvfuHQbcIfFh+sqrylg6wrywjNDWrUt03YiXT/AeVk5M7UuwSqAOMb8EW?=\n\t=?utf-8?q?g6AKS/737ovdg8fi4G4mSs6WVM9KucV8s3o3ckQxVXMGtsdCbfvd2gMAPjNwWgSaj?=\n\t=?utf-8?q?nXU45Xjg7MxtgEMuKrMyXClU49bLf8txvQpmgH5YsMV4J2ZKLOhzZsVa13yo/Olw0?=\n\t=?utf-8?q?KOrRi1RM5NBJa8uUJdKi8RlNCEuLhgP6VJuMtdLqwZhPwz2FVlRqjYfx6TsAk+QIk?=\n\t=?utf-8?q?jEpkMLpGNJ5EfOyWus79Qkkymes9KhfC12AQTWX+kmideyGdaWB/CctOiw1HA1LDj?=\n\t=?utf-8?q?jw5q2Kn29PTuRaYrbrscJzpSyMy/QRCE9x/rGa8IvIDQsHs96mH24fnL9LEVodEzm?=\n\t=?utf-8?q?nXF65Sb4rUG+TAUywtxnxb6Z8ebntp6tikLkJ6v1sVwgMJv5N9tqvsHnVs+moUWW0?=\n\t=?utf-8?q?1f7gVksyA78kgB/tBBAhkdHWOeQLH/2+Zs28ld5jTWcJfhLcQ/s0H34sblSit0uNF?=\n\t=?utf-8?q?vWjcEhVxFveP?=", "X-Forefront-Antispam-Report": "CIP:192.176.1.74; CTRY:SE; LANG:en; SCL:1; SRV:;\n IPV:NLI; SFV:NSPM; H:oa.msg.ericsson.com; PTR:office365.se.ericsson.net;\n CAT:NONE; SFS:(13230031)(82310400014)(36860700004)(1800799015)(376005);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "ericsson.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "29 Apr 2024 10:02:09.1068 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n a83bbca3-81e8-47c6-20d9-08dc68336ed5", "X-MS-Exchange-CrossTenant-Id": "92e84ceb-fbfd-47ab-be52-080c6b87953f", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=92e84ceb-fbfd-47ab-be52-080c6b87953f; Ip=[192.176.1.74];\n Helo=[oa.msg.ericsson.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DB5PEPF00014B90.eurprd02.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DB5PR07MB9516", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Add atomic bit test/set/clear/assign and test-and-set/clear functions.\n\nAll atomic bit functions allow (and indeed, require) the caller to\nspecify a memory order.\n\nRFC v3:\n * Work around lack of C++ support for _Generic (Tyler Retzlaff).\n\nRFC v2:\n o Add rte_bit_atomic_test_and_assign() (for consistency).\n o Fix bugs in rte_bit_atomic_test_and_[set|clear]().\n o Use <rte_stdatomics.h> to support MSVC.\n\nSigned-off-by: Mattias Rönnblom <mattias.ronnblom@ericsson.com>\n---\n lib/eal/include/rte_bitops.h | 371 +++++++++++++++++++++++++++++++++++\n 1 file changed, 371 insertions(+)", "diff": "diff --git a/lib/eal/include/rte_bitops.h b/lib/eal/include/rte_bitops.h\nindex eac3f8b86a..2af5355a8a 100644\n--- a/lib/eal/include/rte_bitops.h\n+++ b/lib/eal/include/rte_bitops.h\n@@ -21,6 +21,7 @@\n \n #include <rte_compat.h>\n #include <rte_debug.h>\n+#include <rte_stdatomic.h>\n \n #ifdef __cplusplus\n extern \"C\" {\n@@ -342,6 +343,177 @@ extern \"C\" {\n \t\t uint32_t *: __rte_bit_once_assign32,\t\t\t\\\n \t\t uint64_t *: __rte_bit_once_assign64)(addr, nr, value)\n \n+/**\n+ * @warning\n+ * @b EXPERIMENTAL: this API may change without prior notice.\n+ *\n+ * Test if a particular bit in a word is set with a particular memory\n+ * order.\n+ *\n+ * Test a bit with the resulting memory load ordered as per the\n+ * specified memory order.\n+ *\n+ * @param addr\n+ * A pointer to the word to query.\n+ * @param nr\n+ * The index of the bit.\n+ * @param memory_order\n+ * The memory order to use. See <rte_stdatomics.h> for details.\n+ * @return\n+ * Returns true if the bit is set, and false otherwise.\n+ */\n+#define rte_bit_atomic_test(addr, nr, memory_order)\t\t\t\\\n+\t_Generic((addr),\t\t\t\t\t\t\\\n+\t\t uint32_t *: __rte_bit_atomic_test32,\t\t\t\\\n+\t\t uint64_t *: __rte_bit_atomic_test64)(addr, nr, memory_order)\n+\n+/**\n+ * @warning\n+ * @b EXPERIMENTAL: this API may change without prior notice.\n+ *\n+ * Atomically set bit in word.\n+ *\n+ * Atomically set bit specified by @c nr in the word pointed to by @c\n+ * addr to '1', with the memory ordering as specified by @c\n+ * memory_order.\n+ *\n+ * @param addr\n+ * A pointer to the word to modify.\n+ * @param nr\n+ * The index of the bit.\n+ * @param memory_order\n+ * The memory order to use. See <rte_stdatomics.h> for details.\n+ */\n+#define rte_bit_atomic_set(addr, nr, memory_order)\t\t\t\\\n+\t_Generic((addr),\t\t\t\t\t\t\\\n+\t\t uint32_t *: __rte_bit_atomic_set32,\t\t\t\\\n+\t\t uint64_t *: __rte_bit_atomic_set64)(addr, nr, memory_order)\n+\n+/**\n+ * @warning\n+ * @b EXPERIMENTAL: this API may change without prior notice.\n+ *\n+ * Atomically clear bit in word.\n+ *\n+ * Atomically set bit specified by @c nr in the word pointed to by @c\n+ * addr to '0', with the memory ordering as specified by @c\n+ * memory_order.\n+ *\n+ * @param addr\n+ * A pointer to the word to modify.\n+ * @param nr\n+ * The index of the bit.\n+ * @param memory_order\n+ * The memory order to use. See <rte_stdatomics.h> for details.\n+ */\n+#define rte_bit_atomic_clear(addr, nr, memory_order)\t\t\t\\\n+\t_Generic((addr),\t\t\t\t\t\t\\\n+\t\t uint32_t *: __rte_bit_atomic_clear32,\t\t\t\\\n+\t\t uint64_t *: __rte_bit_atomic_clear64)(addr, nr, memory_order)\n+\n+/**\n+ * @warning\n+ * @b EXPERIMENTAL: this API may change without prior notice.\n+ *\n+ * Atomically assign a value to bit in word.\n+ *\n+ * Atomically set bit specified by @c nr in the word pointed to by @c\n+ * addr to the value indicated by @c value, with the memory ordering\n+ * as specified with @c memory_order.\n+ *\n+ * @param addr\n+ * A pointer to the word to modify.\n+ * @param nr\n+ * The index of the bit.\n+ * @param value\n+ * The new value of the bit - true for '1', or false for '0'.\n+ * @param memory_order\n+ * The memory order to use. See <rte_stdatomics.h> for details.\n+ */\n+#define rte_bit_atomic_assign(addr, nr, value, memory_order)\t\t\\\n+\t_Generic((addr),\t\t\t\t\t\t\\\n+\t\t uint32_t *: __rte_bit_atomic_assign32,\t\t\t\\\n+\t\t uint64_t *: __rte_bit_atomic_assign64)(addr, nr, value, \\\n+\t\t\t\t\t\t\tmemory_order)\n+\n+/**\n+ * @warning\n+ * @b EXPERIMENTAL: this API may change without prior notice.\n+ *\n+ * Atomically test and set a bit in word.\n+ *\n+ * Atomically test and set bit specified by @c nr in the word pointed\n+ * to by @c addr to '1', with the memory ordering as specified with @c\n+ * memory_order.\n+ *\n+ * @param addr\n+ * A pointer to the word to modify.\n+ * @param nr\n+ * The index of the bit.\n+ * @param memory_order\n+ * The memory order to use. See <rte_stdatomics.h> for details.\n+ * @return\n+ * Returns true if the bit was set, and false otherwise.\n+ */\n+#define rte_bit_atomic_test_and_set(addr, nr, memory_order)\t\t\\\n+\t_Generic((addr),\t\t\t\t\t\t\\\n+\t\t uint32_t *: __rte_bit_atomic_test_and_set32,\t\t\\\n+\t\t uint64_t *: __rte_bit_atomic_test_and_set64)(addr, nr,\t\\\n+\t\t\t\t\t\t\t memory_order)\n+\n+/**\n+ * @warning\n+ * @b EXPERIMENTAL: this API may change without prior notice.\n+ *\n+ * Atomically test and clear a bit in word.\n+ *\n+ * Atomically test and clear bit specified by @c nr in the word\n+ * pointed to by @c addr to '0', with the memory ordering as specified\n+ * with @c memory_order.\n+ *\n+ * @param addr\n+ * A pointer to the word to modify.\n+ * @param nr\n+ * The index of the bit.\n+ * @param memory_order\n+ * The memory order to use. See <rte_stdatomics.h> for details.\n+ * @return\n+ * Returns true if the bit was set, and false otherwise.\n+ */\n+#define rte_bit_atomic_test_and_clear(addr, nr, memory_order)\t\t\\\n+\t_Generic((addr),\t\t\t\t\t\t\\\n+\t\t uint32_t *: __rte_bit_atomic_test_and_clear32,\t\t\\\n+\t\t uint64_t *: __rte_bit_atomic_test_and_clear64)(addr, nr, \\\n+\t\t\t\t\t\t\t\tmemory_order)\n+\n+/**\n+ * @warning\n+ * @b EXPERIMENTAL: this API may change without prior notice.\n+ *\n+ * Atomically test and assign a bit in word.\n+ *\n+ * Atomically test and assign bit specified by @c nr in the word\n+ * pointed to by @c addr the value specified by @c value, with the\n+ * memory ordering as specified with @c memory_order.\n+ *\n+ * @param addr\n+ * A pointer to the word to modify.\n+ * @param nr\n+ * The index of the bit.\n+ * @param value\n+ * The new value of the bit - true for '1', or false for '0'.\n+ * @param memory_order\n+ * The memory order to use. See <rte_stdatomics.h> for details.\n+ * @return\n+ * Returns true if the bit was set, and false otherwise.\n+ */\n+#define rte_bit_atomic_test_and_assign(addr, nr, value, memory_order)\t\\\n+\t_Generic((addr),\t\t\t\t\t\t\\\n+\t\t uint32_t *: __rte_bit_atomic_test_and_assign32,\t\\\n+\t\t uint64_t *: __rte_bit_atomic_test_and_assign64)(addr, nr, \\\n+\t\t\t\t\t\t\t\t value, \\\n+\t\t\t\t\t\t\t\t memory_order)\n+\n #define __RTE_GEN_BIT_TEST(name, size, qualifier)\t\t\t\\\n \tstatic inline bool\t\t\t\t\t\t\\\n \tname(const qualifier uint ## size ## _t *addr, unsigned int nr)\t\\\n@@ -429,6 +601,131 @@ __rte_bit_once_assign64(volatile uint64_t *addr, unsigned int nr, bool value)\n \t\t__rte_bit_once_clear64(addr, nr);\n }\n \n+#define __RTE_GEN_BIT_ATOMIC_TEST(size)\t\t\t\t\t\\\n+\tstatic inline bool\t\t\t\t\t\t\\\n+\t__rte_bit_atomic_test ## size(const uint ## size ## _t *addr,\t\\\n+\t\t\t\t unsigned int nr, int memory_order) \\\n+\t{\t\t\t\t\t\t\t\t\\\n+\t\tRTE_ASSERT(nr < size);\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tconst RTE_ATOMIC(uint ## size ## _t) *a_addr =\t\t\\\n+\t\t\t(const RTE_ATOMIC(uint ## size ## _t) *)addr;\t\\\n+\t\tuint ## size ## _t mask = (uint ## size ## _t)1 << nr;\t\\\n+\t\treturn rte_atomic_load_explicit(a_addr, memory_order) & mask; \\\n+\t}\n+\n+#define __RTE_GEN_BIT_ATOMIC_SET(size)\t\t\t\t\t\\\n+\tstatic inline void\t\t\t\t\t\t\\\n+\t__rte_bit_atomic_set ## size(uint ## size ## _t *addr,\t\t\\\n+\t\t\t\t unsigned int nr, int memory_order)\t\\\n+\t{\t\t\t\t\t\t\t\t\\\n+\t\tRTE_ASSERT(nr < size);\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tRTE_ATOMIC(uint ## size ## _t) *a_addr =\t\t\\\n+\t\t\t(RTE_ATOMIC(uint ## size ## _t) *)addr;\t\t\\\n+\t\tuint ## size ## _t mask = (uint ## size ## _t)1 << nr;\t\\\n+\t\trte_atomic_fetch_or_explicit(a_addr, mask, memory_order); \\\n+\t}\n+\n+#define __RTE_GEN_BIT_ATOMIC_CLEAR(size)\t\t\t\t\\\n+\tstatic inline void\t\t\t\t\t\t\\\n+\t__rte_bit_atomic_clear ## size(uint ## size ## _t *addr,\t\\\n+\t\t\t\t unsigned int nr, int memory_order) \\\n+\t{\t\t\t\t\t\t\t\t\\\n+\t\tRTE_ASSERT(nr < size);\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tRTE_ATOMIC(uint ## size ## _t) *a_addr =\t\t\\\n+\t\t\t(RTE_ATOMIC(uint ## size ## _t) *)addr;\t\t\\\n+\t\tuint ## size ## _t mask = (uint ## size ## _t)1 << nr;\t\\\n+\t\trte_atomic_fetch_and_explicit(a_addr, ~mask, memory_order); \\\n+\t}\n+\n+#define __RTE_GEN_BIT_ATOMIC_ASSIGN(size)\t\t\t\t\\\n+\tstatic inline void\t\t\t\t\t\t\\\n+\t__rte_bit_atomic_assign ## size(uint ## size ## _t *addr,\t\\\n+\t\t\t\t\tunsigned int nr, bool value,\t\\\n+\t\t\t\t\tint memory_order)\t\t\\\n+\t{\t\t\t\t\t\t\t\t\\\n+\t\tif (value)\t\t\t\t\t\t\\\n+\t\t\t__rte_bit_atomic_set ## size(addr, nr, memory_order); \\\n+\t\telse\t\t\t\t\t\t\t\\\n+\t\t\t__rte_bit_atomic_clear ## size(addr, nr,\t\\\n+\t\t\t\t\t\t memory_order);\t\\\n+\t}\n+\n+#define __RTE_GEN_BIT_ATOMIC_TEST_AND_ASSIGN(size)\t\t\t\\\n+\tstatic inline bool\t\t\t\t\t\t\\\n+\t__rte_bit_atomic_test_and_assign ## size(uint ## size ## _t *addr, \\\n+\t\t\t\t\t\t unsigned int nr,\t\\\n+\t\t\t\t\t\t bool value,\t\t\\\n+\t\t\t\t\t\t int memory_order)\t\\\n+\t{\t\t\t\t\t\t\t\t\\\n+\t\tRTE_ASSERT(nr < size);\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tRTE_ATOMIC(uint ## size ## _t) *a_addr =\t\t\\\n+\t\t\t(RTE_ATOMIC(uint ## size ## _t) *)addr;\t\t\\\n+\t\tuint ## size ## _t before;\t\t\t\t\\\n+\t\tuint ## size ## _t target;\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tbefore = rte_atomic_load_explicit(a_addr,\t\t\\\n+\t\t\t\t\t\t rte_memory_order_relaxed); \\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tdo {\t\t\t\t\t\t\t\\\n+\t\t\ttarget = before;\t\t\t\t\\\n+\t\t\t__rte_bit_assign ## size(&target, nr, value);\t\\\n+\t\t} while (!rte_atomic_compare_exchange_weak_explicit(\t\\\n+\t\t\t\ta_addr, &before, target,\t\t\\\n+\t\t\t\trte_memory_order_relaxed,\t\t\\\n+\t\t\t\tmemory_order));\t\t\t\t\\\n+\t\treturn __rte_bit_test ## size(&before, nr);\t\t\\\n+\t}\n+\n+#define __RTE_GEN_BIT_ATOMIC_OPS(size)\t\t\t\\\n+\t__RTE_GEN_BIT_ATOMIC_TEST(size)\t\t\t\\\n+\t__RTE_GEN_BIT_ATOMIC_SET(size)\t\t\t\\\n+\t__RTE_GEN_BIT_ATOMIC_CLEAR(size)\t\t\\\n+\t__RTE_GEN_BIT_ATOMIC_ASSIGN(size)\t\t\\\n+\t__RTE_GEN_BIT_ATOMIC_TEST_AND_ASSIGN(size)\n+\n+__RTE_GEN_BIT_ATOMIC_OPS(32)\n+__RTE_GEN_BIT_ATOMIC_OPS(64)\n+\n+__rte_experimental\n+static inline bool\n+__rte_bit_atomic_test_and_set32(uint32_t *addr, unsigned int nr,\n+\t\t\t int memory_order)\n+{\n+\treturn __rte_bit_atomic_test_and_assign32(addr, nr, true,\n+\t\t\t\t\t\t memory_order);\n+}\n+\n+__rte_experimental\n+static inline bool\n+__rte_bit_atomic_test_and_clear32(uint32_t *addr, unsigned int nr,\n+\t\t\t\tint memory_order)\n+{\n+\treturn __rte_bit_atomic_test_and_assign32(addr, nr, false,\n+\t\t\t\t\t\t memory_order);\n+}\n+\n+__rte_experimental\n+static inline bool\n+__rte_bit_atomic_test_and_set64(uint64_t *addr, unsigned int nr,\n+\t\t\t int memory_order)\n+{\n+\treturn __rte_bit_atomic_test_and_assign64(addr, nr, true,\n+\t\t\t\t\t\t memory_order);\n+}\n+\n+__rte_experimental\n+static inline bool\n+__rte_bit_atomic_test_and_clear64(uint64_t *addr, unsigned int nr,\n+\t\t\t int memory_order)\n+{\n+\treturn __rte_bit_atomic_test_and_assign64(addr, nr, false,\n+\t\t\t\t\t\t memory_order);\n+}\n+\n /*------------------------ 32-bit relaxed operations ------------------------*/\n \n /**\n@@ -1128,6 +1425,14 @@ rte_log2_u64(uint64_t v)\n #undef rte_bit_once_clear\n #undef rte_bit_once_assign\n \n+#undef rte_bit_atomic_test\n+#undef rte_bit_atomic_set\n+#undef rte_bit_atomic_clear\n+#undef rte_bit_atomic_assign\n+#undef rte_bit_atomic_test_and_set\n+#undef rte_bit_atomic_test_and_clear\n+#undef rte_bit_atomic_test_and_assign\n+\n #define __RTE_BIT_OVERLOAD_SZ_2(fun, qualifier, size, arg1_type, arg1_name) \\\n \tstatic inline void\t\t\t\t\t\t\\\n \trte_bit_ ## fun(qualifier uint ## size ## _t *addr,\t\t\\\n@@ -1171,6 +1476,59 @@ rte_log2_u64(uint64_t v)\n \t__RTE_BIT_OVERLOAD_SZ_3(fun, qualifier, 64, arg1_type, arg1_name, \\\n \t\t\t\targ2_type, arg2_name)\n \n+#define __RTE_BIT_OVERLOAD_SZ_3R(fun, qualifier, size, ret_type, arg1_type, \\\n+\t\t\t\t arg1_name, arg2_type, arg2_name)\t\\\n+\tstatic inline ret_type\t\t\t\t\t\t\\\n+\trte_bit_ ## fun(uint ## size ## _t *addr, arg1_type arg1_name,\t\\\n+\t\t\targ2_type arg2_name)\t\t\t\t\\\n+\t{\t\t\t\t\t\t\t\t\\\n+\t\treturn __rte_bit_ ## fun ## size(addr, arg1_name, arg2_name); \\\n+\t}\n+\n+#define __RTE_BIT_OVERLOAD_3R(fun, qualifier, ret_type, arg1_type, arg1_name, \\\n+\t\t\t arg2_type, arg2_name)\t\t\t\\\n+\t__RTE_BIT_OVERLOAD_SZ_3R(fun, qualifier, 32, ret_type, arg1_type, \\\n+\t\t\t\t arg1_name, arg2_type, arg2_name)\t\\\n+\t__RTE_BIT_OVERLOAD_SZ_3R(fun, qualifier, 64, ret_type, arg1_type, \\\n+\t\t\t\t arg1_name, arg2_type, arg2_name)\n+\n+#define __RTE_BIT_OVERLOAD_SZ_4(fun, qualifier, size, arg1_type, arg1_name, \\\n+\t\t\t\targ2_type, arg2_name, arg3_type, arg3_name) \\\n+\tstatic inline void\t\t\t\t\t\t\\\n+\trte_bit_ ## fun(uint ## size ## _t *addr, arg1_type arg1_name,\t\\\n+\t\t\targ2_type arg2_name, arg3_type arg3_name)\t\\\n+\t{\t\t\t\t\t\t\t\t\\\n+\t\t__rte_bit_ ## fun ## size(addr, arg1_name, arg2_name,\t\\\n+\t\t\t\t\t arg3_name);\t\t \\\n+\t}\n+\n+#define __RTE_BIT_OVERLOAD_4(fun, qualifier, arg1_type, arg1_name, arg2_type, \\\n+\t\t\t arg2_name, arg3_type, arg3_name)\t\t\\\n+\t__RTE_BIT_OVERLOAD_SZ_4(fun, qualifier, 32, arg1_type, arg1_name, \\\n+\t\t\t\targ2_type, arg2_name, arg3_type, arg3_name) \\\n+\t__RTE_BIT_OVERLOAD_SZ_4(fun, qualifier, 64, arg1_type, arg1_name, \\\n+\t\t\t\targ2_type, arg2_name, arg3_type, arg3_name)\n+\n+#define __RTE_BIT_OVERLOAD_SZ_4R(fun, qualifier, size, ret_type, arg1_type, \\\n+\t\t\t\t arg1_name, arg2_type, arg2_name, arg3_type, \\\n+\t\t\t\t arg3_name)\t\t\t\t\\\n+\tstatic inline ret_type\t\t\t\t\t\t\\\n+\trte_bit_ ## fun(uint ## size ## _t *addr, arg1_type arg1_name,\t\\\n+\t\t\targ2_type arg2_name, arg3_type arg3_name)\t\\\n+\t{\t\t\t\t\t\t\t\t\\\n+\t\treturn __rte_bit_ ## fun ## size(addr, arg1_name, arg2_name, \\\n+\t\t\t\t\t\t arg3_name);\t\t\\\n+\t}\n+\n+#define __RTE_BIT_OVERLOAD_4R(fun, qualifier, ret_type, arg1_type, arg1_name, \\\n+\t\t\t arg2_type, arg2_name, arg3_type, arg3_name) \\\n+\t__RTE_BIT_OVERLOAD_SZ_4R(fun, qualifier, 32, ret_type, arg1_type, \\\n+\t\t\t\t arg1_name, arg2_type, arg2_name, arg3_type, \\\n+\t\t\t\t arg3_name)\t\t\t\t\\\n+\t__RTE_BIT_OVERLOAD_SZ_4R(fun, qualifier, 64, ret_type, arg1_type, \\\n+\t\t\t\t arg1_name, arg2_type, arg2_name, arg3_type, \\\n+\t\t\t\t arg3_name)\n+\n __RTE_BIT_OVERLOAD_2R(test, const, bool, unsigned int, nr)\n __RTE_BIT_OVERLOAD_2(set, , unsigned int, nr)\n __RTE_BIT_OVERLOAD_2(clear, , unsigned int, nr)\n@@ -1181,6 +1539,19 @@ __RTE_BIT_OVERLOAD_2(once_set, volatile, unsigned int, nr)\n __RTE_BIT_OVERLOAD_2(once_clear, volatile, unsigned int, nr)\n __RTE_BIT_OVERLOAD_3(once_assign, volatile, unsigned int, nr, bool, value)\n \n+__RTE_BIT_OVERLOAD_3R(atomic_test, const, bool, unsigned int, nr,\t\\\n+\t\t int, memory_order)\n+__RTE_BIT_OVERLOAD_3(atomic_set,, unsigned int, nr, int, memory_order)\n+__RTE_BIT_OVERLOAD_3(atomic_clear,, unsigned int, nr, int, memory_order)\n+__RTE_BIT_OVERLOAD_4(atomic_assign,, unsigned int, nr, bool, value,\n+\t\t int, memory_order)\n+__RTE_BIT_OVERLOAD_3R(atomic_test_and_set,, bool, unsigned int, nr,\n+\t\t int, memory_order)\n+__RTE_BIT_OVERLOAD_3R(atomic_test_and_clear,, bool, unsigned int, nr,\n+\t\t int, memory_order)\n+__RTE_BIT_OVERLOAD_4R(atomic_test_and_assign,, bool, unsigned int, nr,\n+\t\t bool, value, int, memory_order)\n+\n #endif\n \n #endif /* _RTE_BITOPS_H_ */\n", "prefixes": [ "RFC", "v3", "5/6" ] }