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GET /api/patches/139750/?format=api
{ "id": 139750, "url": "http://patchwork.dpdk.org/api/patches/139750/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20240430202144.49899-4-andrew.boyer@amd.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240430202144.49899-4-andrew.boyer@amd.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240430202144.49899-4-andrew.boyer@amd.com", "date": "2024-04-30T20:21:38", "name": "[v2,3/9] crypto/ionic: add device commands", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "ac17a8dd03b94f41c30d359a5f0a85cf1e2f6306", "submitter": { "id": 2861, "url": "http://patchwork.dpdk.org/api/people/2861/?format=api", "name": "Andrew Boyer", "email": "Andrew.Boyer@amd.com" }, "delegate": { "id": 6690, "url": "http://patchwork.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20240430202144.49899-4-andrew.boyer@amd.com/mbox/", "series": [ { "id": 31850, "url": "http://patchwork.dpdk.org/api/series/31850/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=31850", "date": "2024-04-30T20:21:35", "name": "crypto/ionic: introduce AMD Pensando ionic crypto driver", "version": 2, "mbox": "http://patchwork.dpdk.org/series/31850/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/139750/comments/", "check": "warning", "checks": "http://patchwork.dpdk.org/api/patches/139750/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 12FB943F56;\n\tTue, 30 Apr 2024 22:22:24 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 00DFF402E2;\n\tTue, 30 Apr 2024 22:22:14 +0200 (CEST)", "from NAM12-BN8-obe.outbound.protection.outlook.com\n (mail-bn8nam12on2084.outbound.protection.outlook.com [40.107.237.84])\n by mails.dpdk.org (Postfix) with ESMTP id 677B5402C9\n for <dev@dpdk.org>; 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helo=SATLEXMB04.amd.com; pr=C", "From": "Andrew Boyer <andrew.boyer@amd.com>", "To": "<dev@dpdk.org>", "CC": "Andrew Boyer <andrew.boyer@amd.com>", "Subject": "[PATCH v2 3/9] crypto/ionic: add device commands", "Date": "Tue, 30 Apr 2024 13:21:38 -0700", "Message-ID": "<20240430202144.49899-4-andrew.boyer@amd.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20240430202144.49899-1-andrew.boyer@amd.com>", "References": "<20240419195310.21432-1-andrew.boyer@amd.com>\n <20240430202144.49899-1-andrew.boyer@amd.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.180.168.240]", "X-ClientProxiedBy": "SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com\n (10.181.40.145)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "SN1PEPF00026368:EE_|IA0PR12MB8208:EE_", "X-MS-Office365-Filtering-Correlation-Id": "d55205d2-02ae-40d3-9461-08dc695334bf", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;\n ARA:13230031|36860700004|1800799015|82310400014|376005;", "X-Microsoft-Antispam-Message-Info": "\n FO/pmUSpvXX8MK/Ktq6ovWfh5dwruYipc4rgJyHjFJ7FXW3JpBeodVpE1a3Q6GKH+H1Q92X0PO3zskhWwniPt23cSjbm+eiOt0DguuQrslfq7fo3xzaB/CIqzgPJzqb4ZLco7ptcBSuC6jNCtMx3XCReQZlE1/15vg7E2V3C12qVKpdYdqOfkh0gAuz+75ong4xCkXf1Myy169+0JQPe6QAc3/xlurMz72lhVldLiapVR4bWe4nox5Y4SYbYJMTV0YMmNSrTMTY7Vm5APCQoKb/3+jj6a4TIOMjvrVTeHEue5+s0pf7rrlVfCGjXi/P9OkoQiyyWdyk9LqXLGqMziPhSAE2ZYF9ykaHc5qj0qne68/tgiF8JDGCPQU6mZzsfqYFXkU4uKsC0wIxWXPwZqpewNpx4i7KCeEKyJfMOnPG2vASapz7Y7kW8D9joCyqW5O1DaGJPd2F71MIYNFb9Kc3Ss+xuTGjQkmDojHbJ2pXtMxtdJFs/Q8vhy8d/olTTQNRfiS2L8aRk7MqJuHd51sKFqwvlsiWFkVEESuu//0FRvVVQIz//0q8qL9dVKGvzhT3yBOkD6JFds+R8qrmXSuJH91UgRCpuv9nHJQULyNQhEuYo8ffYXakGaC8BzSqXvUHGnC30s2p8FHZ3u11CtkBncGSYOELdBcz0uvSikU1MaCMpUuhd068kmv8ihJff2bAD9FJZeMWLZi7zJ0LbFJqlm12/8fJDtZLgHXO5Me3KW39HbpF3b2nVdd9mC17kg39nmHx+cRy4fv7uPpQ2Q0yQM0zobF51/rZv92Tb2gGL2mYge13d1IG/EIu+vz33DocK8EdDEIKO8LmVRINwqkqgRKXQ2JDMu1h0NCuL2D+2JmtXIZkjvSBmF/mQJ1Tm9LERdI4B2wVMvmMk+eRXbpu3IN2PTeFTLXpxzXhclzBfFDlf8BB/Qk/xHjYp1VwcQRJ2Jhr3/iRC3LGwxxNljJ2SI9G+15nB3cPIuw23BV6PhoaXnpR3i6dOe2wKXkAzcBak9jWjvevKCxKiU0yfv8C6/KQGeV8lfryZk5V/B5NQaVyPN3HGTglNMk175C2U+xh3fVtv4JuW9l1z41msvnBMImg29sw7W3Xq5dUBGguHMJoFZjPoRYymK/B6g+okYJbsLh6hOMpn6z7bj1RYlv9tRB0LtYjkaMPo2LYSA30i3tUqjsfvKFY/k/6hx6ThqtT82K2GIvJtCUjqGj5dFCKljgvJnLgpxz5Tc2QT9LfTAsmPcnOqDc2VcKVmZvKPKk2ZdZLGaFxt1k+09Yr9/VNP1c7fs5FBBE2xxaLxlEzoWMT20Jf1QkhlB1YiSij4adU4OBuT8jl5T+qLJQ2ALHBiUWpP4UnM3Z5dklfJxe2piQHfu7VY0hRs6B+qXLgp", "X-Forefront-Antispam-Report": "CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:;\n IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE;\n SFS:(13230031)(36860700004)(1800799015)(82310400014)(376005); DIR:OUT;\n SFP:1101;", "X-OriginatorOrg": "amd.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "30 Apr 2024 20:22:06.3096 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n d55205d2-02ae-40d3-9461-08dc695334bf", "X-MS-Exchange-CrossTenant-Id": "3dd8961f-e488-4e60-8e11-a82d994e183d", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17];\n Helo=[SATLEXMB04.amd.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n SN1PEPF00026368.namprd02.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "IA0PR12MB8208", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "This defines the device (register-based) commands. They are used for\ndevice identification, setup, and teardown.\n\nSigned-off-by: Andrew Boyer <andrew.boyer@amd.com>\n---\n drivers/crypto/ionic/ionic_crypto.h | 24 ++\n drivers/crypto/ionic/ionic_crypto_cmds.c | 348 +++++++++++++++++++++++\n drivers/crypto/ionic/ionic_crypto_main.c | 89 +++++-\n drivers/crypto/ionic/meson.build | 1 +\n 4 files changed, 461 insertions(+), 1 deletion(-)\n create mode 100644 drivers/crypto/ionic/ionic_crypto_cmds.c", "diff": "diff --git a/drivers/crypto/ionic/ionic_crypto.h b/drivers/crypto/ionic/ionic_crypto.h\nindex 7f456b5154..a7999a0f68 100644\n--- a/drivers/crypto/ionic/ionic_crypto.h\n+++ b/drivers/crypto/ionic/ionic_crypto.h\n@@ -80,6 +80,17 @@ struct iocpt_dev_bars {\n \tuint32_t num_bars;\n };\n \n+struct iocpt_qtype_info {\n+\tuint8_t\t version;\n+\tuint8_t\t supported;\n+\tuint64_t features;\n+\tuint16_t desc_sz;\n+\tuint16_t comp_sz;\n+\tuint16_t sg_desc_sz;\n+\tuint16_t max_sg_elems;\n+\tuint16_t sg_desc_stride;\n+};\n+\n #define IOCPT_DEV_F_INITED\t\tBIT(0)\n #define IOCPT_DEV_F_UP\t\t\tBIT(1)\n #define IOCPT_DEV_F_FW_RESET\t\tBIT(2)\n@@ -89,6 +100,7 @@ struct iocpt_dev {\n \tconst char *name;\n \tchar fw_version[IOCPT_FWVERS_BUFLEN];\n \tstruct iocpt_dev_bars bars;\n+\tstruct iocpt_identity ident;\n \n \tconst struct iocpt_dev_intf *intf;\n \tvoid *bus_dev;\n@@ -108,6 +120,14 @@ struct iocpt_dev {\n \n \tuint64_t features;\n \tuint32_t hw_features;\n+\n+\tuint32_t info_sz;\n+\tstruct iocpt_lif_info *info;\n+\trte_iova_t info_pa;\n+\tconst struct rte_memzone *info_z;\n+\n+\tstruct iocpt_qtype_info qtype_info[IOCPT_QTYPE_MAX];\n+\tuint8_t qtype_ver[IOCPT_QTYPE_MAX];\n };\n \n struct iocpt_dev_intf {\n@@ -132,6 +152,10 @@ int iocpt_remove(struct rte_device *rte_dev);\n void iocpt_configure(struct iocpt_dev *dev);\n void iocpt_deinit(struct iocpt_dev *dev);\n \n+int iocpt_dev_identify(struct iocpt_dev *dev);\n+int iocpt_dev_init(struct iocpt_dev *dev, rte_iova_t info_pa);\n+void iocpt_dev_reset(struct iocpt_dev *dev);\n+\n static inline bool\n iocpt_is_embedded(void)\n {\ndiff --git a/drivers/crypto/ionic/ionic_crypto_cmds.c b/drivers/crypto/ionic/ionic_crypto_cmds.c\nnew file mode 100644\nindex 0000000000..105005539b\n--- /dev/null\n+++ b/drivers/crypto/ionic/ionic_crypto_cmds.c\n@@ -0,0 +1,348 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright 2021-2024 Advanced Micro Devices, Inc.\n+ */\n+\n+#include <stdbool.h>\n+\n+#include <rte_malloc.h>\n+#include <rte_memzone.h>\n+\n+#include \"ionic_crypto.h\"\n+\n+/* queuetype support level */\n+static const uint8_t iocpt_qtype_vers[IOCPT_QTYPE_MAX] = {\n+\t[IOCPT_QTYPE_ADMINQ] = 0, /* 0 = Base version */\n+\t[IOCPT_QTYPE_NOTIFYQ] = 0, /* 0 = Base version */\n+\t[IOCPT_QTYPE_CRYPTOQ] = 0, /* 0 = Base version */\n+};\n+\n+static const char *\n+iocpt_opcode_to_str(enum iocpt_cmd_opcode opcode)\n+{\n+\tswitch (opcode) {\n+\tcase IOCPT_CMD_NOP:\n+\t\treturn \"IOCPT_CMD_NOP\";\n+\tcase IOCPT_CMD_IDENTIFY:\n+\t\treturn \"IOCPT_CMD_IDENTIFY\";\n+\tcase IOCPT_CMD_RESET:\n+\t\treturn \"IOCPT_CMD_RESET\";\n+\tcase IOCPT_CMD_LIF_IDENTIFY:\n+\t\treturn \"IOCPT_CMD_LIF_IDENTIFY\";\n+\tcase IOCPT_CMD_LIF_INIT:\n+\t\treturn \"IOCPT_CMD_LIF_INIT\";\n+\tcase IOCPT_CMD_LIF_RESET:\n+\t\treturn \"IOCPT_CMD_LIF_RESET\";\n+\tcase IOCPT_CMD_LIF_GETATTR:\n+\t\treturn \"IOCPT_CMD_LIF_GETATTR\";\n+\tcase IOCPT_CMD_LIF_SETATTR:\n+\t\treturn \"IOCPT_CMD_LIF_SETATTR\";\n+\tcase IOCPT_CMD_Q_IDENTIFY:\n+\t\treturn \"IOCPT_CMD_Q_IDENTIFY\";\n+\tcase IOCPT_CMD_Q_INIT:\n+\t\treturn \"IOCPT_CMD_Q_INIT\";\n+\tcase IOCPT_CMD_Q_CONTROL:\n+\t\treturn \"IOCPT_CMD_Q_CONTROL\";\n+\tcase IOCPT_CMD_SESS_CONTROL:\n+\t\treturn \"IOCPT_CMD_SESS_CONTROL\";\n+\tdefault:\n+\t\treturn \"DEVCMD_UNKNOWN\";\n+\t}\n+}\n+\n+/* Dev_cmd Interface */\n+\n+static void\n+iocpt_dev_cmd_go(struct iocpt_dev *dev, union iocpt_dev_cmd *cmd)\n+{\n+\tuint32_t cmd_size = RTE_DIM(cmd->words);\n+\tuint32_t i;\n+\n+\tIOCPT_PRINT(DEBUG, \"Sending %s (%d) via dev_cmd\",\n+\t\tiocpt_opcode_to_str(cmd->cmd.opcode), cmd->cmd.opcode);\n+\n+\tfor (i = 0; i < cmd_size; i++)\n+\t\tiowrite32(cmd->words[i], &dev->dev_cmd->cmd.words[i]);\n+\n+\tiowrite32(0, &dev->dev_cmd->done);\n+\tiowrite32(1, &dev->dev_cmd->doorbell);\n+}\n+\n+static int\n+iocpt_dev_cmd_wait(struct iocpt_dev *dev, unsigned long max_wait)\n+{\n+\tunsigned long step_usec = IONIC_DEVCMD_CHECK_PERIOD_US;\n+\tunsigned long max_wait_usec = max_wait * 1000000L;\n+\tunsigned long elapsed_usec = 0;\n+\tint done;\n+\n+\t/* Wait for dev cmd to complete.. but no more than max_wait sec */\n+\n+\tdo {\n+\t\tdone = ioread32(&dev->dev_cmd->done) & IONIC_DEV_CMD_DONE;\n+\t\tif (done != 0) {\n+\t\t\tIOCPT_PRINT(DEBUG, \"DEVCMD %d done took %lu usecs\",\n+\t\t\t\tioread8(&dev->dev_cmd->cmd.cmd.opcode),\n+\t\t\t\telapsed_usec);\n+\t\t\treturn 0;\n+\t\t}\n+\n+\t\trte_delay_us_block(step_usec);\n+\n+\t\telapsed_usec += step_usec;\n+\t} while (elapsed_usec < max_wait_usec);\n+\n+\tIOCPT_PRINT(ERR, \"DEVCMD %d timeout after %lu usecs\",\n+\t\tioread8(&dev->dev_cmd->cmd.cmd.opcode), elapsed_usec);\n+\n+\treturn -ETIMEDOUT;\n+}\n+\n+static int\n+iocpt_dev_cmd_wait_check(struct iocpt_dev *dev, unsigned long max_wait)\n+{\n+\tuint8_t status;\n+\tint err;\n+\n+\terr = iocpt_dev_cmd_wait(dev, max_wait);\n+\tif (err == 0) {\n+\t\tstatus = ioread8(&dev->dev_cmd->comp.comp.status);\n+\t\tif (status == IOCPT_RC_EAGAIN)\n+\t\t\terr = -EAGAIN;\n+\t\telse if (status != 0)\n+\t\t\terr = -EIO;\n+\t}\n+\n+\tIOCPT_PRINT(DEBUG, \"dev_cmd returned %d\", err);\n+\treturn err;\n+}\n+\n+/* Dev_cmds */\n+\n+static void\n+iocpt_dev_cmd_reset(struct iocpt_dev *dev)\n+{\n+\tunion iocpt_dev_cmd cmd = {\n+\t\t.reset.opcode = IOCPT_CMD_RESET,\n+\t};\n+\n+\tiocpt_dev_cmd_go(dev, &cmd);\n+}\n+\n+static void\n+iocpt_dev_cmd_lif_identify(struct iocpt_dev *dev, uint8_t ver)\n+{\n+\tunion iocpt_dev_cmd cmd = {\n+\t\t.lif_identify.opcode = IOCPT_CMD_LIF_IDENTIFY,\n+\t\t.lif_identify.type = IOCPT_LIF_TYPE_DEFAULT,\n+\t\t.lif_identify.ver = ver,\n+\t};\n+\n+\tiocpt_dev_cmd_go(dev, &cmd);\n+}\n+\n+static void\n+iocpt_dev_cmd_lif_init(struct iocpt_dev *dev, rte_iova_t info_pa)\n+{\n+\tunion iocpt_dev_cmd cmd = {\n+\t\t.lif_init.opcode = IOCPT_CMD_LIF_INIT,\n+\t\t.lif_init.type = IOCPT_LIF_TYPE_DEFAULT,\n+\t\t.lif_init.info_pa = info_pa,\n+\t};\n+\n+\tiocpt_dev_cmd_go(dev, &cmd);\n+}\n+\n+static void\n+iocpt_dev_cmd_lif_reset(struct iocpt_dev *dev)\n+{\n+\tunion iocpt_dev_cmd cmd = {\n+\t\t.lif_reset.opcode = IOCPT_CMD_LIF_RESET,\n+\t};\n+\n+\tiocpt_dev_cmd_go(dev, &cmd);\n+}\n+\n+static void\n+iocpt_dev_cmd_queue_identify(struct iocpt_dev *dev,\n+\t\tuint8_t qtype, uint8_t qver)\n+{\n+\tunion iocpt_dev_cmd cmd = {\n+\t\t.q_identify.opcode = IOCPT_CMD_Q_IDENTIFY,\n+\t\t.q_identify.type = qtype,\n+\t\t.q_identify.ver = qver,\n+\t};\n+\n+\tiocpt_dev_cmd_go(dev, &cmd);\n+}\n+\n+/* Dev_cmd consumers */\n+\n+static void\n+iocpt_queue_identify(struct iocpt_dev *dev)\n+{\n+\tunion iocpt_q_identity *q_ident = &dev->ident.q;\n+\tuint32_t q_words = RTE_DIM(q_ident->words);\n+\tuint32_t cmd_words = RTE_DIM(dev->dev_cmd->data);\n+\tuint32_t i, nwords, qtype;\n+\tint err;\n+\n+\tfor (qtype = 0; qtype < RTE_DIM(iocpt_qtype_vers); qtype++) {\n+\t\tstruct iocpt_qtype_info *qti = &dev->qtype_info[qtype];\n+\n+\t\t/* Filter out the types this driver knows about */\n+\t\tswitch (qtype) {\n+\t\tcase IOCPT_QTYPE_ADMINQ:\n+\t\tcase IOCPT_QTYPE_NOTIFYQ:\n+\t\tcase IOCPT_QTYPE_CRYPTOQ:\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\tmemset(qti, 0, sizeof(*qti));\n+\n+\t\tif (iocpt_is_embedded()) {\n+\t\t\t/* When embedded, FW will always match the driver */\n+\t\t\tqti->version = iocpt_qtype_vers[qtype];\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\t/* On the host, query the FW for info */\n+\t\tiocpt_dev_cmd_queue_identify(dev,\n+\t\t\tqtype, iocpt_qtype_vers[qtype]);\n+\t\terr = iocpt_dev_cmd_wait_check(dev, IONIC_DEVCMD_TIMEOUT);\n+\t\tif (err == -EINVAL) {\n+\t\t\tIOCPT_PRINT(ERR, \"qtype %d not supported\", qtype);\n+\t\t\tcontinue;\n+\t\t} else if (err == -EIO) {\n+\t\t\tIOCPT_PRINT(ERR, \"q_ident failed, older FW\");\n+\t\t\treturn;\n+\t\t} else if (err != 0) {\n+\t\t\tIOCPT_PRINT(ERR, \"q_ident failed, qtype %d: %d\",\n+\t\t\t\tqtype, err);\n+\t\t\treturn;\n+\t\t}\n+\n+\t\tnwords = RTE_MIN(q_words, cmd_words);\n+\t\tfor (i = 0; i < nwords; i++)\n+\t\t\tq_ident->words[i] = ioread32(&dev->dev_cmd->data[i]);\n+\n+\t\tqti->version = q_ident->version;\n+\t\tqti->supported = q_ident->supported;\n+\t\tqti->features = rte_le_to_cpu_64(q_ident->features);\n+\t\tqti->desc_sz = rte_le_to_cpu_16(q_ident->desc_sz);\n+\t\tqti->comp_sz = rte_le_to_cpu_16(q_ident->comp_sz);\n+\t\tqti->sg_desc_sz = rte_le_to_cpu_16(q_ident->sg_desc_sz);\n+\t\tqti->max_sg_elems = rte_le_to_cpu_16(q_ident->max_sg_elems);\n+\t\tqti->sg_desc_stride =\n+\t\t\trte_le_to_cpu_16(q_ident->sg_desc_stride);\n+\n+\t\tIOCPT_PRINT(DEBUG, \" qtype[%d].version = %d\",\n+\t\t\tqtype, qti->version);\n+\t\tIOCPT_PRINT(DEBUG, \" qtype[%d].supported = %#x\",\n+\t\t\tqtype, qti->supported);\n+\t\tIOCPT_PRINT(DEBUG, \" qtype[%d].features = %#jx\",\n+\t\t\tqtype, qti->features);\n+\t\tIOCPT_PRINT(DEBUG, \" qtype[%d].desc_sz = %d\",\n+\t\t\tqtype, qti->desc_sz);\n+\t\tIOCPT_PRINT(DEBUG, \" qtype[%d].comp_sz = %d\",\n+\t\t\tqtype, qti->comp_sz);\n+\t\tIOCPT_PRINT(DEBUG, \" qtype[%d].sg_desc_sz = %d\",\n+\t\t\tqtype, qti->sg_desc_sz);\n+\t\tIOCPT_PRINT(DEBUG, \" qtype[%d].max_sg_elems = %d\",\n+\t\t\tqtype, qti->max_sg_elems);\n+\t\tIOCPT_PRINT(DEBUG, \" qtype[%d].sg_desc_stride = %d\",\n+\t\t\tqtype, qti->sg_desc_stride);\n+\t}\n+}\n+\n+int\n+iocpt_dev_identify(struct iocpt_dev *dev)\n+{\n+\tunion iocpt_lif_identity *ident = &dev->ident.lif;\n+\tunion iocpt_lif_config *cfg = &ident->config;\n+\tuint64_t features;\n+\tuint32_t cmd_size = RTE_DIM(dev->dev_cmd->data);\n+\tuint32_t dev_size = RTE_DIM(ident->words);\n+\tuint32_t i, nwords;\n+\tint err;\n+\n+\tmemset(ident, 0, sizeof(*ident));\n+\n+\tiocpt_dev_cmd_lif_identify(dev, IOCPT_IDENTITY_VERSION_1);\n+\terr = iocpt_dev_cmd_wait_check(dev, IONIC_DEVCMD_TIMEOUT);\n+\tif (err != 0)\n+\t\treturn err;\n+\n+\tnwords = RTE_MIN(dev_size, cmd_size);\n+\tfor (i = 0; i < nwords; i++)\n+\t\tident->words[i] = ioread32(&dev->dev_cmd->data[i]);\n+\n+\tdev->max_qps =\n+\t\trte_le_to_cpu_32(cfg->queue_count[IOCPT_QTYPE_CRYPTOQ]);\n+\tdev->max_sessions =\n+\t\trte_le_to_cpu_32(ident->max_nb_sessions);\n+\n+\tfeatures = rte_le_to_cpu_64(ident->features);\n+\tdev->features = RTE_CRYPTODEV_FF_HW_ACCELERATED;\n+\tif (features & IOCPT_HW_SYM)\n+\t\tdev->features |= RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO;\n+\tif (features & IOCPT_HW_ASYM)\n+\t\tdev->features |= RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO;\n+\tif (features & IOCPT_HW_CHAIN)\n+\t\tdev->features |= RTE_CRYPTODEV_FF_SYM_OPERATION_CHAINING;\n+\tif (features & IOCPT_HW_IP)\n+\t\tdev->features |= RTE_CRYPTODEV_FF_IN_PLACE_SGL;\n+\tif (features & IOCPT_HW_OOP) {\n+\t\tdev->features |= RTE_CRYPTODEV_FF_OOP_SGL_IN_SGL_OUT;\n+\t\tdev->features |= RTE_CRYPTODEV_FF_OOP_SGL_IN_LB_OUT;\n+\t\tdev->features |= RTE_CRYPTODEV_FF_OOP_LB_IN_LB_OUT;\n+\t\tdev->features |= RTE_CRYPTODEV_FF_OOP_LB_IN_SGL_OUT;\n+\t}\n+\n+\tIOCPT_PRINT(INFO, \"crypto.features %#jx\",\n+\t\trte_le_to_cpu_64(ident->features));\n+\tIOCPT_PRINT(INFO, \"crypto.features_active %#jx\",\n+\t\trte_le_to_cpu_64(cfg->features));\n+\tIOCPT_PRINT(INFO, \"crypto.queue_count[IOCPT_QTYPE_ADMINQ] %#x\",\n+\t\trte_le_to_cpu_32(cfg->queue_count[IOCPT_QTYPE_ADMINQ]));\n+\tIOCPT_PRINT(INFO, \"crypto.queue_count[IOCPT_QTYPE_NOTIFYQ] %#x\",\n+\t\trte_le_to_cpu_32(cfg->queue_count[IOCPT_QTYPE_NOTIFYQ]));\n+\tIOCPT_PRINT(INFO, \"crypto.queue_count[IOCPT_QTYPE_CRYPTOQ] %#x\",\n+\t\trte_le_to_cpu_32(cfg->queue_count[IOCPT_QTYPE_CRYPTOQ]));\n+\tIOCPT_PRINT(INFO, \"crypto.max_sessions %u\",\n+\t\trte_le_to_cpu_32(ident->max_nb_sessions));\n+\n+\tiocpt_queue_identify(dev);\n+\n+\treturn 0;\n+}\n+\n+int\n+iocpt_dev_init(struct iocpt_dev *dev, rte_iova_t info_pa)\n+{\n+\tuint32_t retries = 5;\n+\tint err;\n+\n+retry_lif_init:\n+\tiocpt_dev_cmd_lif_init(dev, info_pa);\n+\n+\terr = iocpt_dev_cmd_wait_check(dev, IONIC_DEVCMD_TIMEOUT);\n+\tif (err == -EAGAIN && retries > 0) {\n+\t\tretries--;\n+\t\trte_delay_us_block(IONIC_DEVCMD_RETRY_WAIT_US);\n+\t\tgoto retry_lif_init;\n+\t}\n+\n+\treturn err;\n+}\n+\n+void\n+iocpt_dev_reset(struct iocpt_dev *dev)\n+{\n+\tiocpt_dev_cmd_lif_reset(dev);\n+\t(void)iocpt_dev_cmd_wait_check(dev, IONIC_DEVCMD_TIMEOUT);\n+\n+\tiocpt_dev_cmd_reset(dev);\n+\t(void)iocpt_dev_cmd_wait_check(dev, IONIC_DEVCMD_TIMEOUT);\n+}\ndiff --git a/drivers/crypto/ionic/ionic_crypto_main.c b/drivers/crypto/ionic/ionic_crypto_main.c\nindex 64b7cae03c..4f782f3fe4 100644\n--- a/drivers/crypto/ionic/ionic_crypto_main.c\n+++ b/drivers/crypto/ionic/ionic_crypto_main.c\n@@ -10,9 +10,64 @@\n \n #include \"ionic_crypto.h\"\n \n+static const struct rte_memzone *\n+iocpt_dma_zone_reserve(const char *type_name, uint16_t qid, size_t size,\n+\t\t\tunsigned int align, int socket_id)\n+{\n+\tchar zone_name[RTE_MEMZONE_NAMESIZE];\n+\tconst struct rte_memzone *mz;\n+\tint err;\n+\n+\terr = snprintf(zone_name, sizeof(zone_name),\n+\t\t\t\"iocpt_%s_%u\", type_name, qid);\n+\tif (err >= RTE_MEMZONE_NAMESIZE) {\n+\t\tIOCPT_PRINT(ERR, \"Name %s too long\", type_name);\n+\t\treturn NULL;\n+\t}\n+\n+\tmz = rte_memzone_lookup(zone_name);\n+\tif (mz != NULL)\n+\t\treturn mz;\n+\n+\treturn rte_memzone_reserve_aligned(zone_name, size, socket_id,\n+\t\t\tRTE_MEMZONE_IOVA_CONTIG, align);\n+}\n+\n+static int\n+iocpt_alloc_objs(struct iocpt_dev *dev)\n+{\n+\tint err;\n+\n+\tIOCPT_PRINT(DEBUG, \"Crypto: %s\", dev->name);\n+\n+\tdev->info_sz = RTE_ALIGN(sizeof(*dev->info), rte_mem_page_size());\n+\tdev->info_z = iocpt_dma_zone_reserve(\"info\", 0, dev->info_sz,\n+\t\t\t\t\tIONIC_ALIGN, dev->socket_id);\n+\tif (dev->info_z == NULL) {\n+\t\tIOCPT_PRINT(ERR, \"Cannot allocate dev info memory\");\n+\t\terr = -ENOMEM;\n+\t\tgoto err_out;\n+\t}\n+\n+\tdev->info = dev->info_z->addr;\n+\tdev->info_pa = dev->info_z->iova;\n+\n+\treturn 0;\n+\n+err_out:\n+\treturn err;\n+}\n+\n static int\n iocpt_init(struct iocpt_dev *dev)\n {\n+\tint err;\n+\n+\t/* Uses dev_cmds */\n+\terr = iocpt_dev_init(dev, dev->info_pa);\n+\tif (err != 0)\n+\t\treturn err;\n+\n \tdev->state |= IOCPT_DEV_F_INITED;\n \n \treturn 0;\n@@ -35,6 +90,19 @@ iocpt_deinit(struct iocpt_dev *dev)\n \tdev->state &= ~IOCPT_DEV_F_INITED;\n }\n \n+static void\n+iocpt_free_objs(struct iocpt_dev *dev)\n+{\n+\tIOCPT_PRINT_CALL();\n+\n+\tif (dev->info != NULL) {\n+\t\trte_memzone_free(dev->info_z);\n+\t\tdev->info_z = NULL;\n+\t\tdev->info = NULL;\n+\t\tdev->info_pa = 0;\n+\t}\n+}\n+\n static int\n iocpt_devargs(struct rte_devargs *devargs, struct iocpt_dev *dev)\n {\n@@ -125,14 +193,29 @@ iocpt_probe(void *bus_dev, struct rte_device *rte_dev,\n \tdev->fw_version[IOCPT_FWVERS_BUFLEN - 1] = '\\0';\n \tIOCPT_PRINT(DEBUG, \"%s firmware: %s\", dev->name, dev->fw_version);\n \n+\terr = iocpt_dev_identify(dev);\n+\tif (err != 0) {\n+\t\tIOCPT_PRINT(ERR, \"Cannot identify device: %d, aborting\",\n+\t\t\terr);\n+\t\tgoto err_destroy_crypto_dev;\n+\t}\n+\n+\terr = iocpt_alloc_objs(dev);\n+\tif (err != 0) {\n+\t\tIOCPT_PRINT(ERR, \"Cannot alloc device objects: %d\", err);\n+\t\tgoto err_destroy_crypto_dev;\n+\t}\n+\n \terr = iocpt_init(dev);\n \tif (err != 0) {\n \t\tIOCPT_PRINT(ERR, \"Cannot init device: %d, aborting\", err);\n-\t\tgoto err_destroy_crypto_dev;\n+\t\tgoto err_free_objs;\n \t}\n \n \treturn 0;\n \n+err_free_objs:\n+\tiocpt_free_objs(dev);\n err_destroy_crypto_dev:\n \trte_cryptodev_pmd_destroy(cdev);\n err:\n@@ -155,6 +238,10 @@ iocpt_remove(struct rte_device *rte_dev)\n \n \tiocpt_deinit(dev);\n \n+\tiocpt_dev_reset(dev);\n+\n+\tiocpt_free_objs(dev);\n+\n \trte_cryptodev_pmd_destroy(cdev);\n \n \treturn 0;\ndiff --git a/drivers/crypto/ionic/meson.build b/drivers/crypto/ionic/meson.build\nindex 4114e13e53..a6e0a1d415 100644\n--- a/drivers/crypto/ionic/meson.build\n+++ b/drivers/crypto/ionic/meson.build\n@@ -5,6 +5,7 @@ deps += ['bus_vdev']\n deps += ['common_ionic']\n \n sources = files(\n+ 'ionic_crypto_cmds.c',\n 'ionic_crypto_main.c',\n 'ionic_crypto_vdev.c',\n )\n", "prefixes": [ "v2", "3/9" ] }