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GET /api/patches/139778/?format=api
{ "id": 139778, "url": "http://patchwork.dpdk.org/api/patches/139778/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20240501182254.1194146-3-abdullah.sevincer@intel.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240501182254.1194146-3-abdullah.sevincer@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240501182254.1194146-3-abdullah.sevincer@intel.com", "date": "2024-05-01T18:22:53", "name": "[v2,2/3] event/dlb2: add support for dynamic HL entries", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "3018ec0a00b9933a9a599a18ca0a9984d7d800ef", "submitter": { "id": 2843, "url": "http://patchwork.dpdk.org/api/people/2843/?format=api", "name": "Sevincer, Abdullah", "email": "abdullah.sevincer@intel.com" }, "delegate": { "id": 310, "url": "http://patchwork.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20240501182254.1194146-3-abdullah.sevincer@intel.com/mbox/", "series": [ { "id": 31859, "url": "http://patchwork.dpdk.org/api/series/31859/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=31859", "date": "2024-05-01T18:22:51", "name": "DLB2 Enhancements", "version": 2, "mbox": "http://patchwork.dpdk.org/series/31859/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/139778/comments/", "check": "pending", "checks": "http://patchwork.dpdk.org/api/patches/139778/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id D601C43F61;\n\tWed, 1 May 2024 20:23:13 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id CADF4402DA;\n\tWed, 1 May 2024 20:23:02 +0200 (CEST)", "from mgamail.intel.com (mgamail.intel.com [192.198.163.7])\n by mails.dpdk.org (Postfix) with ESMTP id D685F402A7\n for <dev@dpdk.org>; Wed, 1 May 2024 20:22:59 +0200 (CEST)", "from orviesa007.jf.intel.com ([10.64.159.147])\n by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 01 May 2024 11:22:59 -0700", "from txanpdk02.an.intel.com ([10.123.117.76])\n by orviesa007.jf.intel.com with ESMTP; 01 May 2024 11:22:59 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1714587780; x=1746123780;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=DADaiVCopX5xjaGnUuCJKk4JisrgUxbjf9xioeymDRQ=;\n b=A9UIu+TY8NLIcwvFdiVbWBJ09+xleed0cjl+yNaM5i3jC0MyrjXYJeIe\n nAhoyF6I9Kl6zMcMNkYCrDJplCeVhOnGAHlCpR8IBdzUiPN1qFoojjg+9\n hXE++pIsyvb2B5r//HQxbbn/QlvjzOn5trFMGI++fSkPRlK1dSvMK/HUX\n svOrwAfR62hYqqQSUj/xYAlFQfJJRp5bdX8ujNmrbzy5aqj97l6tjjfQt\n D4nj2FxNCDyJrD6oJxm8lXc3AJUyaxXvwYf9uuQMHn4msJhYW+uc+FUwq\n dV/2MfQpxOBFSpSb24zFneYibYPLCbvZCVNlG6LZ7y5ZS0ZLElIymaUP7 w==;", "X-CSE-ConnectionGUID": [ "hYJSEER1Syy9RgLrpJvO4Q==", "0oeTm7PqSDqTm9yhhF9cPQ==" ], "X-CSE-MsgGUID": [ "6h3dH92USgGJ+EDTvT7fBg==", "5+Iv3JjcRCGnV4Zar4TJ0Q==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6600,9927,11061\"; a=\"35718563\"", "E=Sophos;i=\"6.07,246,1708416000\"; d=\"scan'208\";a=\"35718563\"", "E=Sophos;i=\"6.07,246,1708416000\"; d=\"scan'208\";a=\"27357908\"" ], "X-ExtLoop1": "1", "From": "Abdullah Sevincer <abdullah.sevincer@intel.com>", "To": "dev@dpdk.org", "Cc": "jerinj@marvell.com, mike.ximing.chen@intel.com,\n tirthendu.sarkar@intel.com,\n pravin.pathak@intel.com, shivani.doneria@intel.com,\n Abdullah Sevincer <abdullah.sevincer@intel.com>", "Subject": "[PATCH v2 2/3] event/dlb2: add support for dynamic HL entries", "Date": "Wed, 1 May 2024 13:22:53 -0500", "Message-Id": "<20240501182254.1194146-3-abdullah.sevincer@intel.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20240501182254.1194146-1-abdullah.sevincer@intel.com>", "References": "<20240501182254.1194146-1-abdullah.sevincer@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "In DLB 2.5, hardware assist is available, complementing the Delayed\ntoken POP software implementation. When it is enabled, the feature\nworks as follows:\n\nIt stops CQ scheduling when the inflight limit associated with the CQ\nis reached. So the feature is activated only if the core is\ncongested. If the core can handle multiple atomic flows, DLB will not\ntry to switch them. This is an improvement over SW implementation\nwhich always switches the flows.\n\nThe feature will resume CQ scheduling when the number of pending\ncompletions fall below a configured threshold.\n\nDLB has 64 LDB ports and 2048 HL entries. If all LDB ports are used,\npossible HL entries per LDB port equals 2048 / 64 = 32. So, the\nmaximum CQ depth possible is 16, if all 64 LB ports are needed in a\nhigh-performance setting.\n\nIn case all CQs are configured to have HL = 2* CQ Depth as a\nperformance option, then the calculation of HL at the time of domain\ncreation will be based on maximum possible dequeue depth. This could\nresult in allocating too many HL entries to the domain as DLB only\nhas limited number of HL entries to be allocated. Hence, it is best\nto allow application to specify HL entries as a command line argument\nand override default allocation. A summary of usage is listed below:\n\nWhen 'use_default_hl = 1', Per port HL is set to\nDLB2_FIXED_CQ_HL_SIZE (32) and command line parameter\nalloc_hl_entries is ignored.\n\nWhen 'use_default_hl = 0', Per LDB port HL = 2 * CQ depth and per\nport HL is set to 2 * DLB2_FIXED_CQ_HL_SIZE.\n\nUser should calculate needed HL entries based on CQ depths the\napplication will use and specify it as command line parameter\n'alloc_hl_entries'. This will be used to allocate HL entries.\nHence, alloc_hl_entries = (Sum of all LDB ports CQ depths * 2).\n\nIf alloc_hl_entries is not specified, then Total HL entries for the\nvdev = num_ldb_ports * 64.\n\nSigned-off-by: Abdullah Sevincer <abdullah.sevincer@intel.com>\n---\n drivers/event/dlb2/dlb2.c | 124 ++++++++++++++++++++++++++++--\n drivers/event/dlb2/dlb2_priv.h | 10 ++-\n drivers/event/dlb2/pf/dlb2_pf.c | 7 +-\n drivers/event/dlb2/rte_pmd_dlb2.h | 1 +\n 4 files changed, 130 insertions(+), 12 deletions(-)", "diff": "diff --git a/drivers/event/dlb2/dlb2.c b/drivers/event/dlb2/dlb2.c\nindex f0faf054b1..d1a3c11a45 100644\n--- a/drivers/event/dlb2/dlb2.c\n+++ b/drivers/event/dlb2/dlb2.c\n@@ -180,10 +180,7 @@ dlb2_hw_query_resources(struct dlb2_eventdev *dlb2)\n \t * The capabilities (CAPs) were set at compile time.\n \t */\n \n-\tif (dlb2->max_cq_depth != DLB2_DEFAULT_CQ_DEPTH)\n-\t\tnum_ldb_ports = DLB2_MAX_HL_ENTRIES / dlb2->max_cq_depth;\n-\telse\n-\t\tnum_ldb_ports = dlb2->hw_rsrc_query_results.num_ldb_ports;\n+\tnum_ldb_ports = dlb2->hw_rsrc_query_results.num_ldb_ports;\n \n \tevdev_dlb2_default_info.max_event_queues =\n \t\tdlb2->hw_rsrc_query_results.num_ldb_queues;\n@@ -631,6 +628,52 @@ set_enable_cq_weight(const char *key __rte_unused,\n \treturn 0;\n }\n \n+static int set_hl_override(const char *key __rte_unused,\n+\t\tconst char *value,\n+\t\tvoid *opaque)\n+{\n+\tbool *default_hl = opaque;\n+\n+\tif (value == NULL || opaque == NULL) {\n+\t\tDLB2_LOG_ERR(\"NULL pointer\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif ((*value == 'n') || (*value == 'N') || (*value == '0'))\n+\t\t*default_hl = false;\n+\telse\n+\t\t*default_hl = true;\n+\n+\treturn 0;\n+}\n+\n+static int set_hl_entries(const char *key __rte_unused,\n+\t\tconst char *value,\n+\t\tvoid *opaque)\n+{\n+\tint hl_entries = 0;\n+\tint ret;\n+\n+\tif (value == NULL || opaque == NULL) {\n+\t\tDLB2_LOG_ERR(\"NULL pointer\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tret = dlb2_string_to_int(&hl_entries, value);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\tif ((uint32_t)hl_entries > DLB2_MAX_HL_ENTRIES) {\n+\t\tDLB2_LOG_ERR(\n+\t\t \"alloc_hl_entries %u out of range, must be in [1 - %d]\\n\",\n+\t\t hl_entries, DLB2_MAX_HL_ENTRIES);\n+\t\treturn -EINVAL;\n+\t}\n+\t*(uint32_t *)opaque = hl_entries;\n+\n+\treturn 0;\n+}\n+\n static int\n set_qid_depth_thresh(const char *key __rte_unused,\n \t\t const char *value,\n@@ -828,8 +871,15 @@ dlb2_hw_create_sched_domain(struct dlb2_eventdev *dlb2,\n \t\tDLB2_NUM_ATOMIC_INFLIGHTS_PER_QUEUE *\n \t\tcfg->num_ldb_queues;\n \n-\tcfg->num_hist_list_entries = resources_asked->num_ldb_ports *\n-\t\tevdev_dlb2_default_info.max_event_port_dequeue_depth;\n+\t/* If hl_entries is non-zero then user specified command line option.\n+\t * Else compute using default_port_hl that has been set earlier based\n+\t * on use_default_hl option\n+\t */\n+\tif (dlb2->hl_entries)\n+\t\tcfg->num_hist_list_entries = dlb2->hl_entries;\n+\telse\n+\t\tcfg->num_hist_list_entries =\n+\t\t resources_asked->num_ldb_ports * dlb2->default_port_hl;\n \n \tif (device_version == DLB2_HW_V2_5) {\n \t\tDLB2_LOG_DBG(\"sched domain create - ldb_qs=%d, ldb_ports=%d, dir_ports=%d, atomic_inflights=%d, hist_list_entries=%d, credits=%d\\n\",\n@@ -1041,7 +1091,7 @@ dlb2_eventdev_port_default_conf_get(struct rte_eventdev *dev,\n \tstruct dlb2_eventdev *dlb2 = dlb2_pmd_priv(dev);\n \n \tport_conf->new_event_threshold = dlb2->new_event_limit;\n-\tport_conf->dequeue_depth = 32;\n+\tport_conf->dequeue_depth = dlb2->default_port_hl / 2;\n \tport_conf->enqueue_depth = DLB2_MAX_ENQUEUE_DEPTH;\n \tport_conf->event_port_cfg = 0;\n }\n@@ -1560,9 +1610,16 @@ dlb2_hw_create_ldb_port(struct dlb2_eventdev *dlb2,\n \tif (dlb2->version == DLB2_HW_V2_5 && qm_port->enable_inflight_ctrl) {\n \t\tcfg.enable_inflight_ctrl = 1;\n \t\tcfg.inflight_threshold = qm_port->inflight_threshold;\n+\t\tif (!qm_port->hist_list)\n+\t\t\tqm_port->hist_list = cfg.cq_depth;\n \t}\n \n-\tcfg.cq_history_list_size = cfg.cq_depth;\n+\tif (qm_port->hist_list)\n+\t\tcfg.cq_history_list_size = qm_port->hist_list;\n+\telse if (dlb2->default_port_hl == DLB2_FIXED_CQ_HL_SIZE)\n+\t\tcfg.cq_history_list_size = DLB2_FIXED_CQ_HL_SIZE;\n+\telse\n+\t\tcfg.cq_history_list_size = cfg.cq_depth * 2;\n \n \tcfg.cos_id = ev_port->cos_id;\n \tcfg.cos_strict = 0;/* best effots */\n@@ -4366,6 +4423,13 @@ dlb2_set_port_param(struct dlb2_eventdev *dlb2,\n \t\t\t\treturn -EINVAL;\n \t\t\t}\n \t\t\tbreak;\n+\t\tcase DLB2_SET_PORT_HL:\n+\t\t\tif (dlb2->ev_ports[port_id].setup_done) {\n+\t\t\t\tDLB2_LOG_ERR(\"DLB2_SET_PORT_HL must be called before setting up port\\n\");\n+\t\t\t\treturn -EINVAL;\n+\t\t\t}\n+\t\t\tport->hist_list = port_param->port_hl;\n+\t\t\tbreak;\n \t\tdefault:\n \t\t\tDLB2_LOG_ERR(\"dlb2: Unsupported flag\\n\");\n \t\t\treturn -EINVAL;\n@@ -4684,6 +4748,28 @@ dlb2_primary_eventdev_probe(struct rte_eventdev *dev,\n \t\treturn err;\n \t}\n \n+\tif (dlb2_args->use_default_hl) {\n+\t\tdlb2->default_port_hl = DLB2_FIXED_CQ_HL_SIZE;\n+\t\tif (dlb2_args->alloc_hl_entries)\n+\t\t\tDLB2_LOG_ERR(\": Ignoring 'alloc_hl_entries' and using \"\n+\t\t\t\t \"default history list sizes for eventdev:\"\n+\t\t\t\t \" %s\\n\", dev->data->name);\n+\t\tdlb2->hl_entries = 0;\n+\t} else {\n+\t\tdlb2->default_port_hl = 2 * DLB2_FIXED_CQ_HL_SIZE;\n+\n+\t\tif (dlb2_args->alloc_hl_entries >\n+\t\t dlb2->hw_rsrc_query_results.num_hist_list_entries) {\n+\t\t\tDLB2_LOG_ERR(\": Insufficient HL entries asked=%d \"\n+\t\t\t\t \"available=%d for eventdev: %s\\n\",\n+\t\t\t\t dlb2->hl_entries,\n+\t\t\t\t dlb2->hw_rsrc_query_results.num_hist_list_entries,\n+\t\t\t\t dev->data->name);\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t\tdlb2->hl_entries = dlb2_args->alloc_hl_entries;\n+\t}\n+\n \tdlb2_iface_hardware_init(&dlb2->qm_instance);\n \n \t/* configure class of service */\n@@ -4791,6 +4877,8 @@ dlb2_parse_params(const char *params,\n \t\t\t\t\t DLB2_PRODUCER_COREMASK,\n \t\t\t\t\t DLB2_DEFAULT_LDB_PORT_ALLOCATION_ARG,\n \t\t\t\t\t DLB2_ENABLE_CQ_WEIGHT_ARG,\n+\t\t\t\t\t DLB2_USE_DEFAULT_HL,\n+\t\t\t\t\t DLB2_ALLOC_HL_ENTRIES,\n \t\t\t\t\t NULL };\n \n \tif (params != NULL && params[0] != '\\0') {\n@@ -4994,6 +5082,26 @@ dlb2_parse_params(const char *params,\n \t\t\t\treturn ret;\n \t\t\t}\n \n+\t\t\tret = rte_kvargs_process(kvlist, DLB2_USE_DEFAULT_HL,\n+\t\t\t\t\t\t set_hl_override,\n+\t\t\t\t\t\t &dlb2_args->use_default_hl);\n+\t\t\tif (ret != 0) {\n+\t\t\t\tDLB2_LOG_ERR(\"%s: Error parsing use_default_hl arg\",\n+\t\t\t\t\t name);\n+\t\t\t\trte_kvargs_free(kvlist);\n+\t\t\t\treturn ret;\n+\t\t\t}\n+\n+\t\t\tret = rte_kvargs_process(kvlist, DLB2_ALLOC_HL_ENTRIES,\n+\t\t\t\t\t\t set_hl_entries,\n+\t\t\t\t\t\t &dlb2_args->alloc_hl_entries);\n+\t\t\tif (ret != 0) {\n+\t\t\t\tDLB2_LOG_ERR(\"%s: Error parsing hl_override arg\",\n+\t\t\t\t\t name);\n+\t\t\t\trte_kvargs_free(kvlist);\n+\t\t\t\treturn ret;\n+\t\t\t}\n+\n \t\t\trte_kvargs_free(kvlist);\n \t\t}\n \t}\ndiff --git a/drivers/event/dlb2/dlb2_priv.h b/drivers/event/dlb2/dlb2_priv.h\nindex d6828aa482..dc9f98e142 100644\n--- a/drivers/event/dlb2/dlb2_priv.h\n+++ b/drivers/event/dlb2/dlb2_priv.h\n@@ -52,6 +52,8 @@\n #define DLB2_PRODUCER_COREMASK \"producer_coremask\"\n #define DLB2_DEFAULT_LDB_PORT_ALLOCATION_ARG \"default_port_allocation\"\n #define DLB2_ENABLE_CQ_WEIGHT_ARG \"enable_cq_weight\"\n+#define DLB2_USE_DEFAULT_HL \"use_default_hl\"\n+#define DLB2_ALLOC_HL_ENTRIES \"alloc_hl_entries\"\n \n /* Begin HW related defines and structs */\n \n@@ -101,7 +103,8 @@\n */\n #define DLB2_MAX_HL_ENTRIES 2048\n #define DLB2_MIN_CQ_DEPTH 1\n-#define DLB2_DEFAULT_CQ_DEPTH 32\n+#define DLB2_DEFAULT_CQ_DEPTH 32 /* Can be overridden using max_cq_depth command line parameter */\n+#define DLB2_FIXED_CQ_HL_SIZE 32 /* Used when ENABLE_FIXED_HL_SIZE is true */\n #define DLB2_MIN_HARDWARE_CQ_DEPTH 8\n #define DLB2_NUM_HIST_LIST_ENTRIES_PER_LDB_PORT \\\n \tDLB2_DEFAULT_CQ_DEPTH\n@@ -391,6 +394,7 @@ struct dlb2_port {\n \tbool is_producer; /* True if port is of type producer */\n \tuint16_t inflight_threshold; /* DLB2.5 HW inflight threshold */\n \tbool enable_inflight_ctrl; /*DLB2.5 enable HW inflight control */\n+\tuint16_t hist_list; /* Port history list */\n };\n \n /* Per-process per-port mmio and memory pointers */\n@@ -640,6 +644,8 @@ struct dlb2_eventdev {\n \tuint32_t cos_bw[DLB2_COS_NUM_VALS]; /* bandwidth per cos domain */\n \tuint8_t max_cos_port; /* Max LDB port from any cos */\n \tbool enable_cq_weight;\n+\tuint16_t hl_entries; /* Num HL entires to allocate for the domain */\n+\tint default_port_hl; /* Fixed or dynamic (2*CQ Depth) HL assignment */\n };\n \n /* used for collecting and passing around the dev args */\n@@ -678,6 +684,8 @@ struct dlb2_devargs {\n \tconst char *producer_coremask;\n \tbool default_ldb_port_allocation;\n \tbool enable_cq_weight;\n+\tbool use_default_hl;\n+\tuint32_t alloc_hl_entries;\n };\n \n /* End Eventdev related defines and structs */\ndiff --git a/drivers/event/dlb2/pf/dlb2_pf.c b/drivers/event/dlb2/pf/dlb2_pf.c\nindex 249ed7ede9..ba22f37731 100644\n--- a/drivers/event/dlb2/pf/dlb2_pf.c\n+++ b/drivers/event/dlb2/pf/dlb2_pf.c\n@@ -422,6 +422,7 @@ dlb2_pf_dir_port_create(struct dlb2_hw_dev *handle,\n \t\t\t\t cfg,\n \t\t\t\t cq_base,\n \t\t\t\t &response);\n+\tcfg->response = response;\n \tif (ret)\n \t\tgoto create_port_err;\n \n@@ -437,8 +438,6 @@ dlb2_pf_dir_port_create(struct dlb2_hw_dev *handle,\n \n \tdlb2_list_init_head(&port_memory.list);\n \n-\tcfg->response = response;\n-\n \treturn 0;\n \n create_port_err:\n@@ -731,7 +730,9 @@ dlb2_eventdev_pci_init(struct rte_eventdev *eventdev)\n \t\t.hw_credit_quanta = DLB2_SW_CREDIT_BATCH_SZ,\n \t\t.default_depth_thresh = DLB2_DEPTH_THRESH_DEFAULT,\n \t\t.max_cq_depth = DLB2_DEFAULT_CQ_DEPTH,\n-\t\t.max_enq_depth = DLB2_MAX_ENQUEUE_DEPTH\n+\t\t.max_enq_depth = DLB2_MAX_ENQUEUE_DEPTH,\n+\t\t.use_default_hl = true,\n+\t\t.alloc_hl_entries = 0\n \t};\n \tstruct dlb2_eventdev *dlb2;\n \tint q;\ndiff --git a/drivers/event/dlb2/rte_pmd_dlb2.h b/drivers/event/dlb2/rte_pmd_dlb2.h\nindex 6e78dfb5a5..91b47ede11 100644\n--- a/drivers/event/dlb2/rte_pmd_dlb2.h\n+++ b/drivers/event/dlb2/rte_pmd_dlb2.h\n@@ -75,6 +75,7 @@ rte_pmd_dlb2_set_token_pop_mode(uint8_t dev_id,\n \n struct dlb2_port_param {\n \tuint16_t inflight_threshold : 12;\n+\tuint16_t port_hl;\n };\n \n /*!\n", "prefixes": [ "v2", "2/3" ] }