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GET /api/patches/139845/?format=api
{ "id": 139845, "url": "http://patchwork.dpdk.org/api/patches/139845/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/11bf7bedca049e25dc2eb9e42a26c4e45900922d.1714744628.git.anatoly.burakov@intel.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<11bf7bedca049e25dc2eb9e42a26c4e45900922d.1714744628.git.anatoly.burakov@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/11bf7bedca049e25dc2eb9e42a26c4e45900922d.1714744628.git.anatoly.burakov@intel.com", "date": "2024-05-03T13:57:48", "name": "[v2,17/27] net/ixgbe/base: add missing QV defines", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "8a56b48cd4f63f8a8290dd0b4a83fba903a26317", "submitter": { "id": 4, "url": "http://patchwork.dpdk.org/api/people/4/?format=api", "name": "Burakov, Anatoly", "email": "anatoly.burakov@intel.com" }, "delegate": null, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/11bf7bedca049e25dc2eb9e42a26c4e45900922d.1714744628.git.anatoly.burakov@intel.com/mbox/", "series": [ { "id": 31875, "url": "http://patchwork.dpdk.org/api/series/31875/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=31875", "date": "2024-05-03T13:57:31", "name": "Update IXGBE base driver", "version": 2, "mbox": "http://patchwork.dpdk.org/series/31875/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/139845/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/139845/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id D093E43F76;\n\tFri, 3 May 2024 16:00:18 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 2185040E64;\n\tFri, 3 May 2024 15:58:57 +0200 (CEST)", "from mgamail.intel.com (mgamail.intel.com [192.198.163.15])\n by mails.dpdk.org (Postfix) with ESMTP id 0CA2540E09\n for <dev@dpdk.org>; Fri, 3 May 2024 15:58:54 +0200 (CEST)", "from fmviesa002.fm.intel.com ([10.60.135.142])\n by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 03 May 2024 06:58:54 -0700", "from silpixa00401119.ir.intel.com ([10.55.129.167])\n by fmviesa002.fm.intel.com with ESMTP; 03 May 2024 06:58:53 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1714744735; x=1746280735;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=nk4D9SUBDAfWvFzTKQ2Sx3ixpH/Y8PPIkUKqRhAn3zo=;\n b=gR/H8ULy0LKmP/LJpA2AQAlnT/9qzwZiw1TyuHWg+gyBDwH9Joi33YtC\n tdkYlqTZaYt5jOiYM+eUssflriKcclpMk2pWBHjowLMXoM4m/tAzTl6W8\n 5Qp7kXvM5R4pd9LJuKVAFRcb8DQ0Fy3N4+cCYfOMi9SFQM/qW4S8q00Ck\n WTnHJscyGdUTjuHv8D9A0MxCBeE5vQSfrUBMKgNWQVMwMDCQIjSwgZvnw\n c8dkpGgV7/gpIv04XW0w5RFD6jmXclSThfMgxkNo9bMYwVQHN5SVA3OWf\n pI86kKAtvZDSzk5nNmKdvUBOPrPqOiDHRja2JbB4jHQ21CImVCN6T3doI g==;", "X-CSE-ConnectionGUID": [ "cvYWkTCKREmAowsrlNndDA==", "2P3FzTqxQTys1z2I9fxJeA==" ], "X-CSE-MsgGUID": [ "aCytvXhOQNmLviJeen7OiQ==", "ySbGAgD6S3eMiWp3hnKMhg==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6600,9927,11063\"; a=\"10714958\"", "E=Sophos;i=\"6.07,251,1708416000\"; d=\"scan'208\";a=\"10714958\"", "E=Sophos;i=\"6.07,251,1708416000\"; d=\"scan'208\";a=\"50642034\"" ], "X-ExtLoop1": "1", "From": "Anatoly Burakov <anatoly.burakov@intel.com>", "To": "dev@dpdk.org", "Cc": "Barbara Skobiej <barbara.skobiej@intel.com>, bruce.richardson@intel.com,\n vladimir.medvedkin@intel.com, Jan Sokolowski <jan.sokolowski@intel.com>", "Subject": "[PATCH v2 17/27] net/ixgbe/base: add missing QV defines", "Date": "Fri, 3 May 2024 14:57:48 +0100", "Message-ID": "\n <11bf7bedca049e25dc2eb9e42a26c4e45900922d.1714744628.git.anatoly.burakov@intel.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<cover.1714744628.git.anatoly.burakov@intel.com>", "References": "<cover.1713964707.git.anatoly.burakov@intel.com>\n <cover.1714744628.git.anatoly.burakov@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Barbara Skobiej <barbara.skobiej@intel.com>\n\nThis patch adds missing QV defines:\n- offset of ANVM data\n- Immediate Field module pointer offset\n- 2.5GBASE-T and 5GBASE-T physical layer types for X550\n\nSigned-off-by: Barbara Skobiej <barbara.skobiej@intel.com>\nSigned-off-by: Jan Sokolowski <jan.sokolowski@intel.com>\n---\n drivers/net/ixgbe/base/ixgbe_type.h | 5 +++++\n 1 file changed, 5 insertions(+)", "diff": "diff --git a/drivers/net/ixgbe/base/ixgbe_type.h b/drivers/net/ixgbe/base/ixgbe_type.h\nindex 5bf03a1f62..9fed8b005c 100644\n--- a/drivers/net/ixgbe/base/ixgbe_type.h\n+++ b/drivers/net/ixgbe/base/ixgbe_type.h\n@@ -3072,6 +3072,7 @@ enum ixgbe_fdir_pballoc_type {\n #define FW_SHADOW_RAM_DUMP_LEN\t\t0\n #define FW_DEFAULT_CHECKSUM\t\t0xFF /* checksum always 0xFF */\n #define FW_NVM_DATA_OFFSET\t\t3\n+#define FW_ANVM_DATA_OFFSET\t\t3\n #define FW_MAX_READ_BUFFER_SIZE\t\t1024\n #define FW_DISABLE_RXEN_CMD\t\t0xDE\n #define FW_DISABLE_RXEN_LEN\t\t0x1\n@@ -3143,6 +3144,8 @@ enum ixgbe_fdir_pballoc_type {\n #define FW_PHY_INFO_ID_HI_MASK\t\t0xFFFF0000u\n #define FW_PHY_INFO_ID_LO_MASK\t\t0x0000FFFFu\n \n+#define IXGBE_SR_IMMEDIATE_VALUES_PTR\t\t0x4E\n+\n /* Host Interface Command Structures */\n \n #pragma pack(push, 1)\n@@ -3446,6 +3449,8 @@ typedef u64 ixgbe_physical_layer;\n #define IXGBE_PHYSICAL_LAYER_1000BASE_SX\t0x04000\n #define IXGBE_PHYSICAL_LAYER_10BASE_T\t\t0x08000\n #define IXGBE_PHYSICAL_LAYER_2500BASE_KX\t0x10000\n+#define IXGBE_PHYSICAL_LAYER_2500BASE_T\t\t0x20000\n+#define IXGBE_PHYSICAL_LAYER_5000BASE_T\t\t0x40000\n \n /* Flow Control Data Sheet defined values\n * Calculation and defines taken from 802.1bb Annex O\n", "prefixes": [ "v2", "17/27" ] }