Patch Detail

HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 139850,
    "url": "http://patchwork.dpdk.org/api/patches/139850/?format=api",
    "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/6014fea5c86f1f48d358c7f2b467a9bb396dc261.1714744628.git.anatoly.burakov@intel.com/",
    "project": {
        "id": 1,
        "url": "http://patchwork.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<6014fea5c86f1f48d358c7f2b467a9bb396dc261.1714744628.git.anatoly.burakov@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/6014fea5c86f1f48d358c7f2b467a9bb396dc261.1714744628.git.anatoly.burakov@intel.com",
    "date": "2024-05-03T13:57:53",
    "name": "[v2,22/27] net/ixgbe/base: add support for E610 Admin Command Interface",
    "commit_ref": null,
    "pull_url": null,
    "state": "new",
    "archived": false,
    "hash": "2f884876f9c271fa745b47a7f617b885fa117e89",
    "submitter": {
        "id": 4,
        "url": "http://patchwork.dpdk.org/api/people/4/?format=api",
        "name": "Burakov, Anatoly",
        "email": "anatoly.burakov@intel.com"
    },
    "delegate": null,
    "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/6014fea5c86f1f48d358c7f2b467a9bb396dc261.1714744628.git.anatoly.burakov@intel.com/mbox/",
    "series": [
        {
            "id": 31875,
            "url": "http://patchwork.dpdk.org/api/series/31875/?format=api",
            "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=31875",
            "date": "2024-05-03T13:57:31",
            "name": "Update IXGBE base driver",
            "version": 2,
            "mbox": "http://patchwork.dpdk.org/series/31875/mbox/"
        }
    ],
    "comments": "http://patchwork.dpdk.org/api/patches/139850/comments/",
    "check": "warning",
    "checks": "http://patchwork.dpdk.org/api/patches/139850/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id B31AD43F76;\n\tFri,  3 May 2024 16:00:54 +0200 (CEST)",
            "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 957D94067D;\n\tFri,  3 May 2024 15:59:08 +0200 (CEST)",
            "from mgamail.intel.com (mgamail.intel.com [192.198.163.15])\n by mails.dpdk.org (Postfix) with ESMTP id 3581440E72\n for <dev@dpdk.org>; Fri,  3 May 2024 15:59:05 +0200 (CEST)",
            "from fmviesa002.fm.intel.com ([10.60.135.142])\n by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 03 May 2024 06:59:04 -0700",
            "from silpixa00401119.ir.intel.com ([10.55.129.167])\n by fmviesa002.fm.intel.com with ESMTP; 03 May 2024 06:59:01 -0700"
        ],
        "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1714744745; x=1746280745;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=pzBX8uf59SlhP00PQ8JDh4mNglTFVEPK7PcmtzlABSU=;\n b=YDYuql2cRp5H7LAu1CbK3soqFIy+YupUOkZ3bl+GFNxMOY2VIzriHkHt\n eDg5n3qpefXJ6ozCKiOmm707LATw0pQg+85w3Y378yhK1g8dZZL8G9eFf\n ftwkUIAht4Vfidkcu5CVaRBrOmqhHyvqVFIN3JT7Pbxxr1lBb7W3uxV4A\n gj5UVLQzIPwe9toZ027WEvXg4ByI65yWML+AKxbvpbHkV28ILEkcWWvDj\n o4HH8PCisLBHhyT+LNFuCZMb10zB/oM++BFb4qVnQ+f8TxGOc3VeMEfPP\n Dfpe3hCtQMabv6DPIl5kssxawP4NpGF+K4IUlKh+sMoQ1rsls7EGVEL3G g==;",
        "X-CSE-ConnectionGUID": [
            "bPJD/Aa7SCODprYHbFIl8w==",
            "k1/lFLvxQp2bfPANFqG/4Q=="
        ],
        "X-CSE-MsgGUID": [
            "xEhTiPG9S0GkJtD+3NzWMw==",
            "3zbVddtbQkGWDiTRR+BGwg=="
        ],
        "X-IronPort-AV": [
            "E=McAfee;i=\"6600,9927,11063\"; a=\"10714976\"",
            "E=Sophos;i=\"6.07,251,1708416000\"; d=\"scan'208\";a=\"10714976\"",
            "E=Sophos;i=\"6.07,251,1708416000\"; d=\"scan'208\";a=\"50642051\""
        ],
        "X-ExtLoop1": "1",
        "From": "Anatoly Burakov <anatoly.burakov@intel.com>",
        "To": "dev@dpdk.org",
        "Cc": "Piotr Kwapulinski <piotr.kwapulinski@intel.com>,\n bruce.richardson@intel.com, vladimir.medvedkin@intel.com,\n Stefan Wegrzyn <stefan.wegrzyn@intel.com>,\n Jedrzej Jagielski <jedrzej.jagielski@intel.com>",
        "Subject": "[PATCH v2 22/27] net/ixgbe/base: add support for E610 Admin Command\n Interface",
        "Date": "Fri,  3 May 2024 14:57:53 +0100",
        "Message-ID": "\n <6014fea5c86f1f48d358c7f2b467a9bb396dc261.1714744628.git.anatoly.burakov@intel.com>",
        "X-Mailer": "git-send-email 2.43.0",
        "In-Reply-To": "<cover.1714744628.git.anatoly.burakov@intel.com>",
        "References": "<cover.1713964707.git.anatoly.burakov@intel.com>\n <cover.1714744628.git.anatoly.burakov@intel.com>",
        "MIME-Version": "1.0",
        "Content-Transfer-Encoding": "8bit",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.29",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org"
    },
    "content": "From: Piotr Kwapulinski <piotr.kwapulinski@intel.com>\n\nAdd low level support for Admin Command Interface (ACI). ACI is the\nFirmware interface used by a driver to communicate with E610 adapter. Add\nthe following ACI features:\n- data structures, macros, register definitions\n- commands handling\n- events handling\n\nSigned-off-by: Stefan Wegrzyn <stefan.wegrzyn@intel.com>\nSigned-off-by: Jedrzej Jagielski <jedrzej.jagielski@intel.com>\nSigned-off-by: Piotr Kwapulinski <piotr.kwapulinski@intel.com>\nSigned-off-by: Anatoly Burakov <anatoly.burakov@intel.com>\n---\n drivers/net/ixgbe/base/ixgbe_e610.c      |  569 ++++++++\n drivers/net/ixgbe/base/ixgbe_e610.h      |   25 +\n drivers/net/ixgbe/base/ixgbe_osdep.c     |   47 +\n drivers/net/ixgbe/base/ixgbe_osdep.h     |   18 +-\n drivers/net/ixgbe/base/ixgbe_type.h      |   59 +-\n drivers/net/ixgbe/base/ixgbe_type_e610.h | 1682 ++++++++++++++++++++++\n drivers/net/ixgbe/base/meson.build       |    4 +-\n 7 files changed, 2400 insertions(+), 4 deletions(-)\n create mode 100644 drivers/net/ixgbe/base/ixgbe_e610.c\n create mode 100644 drivers/net/ixgbe/base/ixgbe_e610.h\n create mode 100644 drivers/net/ixgbe/base/ixgbe_osdep.c\n create mode 100644 drivers/net/ixgbe/base/ixgbe_type_e610.h",
    "diff": "diff --git a/drivers/net/ixgbe/base/ixgbe_e610.c b/drivers/net/ixgbe/base/ixgbe_e610.c\nnew file mode 100644\nindex 0000000000..a989fd741a\n--- /dev/null\n+++ b/drivers/net/ixgbe/base/ixgbe_e610.c\n@@ -0,0 +1,569 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2024 Intel Corporation\n+ */\n+\n+#include \"ixgbe_type.h\"\n+#include \"ixgbe_e610.h\"\n+#include \"ixgbe_x550.h\"\n+#include \"ixgbe_common.h\"\n+#include \"ixgbe_phy.h\"\n+#include \"ixgbe_api.h\"\n+\n+/**\n+ * ixgbe_init_aci - initialization routine for Admin Command Interface\n+ * @hw: pointer to the hardware structure\n+ *\n+ * Initialize the ACI lock.\n+ */\n+void ixgbe_init_aci(struct ixgbe_hw *hw)\n+{\n+\tixgbe_init_lock(&hw->aci.lock);\n+}\n+\n+/**\n+ * ixgbe_shutdown_aci - shutdown routine for Admin Command Interface\n+ * @hw: pointer to the hardware structure\n+ *\n+ * Destroy the ACI lock.\n+ */\n+void ixgbe_shutdown_aci(struct ixgbe_hw *hw)\n+{\n+\tixgbe_destroy_lock(&hw->aci.lock);\n+}\n+\n+/**\n+ * ixgbe_should_retry_aci_send_cmd_execute - decide if ACI command should\n+ * be resent\n+ * @opcode: ACI opcode\n+ *\n+ * Check if ACI command should be sent again depending on the provided opcode.\n+ *\n+ * Return: true if the sending command routine should be repeated,\n+ * otherwise false.\n+ */\n+STATIC bool ixgbe_should_retry_aci_send_cmd_execute(u16 opcode)\n+{\n+\n+\tswitch (opcode) {\n+\tcase ixgbe_aci_opc_disable_rxen:\n+\tcase ixgbe_aci_opc_get_phy_caps:\n+\tcase ixgbe_aci_opc_get_link_status:\n+\tcase ixgbe_aci_opc_get_link_topo:\n+\t\treturn true;\n+\t}\n+\n+\treturn false;\n+}\n+\n+/**\n+ * ixgbe_aci_send_cmd_execute - execute sending FW Admin Command to FW Admin\n+ * Command Interface\n+ * @hw: pointer to the HW struct\n+ * @desc: descriptor describing the command\n+ * @buf: buffer to use for indirect commands (NULL for direct commands)\n+ * @buf_size: size of buffer for indirect commands (0 for direct commands)\n+ *\n+ * Admin Command is sent using CSR by setting descriptor and buffer in specific\n+ * registers.\n+ *\n+ * Return: the exit code of the operation.\n+ * * - IXGBE_SUCCESS - success.\n+ * * - IXGBE_ERR_ACI_DISABLED - CSR mechanism is not enabled.\n+ * * - IXGBE_ERR_ACI_BUSY - CSR mechanism is busy.\n+ * * - IXGBE_ERR_PARAM - buf_size is too big or\n+ * invalid argument buf or buf_size.\n+ * * - IXGBE_ERR_ACI_TIMEOUT - Admin Command X command timeout.\n+ * * - IXGBE_ERR_ACI_ERROR - Admin Command X invalid state of HICR register or\n+ * Admin Command failed because of bad opcode was returned or\n+ * Admin Command failed with error Y.\n+ */\n+STATIC s32\n+ixgbe_aci_send_cmd_execute(struct ixgbe_hw *hw, struct ixgbe_aci_desc *desc,\n+\t\t\t   void *buf, u16 buf_size)\n+{\n+\tu32 hicr = 0, tmp_buf_size = 0, i = 0;\n+\tu32 *raw_desc = (u32 *)desc;\n+\ts32 status = IXGBE_SUCCESS;\n+\tbool valid_buf = false;\n+\tu32 *tmp_buf = NULL;\n+\tu16 opcode = 0;\n+\n+\tdo {\n+\t\thw->aci.last_status = IXGBE_ACI_RC_OK;\n+\n+\t\t/* It's necessary to check if mechanism is enabled */\n+\t\thicr = IXGBE_READ_REG(hw, PF_HICR);\n+\t\tif (!(hicr & PF_HICR_EN)) {\n+\t\t\tstatus = IXGBE_ERR_ACI_DISABLED;\n+\t\t\tbreak;\n+\t\t}\n+\t\tif (hicr & PF_HICR_C) {\n+\t\t\thw->aci.last_status = IXGBE_ACI_RC_EBUSY;\n+\t\t\tstatus = IXGBE_ERR_ACI_BUSY;\n+\t\t\tbreak;\n+\t\t}\n+\t\topcode = desc->opcode;\n+\n+\t\tif (buf_size > IXGBE_ACI_MAX_BUFFER_SIZE) {\n+\t\t\tstatus = IXGBE_ERR_PARAM;\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tif (buf)\n+\t\t\tdesc->flags |= IXGBE_CPU_TO_LE16(IXGBE_ACI_FLAG_BUF);\n+\n+\t\t/* Check if buf and buf_size are proper params */\n+\t\tif (desc->flags & IXGBE_CPU_TO_LE16(IXGBE_ACI_FLAG_BUF)) {\n+\t\t\tif ((buf && buf_size == 0) ||\n+\t\t\t    (buf == NULL && buf_size)) {\n+\t\t\t\tstatus = IXGBE_ERR_PARAM;\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t\tif (buf && buf_size)\n+\t\t\t\tvalid_buf = true;\n+\t\t}\n+\n+\t\tif (valid_buf == true) {\n+\t\t\tif (buf_size % 4 == 0)\n+\t\t\t\ttmp_buf_size = buf_size;\n+\t\t\telse\n+\t\t\t\ttmp_buf_size = (buf_size & (u16)(~0x03)) + 4;\n+\n+\t\t\ttmp_buf = (u32*)ixgbe_malloc(hw, tmp_buf_size);\n+\t\t\tif (!tmp_buf)\n+\t\t\t\treturn IXGBE_ERR_OUT_OF_MEM;\n+\n+\t\t\t/* tmp_buf will be firstly filled with 0xFF and after\n+\t\t\t * that the content of buf will be written into it.\n+\t\t\t * This approach lets us use valid buf_size and\n+\t\t\t * prevents us from reading past buf area\n+\t\t\t * when buf_size mod 4 not equal to 0.\n+\t\t\t */\n+\t\t\tmemset(tmp_buf, 0xFF, tmp_buf_size);\n+\t\t\tmemcpy(tmp_buf, buf, buf_size);\n+\n+\t\t\tif (tmp_buf_size > IXGBE_ACI_LG_BUF)\n+\t\t\t\tdesc->flags |=\n+\t\t\t\tIXGBE_CPU_TO_LE16(IXGBE_ACI_FLAG_LB);\n+\n+\t\t\tdesc->datalen = IXGBE_CPU_TO_LE16(buf_size);\n+\n+\t\t\tif (desc->flags & IXGBE_CPU_TO_LE16(IXGBE_ACI_FLAG_RD)) {\n+\t\t\t\tfor (i = 0; i < tmp_buf_size / 4; i++) {\n+\t\t\t\t\tIXGBE_WRITE_REG(hw, PF_HIBA(i),\n+\t\t\t\t\t\tIXGBE_LE32_TO_CPU(tmp_buf[i]));\n+\t\t\t\t}\n+\t\t\t}\n+\t\t}\n+\n+\t\t/* Descriptor is written to specific registers */\n+\t\tfor (i = 0; i < IXGBE_ACI_DESC_SIZE_IN_DWORDS; i++)\n+\t\t\tIXGBE_WRITE_REG(hw, PF_HIDA(i),\n+\t\t\t\t\tIXGBE_LE32_TO_CPU(raw_desc[i]));\n+\n+\t\t/* SW has to set PF_HICR.C bit and clear PF_HICR.SV and\n+\t\t * PF_HICR_EV\n+\t\t */\n+\t\thicr = IXGBE_READ_REG(hw, PF_HICR);\n+\t\thicr = (hicr | PF_HICR_C) & ~(PF_HICR_SV | PF_HICR_EV);\n+\t\tIXGBE_WRITE_REG(hw, PF_HICR, hicr);\n+\n+\t\t/* Wait for sync Admin Command response */\n+\t\tfor (i = 0; i < IXGBE_ACI_SYNC_RESPONSE_TIMEOUT; i += 1) {\n+\t\t\thicr = IXGBE_READ_REG(hw, PF_HICR);\n+\t\t\tif ((hicr & PF_HICR_SV) || !(hicr & PF_HICR_C))\n+\t\t\t\tbreak;\n+\n+\t\t\tmsec_delay(1);\n+\t\t}\n+\n+\t\t/* Wait for async Admin Command response */\n+\t\tif ((hicr & PF_HICR_SV) && (hicr & PF_HICR_C)) {\n+\t\t\tfor (i = 0; i < IXGBE_ACI_ASYNC_RESPONSE_TIMEOUT;\n+\t\t\t     i += 1) {\n+\t\t\t\thicr = IXGBE_READ_REG(hw, PF_HICR);\n+\t\t\t\tif ((hicr & PF_HICR_EV) || !(hicr & PF_HICR_C))\n+\t\t\t\t\tbreak;\n+\n+\t\t\t\tmsec_delay(1);\n+\t\t\t}\n+\t\t}\n+\n+\t\t/* Read sync Admin Command response */\n+\t\tif ((hicr & PF_HICR_SV)) {\n+\t\t\tfor (i = 0; i < IXGBE_ACI_DESC_SIZE_IN_DWORDS; i++) {\n+\t\t\t\traw_desc[i] = IXGBE_READ_REG(hw, PF_HIDA(i));\n+\t\t\t\traw_desc[i] = IXGBE_CPU_TO_LE32(raw_desc[i]);\n+\t\t\t}\n+\t\t}\n+\n+\t\t/* Read async Admin Command response */\n+\t\tif ((hicr & PF_HICR_EV) && !(hicr & PF_HICR_C)) {\n+\t\t\tfor (i = 0; i < IXGBE_ACI_DESC_SIZE_IN_DWORDS; i++) {\n+\t\t\t\traw_desc[i] = IXGBE_READ_REG(hw, PF_HIDA_2(i));\n+\t\t\t\traw_desc[i] = IXGBE_CPU_TO_LE32(raw_desc[i]);\n+\t\t\t}\n+\t\t}\n+\n+\t\t/* Handle timeout and invalid state of HICR register */\n+\t\tif (hicr & PF_HICR_C) {\n+\t\t\tstatus = IXGBE_ERR_ACI_TIMEOUT;\n+\t\t\tbreak;\n+\t\t} else if (!(hicr & PF_HICR_SV) && !(hicr & PF_HICR_EV)) {\n+\t\t\tstatus = IXGBE_ERR_ACI_ERROR;\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\t/* For every command other than 0x0014 treat opcode mismatch\n+\t\t * as an error. Response to 0x0014 command read from HIDA_2\n+\t\t * is a descriptor of an event which is expected to contain\n+\t\t * different opcode than the command.\n+\t\t */\n+\t\tif (desc->opcode != opcode &&\n+\t\t    opcode != IXGBE_CPU_TO_LE16(ixgbe_aci_opc_get_fw_event)) {\n+\t\t\tstatus = IXGBE_ERR_ACI_ERROR;\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tif (desc->retval != IXGBE_ACI_RC_OK) {\n+\t\t\thw->aci.last_status = (enum ixgbe_aci_err)desc->retval;\n+\t\t\tstatus = IXGBE_ERR_ACI_ERROR;\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\t/* Write a response values to a buf */\n+\t\tif (valid_buf && (desc->flags &\n+\t\t\t\t  IXGBE_CPU_TO_LE16(IXGBE_ACI_FLAG_BUF))) {\n+\t\t\tfor (i = 0; i < tmp_buf_size / 4; i++) {\n+\t\t\t\ttmp_buf[i] = IXGBE_READ_REG(hw, PF_HIBA(i));\n+\t\t\t\ttmp_buf[i] = IXGBE_CPU_TO_LE32(tmp_buf[i]);\n+\t\t\t}\n+\t\t\tmemcpy(buf, tmp_buf, buf_size);\n+\t\t}\n+\t} while (0);\n+\n+\tif (tmp_buf)\n+\t\tixgbe_free(hw, tmp_buf);\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ixgbe_aci_send_cmd - send FW Admin Command to FW Admin Command Interface\n+ * @hw: pointer to the HW struct\n+ * @desc: descriptor describing the command\n+ * @buf: buffer to use for indirect commands (NULL for direct commands)\n+ * @buf_size: size of buffer for indirect commands (0 for direct commands)\n+ *\n+ * Helper function to send FW Admin Commands to the FW Admin Command Interface.\n+ *\n+ * Retry sending the FW Admin Command multiple times to the FW ACI\n+ * if the EBUSY Admin Command error is returned.\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_aci_send_cmd(struct ixgbe_hw *hw, struct ixgbe_aci_desc *desc,\n+\t\t       void *buf, u16 buf_size)\n+{\n+\tstruct ixgbe_aci_desc desc_cpy;\n+\tenum ixgbe_aci_err last_status;\n+\tbool is_cmd_for_retry;\n+\tu8 *buf_cpy = NULL;\n+\ts32 status;\n+\tu16 opcode;\n+\tu8 idx = 0;\n+\n+\topcode = IXGBE_LE16_TO_CPU(desc->opcode);\n+\tis_cmd_for_retry = ixgbe_should_retry_aci_send_cmd_execute(opcode);\n+\tmemset(&desc_cpy, 0, sizeof(desc_cpy));\n+\n+\tif (is_cmd_for_retry) {\n+\t\tif (buf) {\n+\t\t\tbuf_cpy = (u8 *)ixgbe_malloc(hw, buf_size);\n+\t\t\tif (!buf_cpy)\n+\t\t\t\treturn IXGBE_ERR_OUT_OF_MEM;\n+\t\t}\n+\t\tmemcpy(&desc_cpy, desc, sizeof(desc_cpy));\n+\t}\n+\n+\tdo {\n+\t\tixgbe_acquire_lock(&hw->aci.lock);\n+\t\tstatus = ixgbe_aci_send_cmd_execute(hw, desc, buf, buf_size);\n+\t\tlast_status = hw->aci.last_status;\n+\t\tixgbe_release_lock(&hw->aci.lock);\n+\n+\t\tif (!is_cmd_for_retry || status == IXGBE_SUCCESS ||\n+\t\t    last_status != IXGBE_ACI_RC_EBUSY)\n+\t\t\tbreak;\n+\n+\t\tif (buf)\n+\t\t\tmemcpy(buf, buf_cpy, buf_size);\n+\t\tmemcpy(desc, &desc_cpy, sizeof(desc_cpy));\n+\n+\t\tmsec_delay(IXGBE_ACI_SEND_DELAY_TIME_MS);\n+\t} while (++idx < IXGBE_ACI_SEND_MAX_EXECUTE);\n+\n+\tif (buf_cpy)\n+\t\tixgbe_free(hw, buf_cpy);\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ixgbe_aci_check_event_pending - check if there are any pending events\n+ * @hw: pointer to the HW struct\n+ *\n+ * Determine if there are any pending events.\n+ *\n+ * Return: true if there are any currently pending events\n+ * otherwise false.\n+ */\n+bool ixgbe_aci_check_event_pending(struct ixgbe_hw *hw)\n+{\n+\tu32 ep_bit_mask;\n+\tu32 fwsts;\n+\n+\tep_bit_mask = hw->bus.func ? GL_FWSTS_EP_PF1 : GL_FWSTS_EP_PF0;\n+\n+\t/* Check state of Event Pending (EP) bit */\n+\tfwsts = IXGBE_READ_REG(hw, GL_FWSTS);\n+\treturn (fwsts & ep_bit_mask) ? true : false;\n+}\n+\n+/**\n+ * ixgbe_aci_get_event - get an event from ACI\n+ * @hw: pointer to the HW struct\n+ * @e: event information structure\n+ * @pending: optional flag signaling that there are more pending events\n+ *\n+ * Obtain an event from ACI and return its content\n+ * through 'e' using ACI command (0x0014).\n+ * Provide information if there are more events\n+ * to retrieve through 'pending'.\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_aci_get_event(struct ixgbe_hw *hw, struct ixgbe_aci_event *e,\n+\t\t\tbool *pending)\n+{\n+\tstruct ixgbe_aci_desc desc;\n+\ts32 status;\n+\n+\tif (!e || (!e->msg_buf && e->buf_len) || (e->msg_buf && !e->buf_len))\n+\t\treturn IXGBE_ERR_PARAM;\n+\n+\tixgbe_acquire_lock(&hw->aci.lock);\n+\n+\t/* Check if there are any events pending */\n+\tif (!ixgbe_aci_check_event_pending(hw)) {\n+\t\tstatus = IXGBE_ERR_ACI_NO_EVENTS;\n+\t\tgoto aci_get_event_exit;\n+\t}\n+\n+\t/* Obtain pending event */\n+\tixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_get_fw_event);\n+\tstatus = ixgbe_aci_send_cmd_execute(hw, &desc, e->msg_buf, e->buf_len);\n+\tif (status)\n+\t\tgoto aci_get_event_exit;\n+\n+\t/* Returned 0x0014 opcode indicates that no event was obtained */\n+\tif (desc.opcode == IXGBE_CPU_TO_LE16(ixgbe_aci_opc_get_fw_event)) {\n+\t\tstatus = IXGBE_ERR_ACI_NO_EVENTS;\n+\t\tgoto aci_get_event_exit;\n+\t}\n+\n+\t/* Determine size of event data */\n+\te->msg_len = MIN_T(u16, IXGBE_LE16_TO_CPU(desc.datalen), e->buf_len);\n+\t/* Write event descriptor to event info structure */\n+\tmemcpy(&e->desc, &desc, sizeof(e->desc));\n+\n+\t/* Check if there are any further events pending */\n+\tif (pending) {\n+\t\t*pending = ixgbe_aci_check_event_pending(hw);\n+\t}\n+\n+aci_get_event_exit:\n+\tixgbe_release_lock(&hw->aci.lock);\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ixgbe_fill_dflt_direct_cmd_desc - fill ACI descriptor with default values.\n+ * @desc: pointer to the temp descriptor (non DMA mem)\n+ * @opcode: the opcode can be used to decide which flags to turn off or on\n+ *\n+ * Helper function to fill the descriptor desc with default values\n+ * and the provided opcode.\n+ */\n+void ixgbe_fill_dflt_direct_cmd_desc(struct ixgbe_aci_desc *desc, u16 opcode)\n+{\n+\t/* zero out the desc */\n+\tmemset(desc, 0, sizeof(*desc));\n+\tdesc->opcode = IXGBE_CPU_TO_LE16(opcode);\n+\tdesc->flags = IXGBE_CPU_TO_LE16(IXGBE_ACI_FLAG_SI);\n+}\n+\n+/**\n+ * ixgbe_aci_req_res - request a common resource\n+ * @hw: pointer to the HW struct\n+ * @res: resource ID\n+ * @access: access type\n+ * @sdp_number: resource number\n+ * @timeout: the maximum time in ms that the driver may hold the resource\n+ *\n+ * Requests a common resource using the ACI command (0x0008).\n+ * Specifies the maximum time the driver may hold the resource.\n+ * If the requested resource is currently occupied by some other driver,\n+ * a busy return value is returned and the timeout field value indicates the\n+ * maximum time the current owner has to free it.\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+static s32\n+ixgbe_aci_req_res(struct ixgbe_hw *hw, enum ixgbe_aci_res_ids res,\n+\t\t  enum ixgbe_aci_res_access_type access, u8 sdp_number,\n+\t\t  u32 *timeout)\n+{\n+\tstruct ixgbe_aci_cmd_req_res *cmd_resp;\n+\tstruct ixgbe_aci_desc desc;\n+\ts32 status;\n+\n+\tcmd_resp = &desc.params.res_owner;\n+\n+\tixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_req_res);\n+\n+\tcmd_resp->res_id = IXGBE_CPU_TO_LE16(res);\n+\tcmd_resp->access_type = IXGBE_CPU_TO_LE16(access);\n+\tcmd_resp->res_number = IXGBE_CPU_TO_LE32(sdp_number);\n+\tcmd_resp->timeout = IXGBE_CPU_TO_LE32(*timeout);\n+\t*timeout = 0;\n+\n+\tstatus = ixgbe_aci_send_cmd(hw, &desc, NULL, 0);\n+\n+\t/* The completion specifies the maximum time in ms that the driver\n+\t * may hold the resource in the Timeout field.\n+\t */\n+\n+\t/* If the resource is held by some other driver, the command completes\n+\t * with a busy return value and the timeout field indicates the maximum\n+\t * time the current owner of the resource has to free it.\n+\t */\n+\tif (!status || hw->aci.last_status == IXGBE_ACI_RC_EBUSY)\n+\t\t*timeout = IXGBE_LE32_TO_CPU(cmd_resp->timeout);\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ixgbe_aci_release_res - release a common resource using ACI\n+ * @hw: pointer to the HW struct\n+ * @res: resource ID\n+ * @sdp_number: resource number\n+ *\n+ * Release a common resource using ACI command (0x0009).\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+static s32\n+ixgbe_aci_release_res(struct ixgbe_hw *hw, enum ixgbe_aci_res_ids res,\n+\t\t      u8 sdp_number)\n+{\n+\tstruct ixgbe_aci_cmd_req_res *cmd;\n+\tstruct ixgbe_aci_desc desc;\n+\n+\tcmd = &desc.params.res_owner;\n+\n+\tixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_release_res);\n+\n+\tcmd->res_id = IXGBE_CPU_TO_LE16(res);\n+\tcmd->res_number = IXGBE_CPU_TO_LE32(sdp_number);\n+\n+\treturn ixgbe_aci_send_cmd(hw, &desc, NULL, 0);\n+}\n+\n+/**\n+ * ixgbe_acquire_res - acquire the ownership of a resource\n+ * @hw: pointer to the HW structure\n+ * @res: resource ID\n+ * @access: access type (read or write)\n+ * @timeout: timeout in milliseconds\n+ *\n+ * Make an attempt to acquire the ownership of a resource using\n+ * the ixgbe_aci_req_res to utilize ACI.\n+ * In case if some other driver has previously acquired the resource and\n+ * performed any necessary updates, the IXGBE_ERR_ACI_NO_WORK is returned,\n+ * and the caller does not obtain the resource and has no further work to do.\n+ * If needed, the function will poll until the current lock owner timeouts.\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_acquire_res(struct ixgbe_hw *hw, enum ixgbe_aci_res_ids res,\n+\t\t      enum ixgbe_aci_res_access_type access, u32 timeout)\n+{\n+#define IXGBE_RES_POLLING_DELAY_MS\t10\n+\tu32 delay = IXGBE_RES_POLLING_DELAY_MS;\n+\tu32 res_timeout = timeout;\n+\tu32 retry_timeout = 0;\n+\ts32 status;\n+\n+\tstatus = ixgbe_aci_req_res(hw, res, access, 0, &res_timeout);\n+\n+\t/* A return code of IXGBE_ERR_ACI_NO_WORK means that another driver has\n+\t * previously acquired the resource and performed any necessary updates;\n+\t * in this case the caller does not obtain the resource and has no\n+\t * further work to do.\n+\t */\n+\tif (status == IXGBE_ERR_ACI_NO_WORK)\n+\t\tgoto ixgbe_acquire_res_exit;\n+\n+\t/* If necessary, poll until the current lock owner timeouts.\n+\t * Set retry_timeout to the timeout value reported by the FW in the\n+\t * response to the \"Request Resource Ownership\" (0x0008) Admin Command\n+\t * as it indicates the maximum time the current owner of the resource\n+\t * is allowed to hold it.\n+\t */\n+\tretry_timeout = res_timeout;\n+\twhile (status && retry_timeout && res_timeout) {\n+\t\tmsec_delay(delay);\n+\t\tretry_timeout = (retry_timeout > delay) ?\n+\t\t\tretry_timeout - delay : 0;\n+\t\tstatus = ixgbe_aci_req_res(hw, res, access, 0, &res_timeout);\n+\n+\t\tif (status == IXGBE_ERR_ACI_NO_WORK)\n+\t\t\t/* lock free, but no work to do */\n+\t\t\tbreak;\n+\n+\t\tif (!status)\n+\t\t\t/* lock acquired */\n+\t\t\tbreak;\n+\t}\n+\n+ixgbe_acquire_res_exit:\n+\treturn status;\n+}\n+\n+/**\n+ * ixgbe_release_res - release a common resource\n+ * @hw: pointer to the HW structure\n+ * @res: resource ID\n+ *\n+ * Release a common resource using ixgbe_aci_release_res.\n+ */\n+void ixgbe_release_res(struct ixgbe_hw *hw, enum ixgbe_aci_res_ids res)\n+{\n+\tu32 total_delay = 0;\n+\ts32 status;\n+\n+\tstatus = ixgbe_aci_release_res(hw, res, 0);\n+\n+\t/* There are some rare cases when trying to release the resource\n+\t * results in an admin command timeout, so handle them correctly.\n+\t */\n+\twhile ((status == IXGBE_ERR_ACI_TIMEOUT) &&\n+\t       (total_delay < IXGBE_ACI_RELEASE_RES_TIMEOUT)) {\n+\t\tmsec_delay(1);\n+\t\tstatus = ixgbe_aci_release_res(hw, res, 0);\n+\t\ttotal_delay++;\n+\t}\n+}\ndiff --git a/drivers/net/ixgbe/base/ixgbe_e610.h b/drivers/net/ixgbe/base/ixgbe_e610.h\nnew file mode 100644\nindex 0000000000..aeaa75af37\n--- /dev/null\n+++ b/drivers/net/ixgbe/base/ixgbe_e610.h\n@@ -0,0 +1,25 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2024 Intel Corporation\n+ */\n+\n+#ifndef _IXGBE_E610_H_\n+#define _IXGBE_E610_H_\n+\n+#include \"ixgbe_type.h\"\n+\n+void ixgbe_init_aci(struct ixgbe_hw *hw);\n+void ixgbe_shutdown_aci(struct ixgbe_hw *hw);\n+\n+s32 ixgbe_aci_send_cmd(struct ixgbe_hw *hw, struct ixgbe_aci_desc *desc,\n+\t\t       void *buf, u16 buf_size);\n+bool ixgbe_aci_check_event_pending(struct ixgbe_hw *hw);\n+s32 ixgbe_aci_get_event(struct ixgbe_hw *hw, struct ixgbe_aci_event *e,\n+\t\t\tbool *pending);\n+\n+void ixgbe_fill_dflt_direct_cmd_desc(struct ixgbe_aci_desc *desc, u16 opcode);\n+\n+s32 ixgbe_acquire_res(struct ixgbe_hw *hw, enum ixgbe_aci_res_ids res,\n+\t\t      enum ixgbe_aci_res_access_type access, u32 timeout);\n+void ixgbe_release_res(struct ixgbe_hw *hw, enum ixgbe_aci_res_ids res);\n+\n+#endif /* _IXGBE_E610_H_ */\ndiff --git a/drivers/net/ixgbe/base/ixgbe_osdep.c b/drivers/net/ixgbe/base/ixgbe_osdep.c\nnew file mode 100644\nindex 0000000000..d3d7e8e116\n--- /dev/null\n+++ b/drivers/net/ixgbe/base/ixgbe_osdep.c\n@@ -0,0 +1,47 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2024 Intel Corporation\n+ */\n+\n+#include <stdlib.h>\n+\n+#include <rte_common.h>\n+\n+#include \"ixgbe_osdep.h\"\n+\n+void *\n+ixgbe_calloc(struct ixgbe_hw __rte_unused *hw, size_t count, size_t size)\n+{\n+\treturn malloc(count * size);\n+}\n+\n+void *\n+ixgbe_malloc(struct ixgbe_hw __rte_unused *hw, size_t size)\n+{\n+\treturn malloc(size);\n+}\n+\n+void\n+ixgbe_free(struct ixgbe_hw __rte_unused *hw, void *addr)\n+{\n+\tfree(addr);\n+}\n+\n+void ixgbe_init_lock(struct ixgbe_lock *lock)\n+{\n+\tpthread_mutex_init(&lock->mutex, NULL);\n+}\n+\n+void ixgbe_destroy_lock(struct ixgbe_lock *lock)\n+{\n+\tpthread_mutex_destroy(&lock->mutex);\n+}\n+\n+void ixgbe_acquire_lock(struct ixgbe_lock *lock)\n+{\n+\tpthread_mutex_lock(&lock->mutex);\n+}\n+\n+void ixgbe_release_lock(struct ixgbe_lock *lock)\n+{\n+\tpthread_mutex_unlock(&lock->mutex);\n+}\ndiff --git a/drivers/net/ixgbe/base/ixgbe_osdep.h b/drivers/net/ixgbe/base/ixgbe_osdep.h\nindex 6c25f608b1..b3266a3c77 100644\n--- a/drivers/net/ixgbe/base/ixgbe_osdep.h\n+++ b/drivers/net/ixgbe/base/ixgbe_osdep.h\n@@ -1,10 +1,11 @@\n /* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(c) 2001-2020 Intel Corporation\n+ * Copyright(c) 2001-2024 Intel Corporation\n  */\n \n #ifndef _IXGBE_OS_H_\n #define _IXGBE_OS_H_\n \n+#include <pthread.h>\n #include <string.h>\n #include <stdint.h>\n #include <stdio.h>\n@@ -79,6 +80,7 @@ enum {\n #define IXGBE_NTOHS(_i)\trte_be_to_cpu_16(_i)\n #define IXGBE_CPU_TO_LE16(_i)  rte_cpu_to_le_16(_i)\n #define IXGBE_CPU_TO_LE32(_i)  rte_cpu_to_le_32(_i)\n+#define IXGBE_LE16_TO_CPU(_i)  rte_le_to_cpu_16(_i)\n #define IXGBE_LE32_TO_CPU(_i)  rte_le_to_cpu_32(_i)\n #define IXGBE_LE32_TO_CPUS(_i) rte_le_to_cpu_32(_i)\n #define IXGBE_CPU_TO_BE16(_i)  rte_cpu_to_be_16(_i)\n@@ -152,4 +154,18 @@ do {\t\t\t\t\t\t\t\t\t\\\n \t\trte_delay_ms(1);\t\t\t\t\t\\\n } while (0)\n \n+struct ixgbe_hw;\n+struct ixgbe_lock {\n+\tpthread_mutex_t mutex;\n+};\n+\n+void *ixgbe_calloc(struct ixgbe_hw *hw, size_t count, size_t size);\n+void *ixgbe_malloc(struct ixgbe_hw *hw, size_t size);\n+void ixgbe_free(struct ixgbe_hw *hw, void *addr);\n+\n+void ixgbe_init_lock(struct ixgbe_lock *lock);\n+void ixgbe_destroy_lock(struct ixgbe_lock *lock);\n+void ixgbe_acquire_lock(struct ixgbe_lock *lock);\n+void ixgbe_release_lock(struct ixgbe_lock *lock);\n+\n #endif /* _IXGBE_OS_H_ */\ndiff --git a/drivers/net/ixgbe/base/ixgbe_type.h b/drivers/net/ixgbe/base/ixgbe_type.h\nindex 5db9e03b4d..fe7411541e 100644\n--- a/drivers/net/ixgbe/base/ixgbe_type.h\n+++ b/drivers/net/ixgbe/base/ixgbe_type.h\n@@ -1,5 +1,5 @@\n /* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(c) 2001-2020 Intel Corporation\n+ * Copyright(c) 2001-2024 Intel Corporation\n  */\n \n #ifndef _IXGBE_TYPE_H_\n@@ -44,6 +44,7 @@\n  */\n \n #include \"ixgbe_osdep.h\"\n+#include \"ixgbe_type_e610.h\"\n \n /* Override this by setting IOMEM in your ixgbe_osdep.h header */\n \n@@ -124,6 +125,11 @@\n #define IXGBE_DEV_ID_X550EM_A_VF_HV\t\t0x15B4\n #define IXGBE_DEV_ID_X550EM_X_VF\t\t0x15A8\n #define IXGBE_DEV_ID_X550EM_X_VF_HV\t\t0x15A9\n+#define IXGBE_DEV_ID_E610_BACKPLANE\t\t0x57AE\n+#define IXGBE_DEV_ID_E610_SFP\t\t\t0x57AF\n+#define IXGBE_DEV_ID_E610_10G_T\t\t\t0x57B0\n+#define IXGBE_DEV_ID_E610_2_5G_T\t\t0x57B1\n+#define IXGBE_DEV_ID_E610_SGMII\t\t\t0x57B2\n \n #define IXGBE_CAT(r, m) IXGBE_##r##m\n \n@@ -1887,6 +1893,7 @@ enum {\n #define IXGBE_EICR_MAILBOX\t0x00080000 /* VF to PF Mailbox Interrupt */\n #define IXGBE_EICR_LSC\t\t0x00100000 /* Link Status Change */\n #define IXGBE_EICR_LINKSEC\t0x00200000 /* PN Threshold */\n+#define IXGBE_EICR_FW_EVENT\t0x00200000 /* Async FW event */\n #define IXGBE_EICR_MNG\t\t0x00400000 /* Manageability Event Interrupt */\n #define IXGBE_EICR_TS\t\t0x00800000 /* Thermal Sensor Event */\n #define IXGBE_EICR_TIMESYNC\t0x01000000 /* Timesync Event */\n@@ -1922,6 +1929,7 @@ enum {\n #define IXGBE_EICS_PCI\t\tIXGBE_EICR_PCI /* PCI Exception */\n #define IXGBE_EICS_MAILBOX\tIXGBE_EICR_MAILBOX   /* VF to PF Mailbox Int */\n #define IXGBE_EICS_LSC\t\tIXGBE_EICR_LSC /* Link Status Change */\n+#define IXGBE_EICS_FW_EVENT\tIXGBE_EICR_FW_EVENT /* Async FW event */\n #define IXGBE_EICS_MNG\t\tIXGBE_EICR_MNG /* MNG Event Interrupt */\n #define IXGBE_EICS_TIMESYNC\tIXGBE_EICR_TIMESYNC /* Timesync Event */\n #define IXGBE_EICS_GPI_SDP0\tIXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */\n@@ -1943,6 +1951,7 @@ enum {\n #define IXGBE_EIMS_PCI\t\tIXGBE_EICR_PCI /* PCI Exception */\n #define IXGBE_EIMS_MAILBOX\tIXGBE_EICR_MAILBOX   /* VF to PF Mailbox Int */\n #define IXGBE_EIMS_LSC\t\tIXGBE_EICR_LSC /* Link Status Change */\n+#define IXGBE_EIMS_FW_EVENT\tIXGBE_EICR_FW_EVENT /* Async FW event */\n #define IXGBE_EIMS_MNG\t\tIXGBE_EICR_MNG /* MNG Event Interrupt */\n #define IXGBE_EIMS_TS\t\tIXGBE_EICR_TS /* Thermal Sensor Event */\n #define IXGBE_EIMS_TIMESYNC\tIXGBE_EICR_TIMESYNC /* Timesync Event */\n@@ -1965,6 +1974,7 @@ enum {\n #define IXGBE_EIMC_PCI\t\tIXGBE_EICR_PCI /* PCI Exception */\n #define IXGBE_EIMC_MAILBOX\tIXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */\n #define IXGBE_EIMC_LSC\t\tIXGBE_EICR_LSC /* Link Status Change */\n+#define IXGBE_EIMC_FW_EVENT\tIXGBE_EICR_FW_EVENT /* Async FW event */\n #define IXGBE_EIMC_MNG\t\tIXGBE_EICR_MNG /* MNG Event Interrupt */\n #define IXGBE_EIMC_TIMESYNC\tIXGBE_EICR_TIMESYNC /* Timesync Event */\n #define IXGBE_EIMC_GPI_SDP0\tIXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */\n@@ -2372,6 +2382,7 @@ enum {\n #define IXGBE_82599_SERIAL_NUMBER_MAC_ADDR\t0x11\n #define IXGBE_X550_SERIAL_NUMBER_MAC_ADDR\t0x04\n \n+#define IXGBE_PCIE_MSIX_E610_CAPS\t\t0xB2\n #define IXGBE_PCIE_MSIX_82599_CAPS\t0x72\n #define IXGBE_MAX_MSIX_VECTORS_82599\t0x40\n #define IXGBE_PCIE_MSIX_82598_CAPS\t0x62\n@@ -2489,6 +2500,7 @@ enum {\n #define IXGBE_PCI_DEVICE_STATUS\t\t0xAA\n #define IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING\t0x0020\n #define IXGBE_PCI_LINK_STATUS\t\t0xB2\n+#define IXGBE_PCI_LINK_STATUS_E610\t0x82\n #define IXGBE_PCI_DEVICE_CONTROL2\t0xC8\n #define IXGBE_PCI_LINK_WIDTH\t\t0x3F0\n #define IXGBE_PCI_LINK_WIDTH_1\t\t0x10\n@@ -2626,6 +2638,7 @@ enum {\n #define IXGBE_RXMTRL_V2_MGMT_MSG\t0x0D00\n \n #define IXGBE_FCTRL_SBP\t\t0x00000002 /* Store Bad Packet */\n+#define IXGBE_FCTRL_TPE\t\t0x00000080 /* Tag Promiscuous Ena*/\n #define IXGBE_FCTRL_MPE\t\t0x00000100 /* Multicast Promiscuous Ena*/\n #define IXGBE_FCTRL_UPE\t\t0x00000200 /* Unicast Promiscuous Ena */\n #define IXGBE_FCTRL_BAM\t\t0x00000400 /* Broadcast Accept Mode */\n@@ -2693,6 +2706,7 @@ enum {\n /* Multiple Transmit Queue Command Register */\n #define IXGBE_MTQC_RT_ENA\t0x1 /* DCB Enable */\n #define IXGBE_MTQC_VT_ENA\t0x2 /* VMDQ2 Enable */\n+#define IXGBE_MTQC_NUM_TC_OR_Q  0xC /* Numer of TCs or TxQs per pool */\n #define IXGBE_MTQC_64Q_1PB\t0x0 /* 64 queues 1 pack buffer */\n #define IXGBE_MTQC_32VF\t\t0x8 /* 4 TX Queues per pool w/32VF's */\n #define IXGBE_MTQC_64VF\t\t0x4 /* 2 TX Queues per pool w/64VF's */\n@@ -3660,6 +3674,7 @@ enum ixgbe_mac_type {\n \tixgbe_mac_X550_vf,\n \tixgbe_mac_X550EM_x_vf,\n \tixgbe_mac_X550EM_a_vf,\n+\tixgbe_mac_E610,\n \tixgbe_num_macs\n };\n \n@@ -3738,7 +3753,9 @@ enum ixgbe_media_type {\n \tixgbe_media_type_copper,\n \tixgbe_media_type_backplane,\n \tixgbe_media_type_cx4,\n-\tixgbe_media_type_virtual\n+\tixgbe_media_type_virtual,\n+\tixgbe_media_type_da,\n+\tixgbe_media_type_aui\n };\n \n /* Flow Control Settings */\n@@ -3747,6 +3764,8 @@ enum ixgbe_fc_mode {\n \tixgbe_fc_rx_pause,\n \tixgbe_fc_tx_pause,\n \tixgbe_fc_full,\n+\tixgbe_fc_auto,\n+\tixgbe_fc_pfc,\n \tixgbe_fc_default\n };\n \n@@ -4073,6 +4092,9 @@ struct ixgbe_link_operations {\n struct ixgbe_link_info {\n \tstruct ixgbe_link_operations ops;\n \tu8 addr;\n+\tstruct ixgbe_link_status link_info;\n+\tstruct ixgbe_link_status link_info_old;\n+\tu8 get_link_info;\n };\n \n struct ixgbe_eeprom_info {\n@@ -4144,6 +4166,9 @@ struct ixgbe_phy_info {\n \tbool reset_if_overtemp;\n \tbool qsfp_shared_i2c_bus;\n \tu32 nw_mng_if_sel;\n+\tu64 phy_type_low;\n+\tu64 phy_type_high;\n+\tstruct ixgbe_aci_cmd_set_phy_cfg_data curr_user_phy_cfg;\n };\n \n #include \"ixgbe_mbx.h\"\n@@ -4172,6 +4197,19 @@ struct ixgbe_hw {\n \tbool wol_enabled;\n \tbool need_crosstalk_fix;\n \tu32 fw_rst_cnt;\n+\tu8 api_branch;\n+\tu8 api_maj_ver;\n+\tu8 api_min_ver;\n+\tu8 api_patch;\n+\tu8 fw_branch;\n+\tu8 fw_maj_ver;\n+\tu8 fw_min_ver;\n+\tu8 fw_patch;\n+\tu32 fw_build;\n+\tstruct ixgbe_aci_info aci;\n+\tstruct ixgbe_flash_info flash;\n+\tstruct ixgbe_hw_dev_caps dev_caps;\n+\tstruct ixgbe_hw_func_caps func_caps;\n };\n \n #define ixgbe_call_func(hw, func, params, error) \\\n@@ -4221,6 +4259,23 @@ struct ixgbe_hw {\n #define IXGBE_ERR_MBX\t\t\t\t-41\n #define IXGBE_ERR_MBX_NOMSG\t\t\t-42\n #define IXGBE_ERR_TIMEOUT\t\t\t-43\n+#define IXGBE_ERR_NOT_SUPPORTED\t\t\t-45\n+#define IXGBE_ERR_OUT_OF_RANGE\t\t\t-46\n+\n+#define IXGBE_ERR_NVM\t\t\t\t-50\n+#define IXGBE_ERR_NVM_CHECKSUM\t\t\t-51\n+#define IXGBE_ERR_BUF_TOO_SHORT\t\t\t-52\n+#define IXGBE_ERR_NVM_BLANK_MODE\t\t-53\n+#define IXGBE_ERR_INVAL_SIZE\t\t\t-54\n+#define IXGBE_ERR_DOES_NOT_EXIST\t\t-55\n+\n+#define IXGBE_ERR_ACI_ERROR\t\t\t-100\n+#define IXGBE_ERR_ACI_DISABLED\t\t\t-101\n+#define IXGBE_ERR_ACI_TIMEOUT\t\t\t-102\n+#define IXGBE_ERR_ACI_BUSY\t\t\t-103\n+#define IXGBE_ERR_ACI_NO_WORK\t\t\t-104\n+#define IXGBE_ERR_ACI_NO_EVENTS\t\t\t-105\n+#define IXGBE_ERR_FW_API_VER\t\t\t-106\n \n #define IXGBE_NOT_IMPLEMENTED\t\t\t0x7FFFFFFF\n \ndiff --git a/drivers/net/ixgbe/base/ixgbe_type_e610.h b/drivers/net/ixgbe/base/ixgbe_type_e610.h\nnew file mode 100644\nindex 0000000000..a50603d1b7\n--- /dev/null\n+++ b/drivers/net/ixgbe/base/ixgbe_type_e610.h\n@@ -0,0 +1,1682 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2024 Intel Corporation\n+ */\n+\n+#ifndef _IXGBE_TYPE_E610_H_\n+#define _IXGBE_TYPE_E610_H_\n+\n+/* Little Endian defines */\n+#ifndef __le16\n+#define __le16  u16\n+#endif\n+#ifndef __le32\n+#define __le32  u32\n+#endif\n+#ifndef __le64\n+#define __le64  u64\n+#endif\n+\n+/* Generic defines */\n+#ifndef BIT\n+#define BIT(a) (1UL << (a))\n+#endif /* !BIT */\n+#ifndef BIT_ULL\n+#define BIT_ULL(a) (1ULL << (a))\n+#endif /* !BIT_ULL */\n+#ifndef BITS_PER_BYTE\n+#define BITS_PER_BYTE\t8\n+#endif /* !BITS_PER_BYTE */\n+#ifndef DIVIDE_AND_ROUND_UP\n+#define DIVIDE_AND_ROUND_UP(a, b) (((a) + (b) - 1) / (b))\n+#endif /* !DIVIDE_AND_ROUND_UP */\n+\n+#ifndef ROUND_UP\n+/**\n+ * ROUND_UP - round up to next arbitrary multiple (not a power of 2)\n+ * @a: value to round up\n+ * @b: arbitrary multiple\n+ *\n+ * Round up to the next multiple of the arbitrary b.\n+ */\n+#define ROUND_UP(a, b)\t((b) * DIVIDE_AND_ROUND_UP((a), (b)))\n+#endif /* !ROUND_UP */\n+\n+#define MAKEMASK(mask, shift) (mask << shift)\n+\n+#define BYTES_PER_WORD\t2\n+#define BYTES_PER_DWORD\t4\n+\n+#ifndef BITS_PER_LONG\n+#define BITS_PER_LONG\t\t64\n+#endif /* !BITS_PER_LONG */\n+#ifndef BITS_PER_LONG_LONG\n+#define BITS_PER_LONG_LONG\t64\n+#endif /* !BITS_PER_LONG_LONG */\n+#undef GENMASK\n+#define GENMASK(h, l) \\\n+\t(((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h))))\n+#undef GENMASK_ULL\n+#define GENMASK_ULL(h, l) \\\n+\t(((~0ULL) << (l)) & (~0ULL >> (BITS_PER_LONG_LONG - 1 - (h))))\n+\n+/* Data type manipulation macros. */\n+#define HI_DWORD(x)\t((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF))\n+#define LO_DWORD(x)\t((u32)((x) & 0xFFFFFFFF))\n+#define HI_WORD(x)\t((u16)(((x) >> 16) & 0xFFFF))\n+#define LO_WORD(x)\t((u16)((x) & 0xFFFF))\n+#define HI_BYTE(x)\t((u8)(((x) >> 8) & 0xFF))\n+#define LO_BYTE(x)\t((u8)((x) & 0xFF))\n+\n+#define MIN_T(_t, _a, _b)\tmin((_t)(_a), (_t)(_b))\n+\n+#define IS_ASCII(_ch)\t((_ch) < 0x80)\n+\n+#define STRUCT_HACK_VAR_LEN\n+/**\n+ * ixgbe_struct_size - size of struct with C99 flexible array member\n+ * @ptr: pointer to structure\n+ * @field: flexible array member (last member of the structure)\n+ * @num: number of elements of that flexible array member\n+ */\n+#define ixgbe_struct_size(ptr, field, num) \\\n+\t(sizeof(*(ptr)) + sizeof(*(ptr)->field) * (num))\n+\n+/* General E610 defines */\n+#define IXGBE_MAX_VSI\t\t\t768\n+\n+/* Checksum and Shadow RAM pointers */\n+#define E610_SR_SW_CHECKSUM_WORD\t\t0x3F\n+\n+/* General registers */\n+\n+/* Firmware Status Register (GL_FWSTS) */\n+#define GL_FWSTS\t\t\t\t0x00083048 /* Reset Source: POR */\n+#define GL_FWSTS_FWS0B_S\t\t\t0\n+#define GL_FWSTS_FWS0B_M\t\t\tMAKEMASK(0xFF, 0)\n+#define GL_FWSTS_FWROWD_S\t\t\t8\n+#define GL_FWSTS_FWROWD_M\t\t\tBIT(8)\n+#define GL_FWSTS_FWRI_S\t\t\t\t9\n+#define GL_FWSTS_FWRI_M\t\t\t\tBIT(9)\n+#define GL_FWSTS_FWS1B_S\t\t\t16\n+#define GL_FWSTS_FWS1B_M\t\t\tMAKEMASK(0xFF, 16)\n+#define GL_FWSTS_EP_PF0\t\t\t\tBIT(24)\n+#define GL_FWSTS_EP_PF1\t\t\t\tBIT(25)\n+\n+/* Recovery mode values of Firmware Status 1 Byte (FWS1B) bitfield */\n+#define GL_FWSTS_FWS1B_RECOVERY_MODE_CORER_LEGACY  0x0B\n+#define GL_FWSTS_FWS1B_RECOVERY_MODE_GLOBR_LEGACY  0x0C\n+#define GL_FWSTS_FWS1B_RECOVERY_MODE_CORER         0x30\n+#define GL_FWSTS_FWS1B_RECOVERY_MODE_GLOBR         0x31\n+#define GL_FWSTS_FWS1B_RECOVERY_MODE_TRANSITION    0x32\n+#define GL_FWSTS_FWS1B_RECOVERY_MODE_NVM           0x33\n+\n+/* Firmware Status (GL_MNG_FWSM) */\n+#define GL_MNG_FWSM\t\t\t\t0x000B6134 /* Reset Source: POR */\n+#define GL_MNG_FWSM_FW_MODES_S\t\t\t0\n+#define GL_MNG_FWSM_FW_MODES_M\t\t\tMAKEMASK(0x7, 0)\n+#define GL_MNG_FWSM_RSV0_S\t\t\t2\n+#define GL_MNG_FWSM_RSV0_M\t\t\tMAKEMASK(0xFF, 2)\n+#define GL_MNG_FWSM_EEP_RELOAD_IND_S\t\t10\n+#define GL_MNG_FWSM_EEP_RELOAD_IND_M\t\tBIT(10)\n+#define GL_MNG_FWSM_RSV1_S\t\t\t11\n+#define GL_MNG_FWSM_RSV1_M\t\t\tMAKEMASK(0xF, 11)\n+#define GL_MNG_FWSM_RSV2_S\t\t\t15\n+#define GL_MNG_FWSM_RSV2_M\t\t\tBIT(15)\n+#define GL_MNG_FWSM_PCIR_AL_FAILURE_S\t\t16\n+#define GL_MNG_FWSM_PCIR_AL_FAILURE_M\t\tBIT(16)\n+#define GL_MNG_FWSM_POR_AL_FAILURE_S\t\t17\n+#define GL_MNG_FWSM_POR_AL_FAILURE_M\t\tBIT(17)\n+#define GL_MNG_FWSM_RSV3_S\t\t\t18\n+#define GL_MNG_FWSM_RSV3_M\t\t\tBIT(18)\n+#define GL_MNG_FWSM_EXT_ERR_IND_S\t\t19\n+#define GL_MNG_FWSM_EXT_ERR_IND_M\t\tMAKEMASK(0x3F, 19)\n+#define GL_MNG_FWSM_RSV4_S\t\t\t25\n+#define GL_MNG_FWSM_RSV4_M\t\t\tBIT(25)\n+#define GL_MNG_FWSM_RESERVED_11_S\t\t26\n+#define GL_MNG_FWSM_RESERVED_11_M\t\tMAKEMASK(0xF, 26)\n+#define GL_MNG_FWSM_RSV5_S\t\t\t30\n+#define GL_MNG_FWSM_RSV5_M\t\t\tMAKEMASK(0x3, 30)\n+\n+/* Flash Access Register */\n+#define GLNVM_FLA\t\t\t\t0x000B6108 /* Reset Source: POR */\n+#define GLNVM_FLA_LOCKED_S\t\t\t6\n+#define GLNVM_FLA_LOCKED_M\t\t\tBIT(6)\n+\n+/* Admin Command Interface (ACI) registers */\n+#define PF_HIDA(_i)\t\t\t(0x00085000 + ((_i) * 4))\n+#define PF_HIDA_2(_i)\t\t\t(0x00085020 + ((_i) * 4))\n+#define PF_HIBA(_i)\t\t\t(0x00084000 + ((_i) * 4))\n+#define PF_HICR\t\t\t\t0x00082048\n+\n+#define PF_HICR_EN\t\t\tBIT(0)\n+#define PF_HICR_C\t\t\tBIT(1)\n+#define PF_HICR_SV\t\t\tBIT(2)\n+#define PF_HICR_EV\t\t\tBIT(3)\n+\n+#define IXGBE_ACI_DESC_SIZE\t\t32\n+#define IXGBE_ACI_DESC_SIZE_IN_DWORDS\tIXGBE_ACI_DESC_SIZE / BYTES_PER_DWORD\n+\n+#define IXGBE_ACI_MAX_BUFFER_SIZE\t\t4096    /* Size in bytes */\n+#define IXGBE_ACI_DESC_COOKIE_L_DWORD_OFFSET\t3\n+#define IXGBE_ACI_SEND_DELAY_TIME_MS\t\t10\n+#define IXGBE_ACI_SEND_MAX_EXECUTE\t\t3\n+/* [ms] timeout of waiting for sync response */\n+#define IXGBE_ACI_SYNC_RESPONSE_TIMEOUT\t\t100000\n+/* [ms] timeout of waiting for async response */\n+#define IXGBE_ACI_ASYNC_RESPONSE_TIMEOUT\t150000\n+/* [ms] timeout of waiting for resource release */\n+#define IXGBE_ACI_RELEASE_RES_TIMEOUT\t\t10000\n+\n+/* FW defined boundary for a large buffer, 4k >= Large buffer > 512 bytes */\n+#define IXGBE_ACI_LG_BUF\t\t512\n+\n+/* Flags sub-structure\n+ * |0  |1  |2  |3  |4  |5  |6  |7  |8  |9  |10 |11 |12 |13 |14 |15 |\n+ * |DD |CMP|ERR|VFE| * *  RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE |\n+ */\n+\n+/* command flags and offsets */\n+#define IXGBE_ACI_FLAG_DD_S\t0\n+#define IXGBE_ACI_FLAG_CMP_S\t1\n+#define IXGBE_ACI_FLAG_ERR_S\t2\n+#define IXGBE_ACI_FLAG_VFE_S\t3\n+#define IXGBE_ACI_FLAG_LB_S\t9\n+#define IXGBE_ACI_FLAG_RD_S\t10\n+#define IXGBE_ACI_FLAG_VFC_S\t11\n+#define IXGBE_ACI_FLAG_BUF_S\t12\n+#define IXGBE_ACI_FLAG_SI_S\t13\n+#define IXGBE_ACI_FLAG_EI_S\t14\n+#define IXGBE_ACI_FLAG_FE_S\t15\n+\n+#define IXGBE_ACI_FLAG_DD\t\tBIT(IXGBE_ACI_FLAG_DD_S)  /* 0x1    */\n+#define IXGBE_ACI_FLAG_CMP\t\tBIT(IXGBE_ACI_FLAG_CMP_S) /* 0x2    */\n+#define IXGBE_ACI_FLAG_ERR\t\tBIT(IXGBE_ACI_FLAG_ERR_S) /* 0x4    */\n+#define IXGBE_ACI_FLAG_VFE\t\tBIT(IXGBE_ACI_FLAG_VFE_S) /* 0x8    */\n+#define IXGBE_ACI_FLAG_LB\t\tBIT(IXGBE_ACI_FLAG_LB_S)  /* 0x200  */\n+#define IXGBE_ACI_FLAG_RD\t\tBIT(IXGBE_ACI_FLAG_RD_S)  /* 0x400  */\n+#define IXGBE_ACI_FLAG_VFC\t\tBIT(IXGBE_ACI_FLAG_VFC_S) /* 0x800  */\n+#define IXGBE_ACI_FLAG_BUF\t\tBIT(IXGBE_ACI_FLAG_BUF_S) /* 0x1000 */\n+#define IXGBE_ACI_FLAG_SI\t\tBIT(IXGBE_ACI_FLAG_SI_S)  /* 0x2000 */\n+#define IXGBE_ACI_FLAG_EI\t\tBIT(IXGBE_ACI_FLAG_EI_S)  /* 0x4000 */\n+#define IXGBE_ACI_FLAG_FE\t\tBIT(IXGBE_ACI_FLAG_FE_S)  /* 0x8000 */\n+\n+/* Admin Command Interface (ACI) error codes */\n+enum ixgbe_aci_err {\n+\tIXGBE_ACI_RC_OK\t\t\t= 0,  /* Success */\n+\tIXGBE_ACI_RC_EPERM\t\t= 1,  /* Operation not permitted */\n+\tIXGBE_ACI_RC_ENOENT\t\t= 2,  /* No such element */\n+\tIXGBE_ACI_RC_ESRCH\t\t= 3,  /* Bad opcode */\n+\tIXGBE_ACI_RC_EINTR\t\t= 4,  /* Operation interrupted */\n+\tIXGBE_ACI_RC_EIO\t\t= 5,  /* I/O error */\n+\tIXGBE_ACI_RC_ENXIO\t\t= 6,  /* No such resource */\n+\tIXGBE_ACI_RC_E2BIG\t\t= 7,  /* Arg too long */\n+\tIXGBE_ACI_RC_EAGAIN\t\t= 8,  /* Try again */\n+\tIXGBE_ACI_RC_ENOMEM\t\t= 9,  /* Out of memory */\n+\tIXGBE_ACI_RC_EACCES\t\t= 10, /* Permission denied */\n+\tIXGBE_ACI_RC_EFAULT\t\t= 11, /* Bad address */\n+\tIXGBE_ACI_RC_EBUSY\t\t= 12, /* Device or resource busy */\n+\tIXGBE_ACI_RC_EEXIST\t\t= 13, /* Object already exists */\n+\tIXGBE_ACI_RC_EINVAL\t\t= 14, /* Invalid argument */\n+\tIXGBE_ACI_RC_ENOTTY\t\t= 15, /* Not a typewriter */\n+\tIXGBE_ACI_RC_ENOSPC\t\t= 16, /* No space left or allocation failure */\n+\tIXGBE_ACI_RC_ENOSYS\t\t= 17, /* Function not implemented */\n+\tIXGBE_ACI_RC_ERANGE\t\t= 18, /* Parameter out of range */\n+\tIXGBE_ACI_RC_EFLUSHED\t\t= 19, /* Cmd flushed due to prev cmd error */\n+\tIXGBE_ACI_RC_BAD_ADDR\t\t= 20, /* Descriptor contains a bad pointer */\n+\tIXGBE_ACI_RC_EMODE\t\t= 21, /* Op not allowed in current dev mode */\n+\tIXGBE_ACI_RC_EFBIG\t\t= 22, /* File too big */\n+\tIXGBE_ACI_RC_ESBCOMP\t\t= 23, /* SB-IOSF completion unsuccessful */\n+\tIXGBE_ACI_RC_ENOSEC\t\t= 24, /* Missing security manifest */\n+\tIXGBE_ACI_RC_EBADSIG\t\t= 25, /* Bad RSA signature */\n+\tIXGBE_ACI_RC_ESVN\t\t= 26, /* SVN number prohibits this package */\n+\tIXGBE_ACI_RC_EBADMAN\t\t= 27, /* Manifest hash mismatch */\n+\tIXGBE_ACI_RC_EBADBUF\t\t= 28, /* Buffer hash mismatches manifest */\n+\tIXGBE_ACI_RC_EACCES_BMCU\t= 29, /* BMC Update in progress */\n+};\n+\n+/* Admin Command Interface (ACI) opcodes */\n+enum ixgbe_aci_opc {\n+\tixgbe_aci_opc_get_ver\t\t\t\t= 0x0001,\n+\tixgbe_aci_opc_driver_ver\t\t\t= 0x0002,\n+\tixgbe_aci_opc_get_exp_err\t\t\t= 0x0005,\n+\n+\t/* resource ownership */\n+\tixgbe_aci_opc_req_res\t\t\t\t= 0x0008,\n+\tixgbe_aci_opc_release_res\t\t\t= 0x0009,\n+\n+\t/* device/function capabilities */\n+\tixgbe_aci_opc_list_func_caps\t\t\t= 0x000A,\n+\tixgbe_aci_opc_list_dev_caps\t\t\t= 0x000B,\n+\n+\t/* safe disable of RXEN */\n+\tixgbe_aci_opc_disable_rxen\t\t\t= 0x000C,\n+\n+\t/* FW events */\n+\tixgbe_aci_opc_get_fw_event\t\t\t= 0x0014,\n+\n+\t/* PHY commands */\n+\tixgbe_aci_opc_get_phy_caps\t\t\t= 0x0600,\n+\tixgbe_aci_opc_set_phy_cfg\t\t\t= 0x0601,\n+\tixgbe_aci_opc_restart_an\t\t\t= 0x0605,\n+\tixgbe_aci_opc_get_link_status\t\t\t= 0x0607,\n+\tixgbe_aci_opc_set_event_mask\t\t\t= 0x0613,\n+\tixgbe_aci_opc_get_link_topo\t\t\t= 0x06E0,\n+\tixgbe_aci_opc_get_link_topo_pin\t\t\t= 0x06E1,\n+\tixgbe_aci_opc_read_i2c\t\t\t\t= 0x06E2,\n+\tixgbe_aci_opc_write_i2c\t\t\t\t= 0x06E3,\n+\tixgbe_aci_opc_read_mdio\t\t\t\t= 0x06E4,\n+\tixgbe_aci_opc_write_mdio\t\t\t= 0x06E5,\n+\tixgbe_aci_opc_set_gpio_by_func\t\t\t= 0x06E6,\n+\tixgbe_aci_opc_get_gpio_by_func\t\t\t= 0x06E7,\n+\tixgbe_aci_opc_set_gpio\t\t\t\t= 0x06EC,\n+\tixgbe_aci_opc_get_gpio\t\t\t\t= 0x06ED,\n+\tixgbe_aci_opc_sff_eeprom\t\t\t= 0x06EE,\n+\tixgbe_aci_opc_prog_topo_dev_nvm\t\t\t= 0x06F2,\n+\tixgbe_aci_opc_read_topo_dev_nvm\t\t\t= 0x06F3,\n+\n+\t/* NVM commands */\n+\tixgbe_aci_opc_nvm_read\t\t\t\t= 0x0701,\n+\tixgbe_aci_opc_nvm_erase\t\t\t\t= 0x0702,\n+\tixgbe_aci_opc_nvm_write\t\t\t\t= 0x0703,\n+\tixgbe_aci_opc_nvm_cfg_read\t\t\t= 0x0704,\n+\tixgbe_aci_opc_nvm_cfg_write\t\t\t= 0x0705,\n+\tixgbe_aci_opc_nvm_checksum\t\t\t= 0x0706,\n+\tixgbe_aci_opc_nvm_write_activate\t\t= 0x0707,\n+\tixgbe_aci_opc_nvm_sr_dump\t\t\t= 0x0707,\n+\tixgbe_aci_opc_nvm_save_factory_settings\t\t= 0x0708,\n+\tixgbe_aci_opc_nvm_update_empr\t\t\t= 0x0709,\n+\tixgbe_aci_opc_nvm_pkg_data\t\t\t= 0x070A,\n+\tixgbe_aci_opc_nvm_pass_component_tbl\t\t= 0x070B,\n+\tixgbe_aci_opc_nvm_sanitization\t\t\t= 0x070C,\n+\n+\t/* Alternate Structure Commands */\n+\tixgbe_aci_opc_write_alt_direct\t\t\t= 0x0900,\n+\tixgbe_aci_opc_write_alt_indirect\t\t= 0x0901,\n+\tixgbe_aci_opc_read_alt_direct\t\t\t= 0x0902,\n+\tixgbe_aci_opc_read_alt_indirect\t\t\t= 0x0903,\n+\tixgbe_aci_opc_done_alt_write\t\t\t= 0x0904,\n+\tixgbe_aci_opc_clear_port_alt_write\t\t= 0x0906,\n+\n+\t/* debug commands */\n+\tixgbe_aci_opc_debug_dump_internals\t\t= 0xFF08,\n+\n+\t/* SystemDiagnostic commands */\n+\tixgbe_aci_opc_set_health_status_config\t\t= 0xFF20,\n+\tixgbe_aci_opc_get_supported_health_status_codes\t= 0xFF21,\n+\tixgbe_aci_opc_get_health_status\t\t\t= 0xFF22,\n+\tixgbe_aci_opc_clear_health_status\t\t= 0xFF23,\n+\n+};\n+\n+/* This macro is used to generate a compilation error if a structure\n+ * is not exactly the correct length. It gives a divide by zero error if the\n+ * structure is not of the correct size, otherwise it creates an enum that is\n+ * never used.\n+ */\n+#define IXGBE_CHECK_STRUCT_LEN(n, X) enum ixgbe_static_assert_enum_##X \\\n+\t{ ixgbe_static_assert_##X = (n) / ((sizeof(struct X) == (n)) ? 1 : 0) }\n+\n+/* This macro is used to generate a compilation error if a variable-length\n+ * structure is not exactly the correct length assuming a single element of\n+ * the variable-length object as the last element of the structure. It gives\n+ * a divide by zero error if the structure is not of the correct size,\n+ * otherwise it creates an enum that is never used.\n+ */\n+#define IXGBE_CHECK_VAR_LEN_STRUCT_LEN(n, X, T) enum ixgbe_static_assert_enum_##X \\\n+\t{ ixgbe_static_assert_##X = (n) / \\\n+\t  (((sizeof(struct X) + sizeof(T)) == (n)) ? 1 : 0) }\n+\n+/* This macro is used to ensure that parameter structures (i.e. structures\n+ * in the params union member of struct ixgbe_aci_desc) are 16 bytes in length.\n+ *\n+ * NOT intended to be used to check the size of an indirect command/response\n+ * additional data buffer (e.g. struct foo) which should just happen to be 16\n+ * bytes (instead, use IXGBE_CHECK_STRUCT_LEN(16, foo) for that).\n+ */\n+#define IXGBE_CHECK_PARAM_LEN(X)\tIXGBE_CHECK_STRUCT_LEN(16, X)\n+\n+struct ixgbe_aci_cmd_generic {\n+\t__le32 param0;\n+\t__le32 param1;\n+\t__le32 addr_high;\n+\t__le32 addr_low;\n+};\n+\n+IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_generic);\n+\n+/* Get version (direct 0x0001) */\n+struct ixgbe_aci_cmd_get_ver {\n+\t__le32 rom_ver;\n+\t__le32 fw_build;\n+\tu8 fw_branch;\n+\tu8 fw_major;\n+\tu8 fw_minor;\n+\tu8 fw_patch;\n+\tu8 api_branch;\n+\tu8 api_major;\n+\tu8 api_minor;\n+\tu8 api_patch;\n+};\n+\n+IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_get_ver);\n+\n+#define IXGBE_DRV_VER_STR_LEN_E610\t32\n+\n+struct ixgbe_driver_ver {\n+\tu8 major_ver;\n+\tu8 minor_ver;\n+\tu8 build_ver;\n+\tu8 subbuild_ver;\n+\tu8 driver_string[IXGBE_DRV_VER_STR_LEN_E610];\n+};\n+\n+/* Send driver version (indirect 0x0002) */\n+struct ixgbe_aci_cmd_driver_ver {\n+\tu8 major_ver;\n+\tu8 minor_ver;\n+\tu8 build_ver;\n+\tu8 subbuild_ver;\n+\tu8 reserved[4];\n+\t__le32 addr_high;\n+\t__le32 addr_low;\n+};\n+\n+IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_driver_ver);\n+\n+/* Get Expanded Error Code (0x0005, direct) */\n+struct ixgbe_aci_cmd_get_exp_err {\n+\t__le32 reason;\n+#define IXGBE_ACI_EXPANDED_ERROR_NOT_PROVIDED\t0xFFFFFFFF\n+\t__le32 identifier;\n+\tu8 rsvd[8];\n+};\n+\n+IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_get_exp_err);\n+\n+/* FW update timeout definitions are in milliseconds */\n+#define IXGBE_NVM_TIMEOUT\t\t180000\n+\n+enum ixgbe_aci_res_access_type {\n+\tIXGBE_RES_READ = 1,\n+\tIXGBE_RES_WRITE\n+};\n+\n+enum ixgbe_aci_res_ids {\n+\tIXGBE_NVM_RES_ID = 1,\n+\tIXGBE_SPD_RES_ID,\n+\tIXGBE_CHANGE_LOCK_RES_ID,\n+\tIXGBE_GLOBAL_CFG_LOCK_RES_ID\n+};\n+\n+/* Request resource ownership (direct 0x0008)\n+ * Release resource ownership (direct 0x0009)\n+ */\n+struct ixgbe_aci_cmd_req_res {\n+\t__le16 res_id;\n+#define IXGBE_ACI_RES_ID_NVM\t\t1\n+#define IXGBE_ACI_RES_ID_SDP\t\t2\n+#define IXGBE_ACI_RES_ID_CHNG_LOCK\t3\n+#define IXGBE_ACI_RES_ID_GLBL_LOCK\t4\n+\t__le16 access_type;\n+#define IXGBE_ACI_RES_ACCESS_READ\t1\n+#define IXGBE_ACI_RES_ACCESS_WRITE\t2\n+\n+\t/* Upon successful completion, FW writes this value and driver is\n+\t * expected to release resource before timeout. This value is provided\n+\t * in milliseconds.\n+\t */\n+\t__le32 timeout;\n+#define IXGBE_ACI_RES_NVM_READ_DFLT_TIMEOUT_MS\t3000\n+#define IXGBE_ACI_RES_NVM_WRITE_DFLT_TIMEOUT_MS\t180000\n+#define IXGBE_ACI_RES_CHNG_LOCK_DFLT_TIMEOUT_MS\t1000\n+#define IXGBE_ACI_RES_GLBL_LOCK_DFLT_TIMEOUT_MS\t3000\n+\t/* For SDP: pin ID of the SDP */\n+\t__le32 res_number;\n+\t/* Status is only used for IXGBE_ACI_RES_ID_GLBL_LOCK */\n+\t__le16 status;\n+#define IXGBE_ACI_RES_GLBL_SUCCESS\t\t0\n+#define IXGBE_ACI_RES_GLBL_IN_PROG\t\t1\n+#define IXGBE_ACI_RES_GLBL_DONE\t\t\t2\n+\tu8 reserved[2];\n+};\n+\n+IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_req_res);\n+\n+/* Get function capabilities (indirect 0x000A)\n+ * Get device capabilities (indirect 0x000B)\n+ */\n+struct ixgbe_aci_cmd_list_caps {\n+\tu8 cmd_flags;\n+\tu8 pf_index;\n+\tu8 reserved[2];\n+\t__le32 count;\n+\t__le32 addr_high;\n+\t__le32 addr_low;\n+};\n+\n+IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_list_caps);\n+\n+/* Device/Function buffer entry, repeated per reported capability */\n+struct ixgbe_aci_cmd_list_caps_elem {\n+\t__le16 cap;\n+#define IXGBE_ACI_CAPS_VALID_FUNCTIONS\t\t\t0x0005\n+#define IXGBE_ACI_MAX_VALID_FUNCTIONS\t\t\t0x8\n+#define IXGBE_ACI_CAPS_VMDQ\t\t\t\t0x0014\n+#define IXGBE_ACI_CAPS_VSI\t\t\t\t0x0017\n+#define IXGBE_ACI_CAPS_DCB\t\t\t\t0x0018\n+#define IXGBE_ACI_CAPS_RSS\t\t\t\t0x0040\n+#define IXGBE_ACI_CAPS_RXQS\t\t\t\t0x0041\n+#define IXGBE_ACI_CAPS_TXQS\t\t\t\t0x0042\n+#define IXGBE_ACI_CAPS_MSIX\t\t\t\t0x0043\n+#define IXGBE_ACI_CAPS_FD\t\t\t\t0x0045\n+#define IXGBE_ACI_CAPS_1588\t\t\t\t0x0046\n+#define IXGBE_ACI_CAPS_MAX_MTU\t\t\t\t0x0047\n+#define IXGBE_ACI_CAPS_NVM_VER\t\t\t\t0x0048\n+#define IXGBE_ACI_CAPS_OROM_VER\t\t\t\t0x004A\n+#define IXGBE_ACI_CAPS_INLINE_IPSEC\t\t\t0x0070\n+#define IXGBE_ACI_CAPS_NUM_ENABLED_PORTS\t\t0x0072\n+#define IXGBE_ACI_CAPS_PCIE_RESET_AVOIDANCE\t\t0x0076\n+#define IXGBE_ACI_CAPS_POST_UPDATE_RESET_RESTRICT\t0x0077\n+#define IXGBE_ACI_CAPS_NVM_MGMT\t\t\t\t0x0080\n+#define IXGBE_ACI_CAPS_EXT_TOPO_DEV_IMG0\t\t0x0081\n+#define IXGBE_ACI_CAPS_EXT_TOPO_DEV_IMG1\t\t0x0082\n+#define IXGBE_ACI_CAPS_EXT_TOPO_DEV_IMG2\t\t0x0083\n+#define IXGBE_ACI_CAPS_EXT_TOPO_DEV_IMG3\t\t0x0084\n+#define IXGBE_ACI_CAPS_NEXT_CLUSTER_ID\t\t\t0x0096\n+\tu8 major_ver;\n+\tu8 minor_ver;\n+\t/* Number of resources described by this capability */\n+\t__le32 number;\n+\t/* Only meaningful for some types of resources */\n+\t__le32 logical_id;\n+\t/* Only meaningful for some types of resources */\n+\t__le32 phys_id;\n+\t__le64 rsvd1;\n+\t__le64 rsvd2;\n+};\n+\n+IXGBE_CHECK_STRUCT_LEN(32, ixgbe_aci_cmd_list_caps_elem);\n+\n+/* Disable RXEN (direct 0x000C) */\n+struct ixgbe_aci_cmd_disable_rxen {\n+\tu8 lport_num;\n+\tu8 reserved[15];\n+};\n+\n+IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_disable_rxen);\n+\n+/* Get FW Event (indirect 0x0014) */\n+struct ixgbe_aci_cmd_get_fw_event {\n+\t__le16 fw_buf_status;\n+#define IXGBE_ACI_GET_FW_EVENT_STATUS_OBTAINED\tBIT(0)\n+#define IXGBE_ACI_GET_FW_EVENT_STATUS_PENDING\tBIT(1)\n+\tu8 rsvd[14];\n+};\n+\n+IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_get_fw_event);\n+\n+/* Get PHY capabilities (indirect 0x0600) */\n+struct ixgbe_aci_cmd_get_phy_caps {\n+\tu8 lport_num;\n+\tu8 reserved;\n+\t__le16 param0;\n+\t/* 18.0 - Report qualified modules */\n+#define IXGBE_ACI_GET_PHY_RQM\t\tBIT(0)\n+\t/* 18.1 - 18.3 : Report mode\n+\t * 000b - Report topology capabilities, without media\n+\t * 001b - Report topology capabilities, with media\n+\t * 010b - Report Active configuration\n+\t * 011b - Report PHY Type and FEC mode capabilities\n+\t * 100b - Report Default capabilities\n+\t */\n+#define IXGBE_ACI_REPORT_MODE_S\t\t\t1\n+#define IXGBE_ACI_REPORT_MODE_M\t\t\t(7 << IXGBE_ACI_REPORT_MODE_S)\n+#define IXGBE_ACI_REPORT_TOPO_CAP_NO_MEDIA\t0\n+#define IXGBE_ACI_REPORT_TOPO_CAP_MEDIA\t\tBIT(1)\n+#define IXGBE_ACI_REPORT_ACTIVE_CFG\t\tBIT(2)\n+#define IXGBE_ACI_REPORT_DFLT_CFG\t\tBIT(3)\n+\t__le32 reserved1;\n+\t__le32 addr_high;\n+\t__le32 addr_low;\n+};\n+\n+IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_get_phy_caps);\n+\n+/* This is #define of PHY type (Extended):\n+ * The first set of defines is for phy_type_low.\n+ */\n+#define IXGBE_PHY_TYPE_LOW_100BASE_TX\t\tBIT_ULL(0)\n+#define IXGBE_PHY_TYPE_LOW_100M_SGMII\t\tBIT_ULL(1)\n+#define IXGBE_PHY_TYPE_LOW_1000BASE_T\t\tBIT_ULL(2)\n+#define IXGBE_PHY_TYPE_LOW_1000BASE_SX\t\tBIT_ULL(3)\n+#define IXGBE_PHY_TYPE_LOW_1000BASE_LX\t\tBIT_ULL(4)\n+#define IXGBE_PHY_TYPE_LOW_1000BASE_KX\t\tBIT_ULL(5)\n+#define IXGBE_PHY_TYPE_LOW_1G_SGMII\t\tBIT_ULL(6)\n+#define IXGBE_PHY_TYPE_LOW_2500BASE_T\t\tBIT_ULL(7)\n+#define IXGBE_PHY_TYPE_LOW_2500BASE_X\t\tBIT_ULL(8)\n+#define IXGBE_PHY_TYPE_LOW_2500BASE_KX\t\tBIT_ULL(9)\n+#define IXGBE_PHY_TYPE_LOW_5GBASE_T\t\tBIT_ULL(10)\n+#define IXGBE_PHY_TYPE_LOW_5GBASE_KR\t\tBIT_ULL(11)\n+#define IXGBE_PHY_TYPE_LOW_10GBASE_T\t\tBIT_ULL(12)\n+#define IXGBE_PHY_TYPE_LOW_10G_SFI_DA\t\tBIT_ULL(13)\n+#define IXGBE_PHY_TYPE_LOW_10GBASE_SR\t\tBIT_ULL(14)\n+#define IXGBE_PHY_TYPE_LOW_10GBASE_LR\t\tBIT_ULL(15)\n+#define IXGBE_PHY_TYPE_LOW_10GBASE_KR_CR1\tBIT_ULL(16)\n+#define IXGBE_PHY_TYPE_LOW_10G_SFI_AOC_ACC\tBIT_ULL(17)\n+#define IXGBE_PHY_TYPE_LOW_10G_SFI_C2C\t\tBIT_ULL(18)\n+#define IXGBE_PHY_TYPE_LOW_25GBASE_T\t\tBIT_ULL(19)\n+#define IXGBE_PHY_TYPE_LOW_25GBASE_CR\t\tBIT_ULL(20)\n+#define IXGBE_PHY_TYPE_LOW_25GBASE_CR_S\t\tBIT_ULL(21)\n+#define IXGBE_PHY_TYPE_LOW_25GBASE_CR1\t\tBIT_ULL(22)\n+#define IXGBE_PHY_TYPE_LOW_25GBASE_SR\t\tBIT_ULL(23)\n+#define IXGBE_PHY_TYPE_LOW_25GBASE_LR\t\tBIT_ULL(24)\n+#define IXGBE_PHY_TYPE_LOW_25GBASE_KR\t\tBIT_ULL(25)\n+#define IXGBE_PHY_TYPE_LOW_25GBASE_KR_S\t\tBIT_ULL(26)\n+#define IXGBE_PHY_TYPE_LOW_25GBASE_KR1\t\tBIT_ULL(27)\n+#define IXGBE_PHY_TYPE_LOW_25G_AUI_AOC_ACC\tBIT_ULL(28)\n+#define IXGBE_PHY_TYPE_LOW_25G_AUI_C2C\t\tBIT_ULL(29)\n+#define IXGBE_PHY_TYPE_LOW_MAX_INDEX\t\t29\n+/* The second set of defines is for phy_type_high. */\n+#define IXGBE_PHY_TYPE_HIGH_10BASE_T\t\tBIT_ULL(1)\n+#define IXGBE_PHY_TYPE_HIGH_10M_SGMII\t\tBIT_ULL(2)\n+#define IXGBE_PHY_TYPE_HIGH_2500M_SGMII\t\tBIT_ULL(56)\n+#define IXGBE_PHY_TYPE_HIGH_100M_USXGMII\tBIT_ULL(57)\n+#define IXGBE_PHY_TYPE_HIGH_1G_USXGMII\t\tBIT_ULL(58)\n+#define IXGBE_PHY_TYPE_HIGH_2500M_USXGMII\tBIT_ULL(59)\n+#define IXGBE_PHY_TYPE_HIGH_5G_USXGMII\t\tBIT_ULL(60)\n+#define IXGBE_PHY_TYPE_HIGH_10G_USXGMII\t\tBIT_ULL(61)\n+#define IXGBE_PHY_TYPE_HIGH_MAX_INDEX\t\t61\n+\n+struct ixgbe_aci_cmd_get_phy_caps_data {\n+\t__le64 phy_type_low; /* Use values from IXGBE_PHY_TYPE_LOW_* */\n+\t__le64 phy_type_high; /* Use values from IXGBE_PHY_TYPE_HIGH_* */\n+\tu8 caps;\n+#define IXGBE_ACI_PHY_EN_TX_LINK_PAUSE\t\t\tBIT(0)\n+#define IXGBE_ACI_PHY_EN_RX_LINK_PAUSE\t\t\tBIT(1)\n+#define IXGBE_ACI_PHY_LOW_POWER_MODE\t\t\tBIT(2)\n+#define IXGBE_ACI_PHY_EN_LINK\t\t\t\tBIT(3)\n+#define IXGBE_ACI_PHY_AN_MODE\t\t\t\tBIT(4)\n+#define IXGBE_ACI_PHY_EN_MOD_QUAL\t\t\tBIT(5)\n+#define IXGBE_ACI_PHY_EN_LESM\t\t\t\tBIT(6)\n+#define IXGBE_ACI_PHY_EN_AUTO_FEC\t\t\tBIT(7)\n+#define IXGBE_ACI_PHY_CAPS_MASK\t\t\t\tMAKEMASK(0xff, 0)\n+\tu8 low_power_ctrl_an;\n+#define IXGBE_ACI_PHY_EN_D3COLD_LOW_POWER_AUTONEG\tBIT(0)\n+#define IXGBE_ACI_PHY_AN_EN_CLAUSE28\t\t\tBIT(1)\n+#define IXGBE_ACI_PHY_AN_EN_CLAUSE73\t\t\tBIT(2)\n+#define IXGBE_ACI_PHY_AN_EN_CLAUSE37\t\t\tBIT(3)\n+\t__le16 eee_cap;\n+#define IXGBE_ACI_PHY_EEE_EN_100BASE_TX\t\t\tBIT(0)\n+#define IXGBE_ACI_PHY_EEE_EN_1000BASE_T\t\t\tBIT(1)\n+#define IXGBE_ACI_PHY_EEE_EN_10GBASE_T\t\t\tBIT(2)\n+#define IXGBE_ACI_PHY_EEE_EN_1000BASE_KX\t\tBIT(3)\n+#define IXGBE_ACI_PHY_EEE_EN_10GBASE_KR\t\t\tBIT(4)\n+#define IXGBE_ACI_PHY_EEE_EN_25GBASE_KR\t\t\tBIT(5)\n+#define IXGBE_ACI_PHY_EEE_EN_10BASE_T\t\t\tBIT(11)\n+\t__le16 eeer_value;\n+\tu8 phy_id_oui[4]; /* PHY/Module ID connected on the port */\n+\tu8 phy_fw_ver[8];\n+\tu8 link_fec_options;\n+#define IXGBE_ACI_PHY_FEC_10G_KR_40G_KR4_EN\t\tBIT(0)\n+#define IXGBE_ACI_PHY_FEC_10G_KR_40G_KR4_REQ\t\tBIT(1)\n+#define IXGBE_ACI_PHY_FEC_25G_RS_528_REQ\t\tBIT(2)\n+#define IXGBE_ACI_PHY_FEC_25G_KR_REQ\t\t\tBIT(3)\n+#define IXGBE_ACI_PHY_FEC_25G_RS_544_REQ\t\tBIT(4)\n+#define IXGBE_ACI_PHY_FEC_25G_RS_CLAUSE91_EN\t\tBIT(6)\n+#define IXGBE_ACI_PHY_FEC_25G_KR_CLAUSE74_EN\t\tBIT(7)\n+#define IXGBE_ACI_PHY_FEC_MASK\t\t\t\tMAKEMASK(0xdf, 0)\n+\tu8 module_compliance_enforcement;\n+#define IXGBE_ACI_MOD_ENFORCE_STRICT_MODE\t\tBIT(0)\n+\tu8 extended_compliance_code;\n+#define IXGBE_ACI_MODULE_TYPE_TOTAL_BYTE\t\t3\n+\tu8 module_type[IXGBE_ACI_MODULE_TYPE_TOTAL_BYTE];\n+#define IXGBE_ACI_MOD_TYPE_BYTE0_SFP_PLUS\t\t0xA0\n+#define IXGBE_ACI_MOD_TYPE_BYTE0_QSFP_PLUS\t\t0x80\n+#define IXGBE_ACI_MOD_TYPE_IDENT\t\t\t1\n+#define IXGBE_ACI_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE\tBIT(0)\n+#define IXGBE_ACI_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE\tBIT(1)\n+#define IXGBE_ACI_MOD_TYPE_BYTE1_10G_BASE_SR\t\tBIT(4)\n+#define IXGBE_ACI_MOD_TYPE_BYTE1_10G_BASE_LR\t\tBIT(5)\n+#define IXGBE_ACI_MOD_TYPE_BYTE1_10G_BASE_LRM\t\tBIT(6)\n+#define IXGBE_ACI_MOD_TYPE_BYTE1_10G_BASE_ER\t\tBIT(7)\n+#define IXGBE_ACI_MOD_TYPE_BYTE2_SFP_PLUS\t\t0xA0\n+#define IXGBE_ACI_MOD_TYPE_BYTE2_QSFP_PLUS\t\t0x86\n+\tu8 qualified_module_count;\n+\tu8 rsvd2[7];\t/* Bytes 47:41 reserved */\n+#define IXGBE_ACI_QUAL_MOD_COUNT_MAX\t\t\t16\n+\tstruct {\n+\t\tu8 v_oui[3];\n+\t\tu8 rsvd3;\n+\t\tu8 v_part[16];\n+\t\t__le32 v_rev;\n+\t\t__le64 rsvd4;\n+\t} qual_modules[IXGBE_ACI_QUAL_MOD_COUNT_MAX];\n+};\n+\n+IXGBE_CHECK_STRUCT_LEN(560, ixgbe_aci_cmd_get_phy_caps_data);\n+\n+/* Set PHY capabilities (direct 0x0601)\n+ * NOTE: This command must be followed by setup link and restart auto-neg\n+ */\n+struct ixgbe_aci_cmd_set_phy_cfg {\n+\tu8 reserved[8];\n+\t__le32 addr_high;\n+\t__le32 addr_low;\n+};\n+\n+IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_set_phy_cfg);\n+\n+/* Set PHY config command data structure */\n+struct ixgbe_aci_cmd_set_phy_cfg_data {\n+\t__le64 phy_type_low; /* Use values from IXGBE_PHY_TYPE_LOW_* */\n+\t__le64 phy_type_high; /* Use values from IXGBE_PHY_TYPE_HIGH_* */\n+\tu8 caps;\n+#define IXGBE_ACI_PHY_ENA_VALID_MASK\t\tMAKEMASK(0xef, 0)\n+#define IXGBE_ACI_PHY_ENA_TX_PAUSE_ABILITY\tBIT(0)\n+#define IXGBE_ACI_PHY_ENA_RX_PAUSE_ABILITY\tBIT(1)\n+#define IXGBE_ACI_PHY_ENA_LOW_POWER\t\tBIT(2)\n+#define IXGBE_ACI_PHY_ENA_LINK\t\t\tBIT(3)\n+#define IXGBE_ACI_PHY_ENA_AUTO_LINK_UPDT\tBIT(5)\n+#define IXGBE_ACI_PHY_ENA_LESM\t\t\tBIT(6)\n+#define IXGBE_ACI_PHY_ENA_AUTO_FEC\t\tBIT(7)\n+\tu8 low_power_ctrl_an;\n+\t__le16 eee_cap; /* Value from ixgbe_aci_get_phy_caps */\n+\t__le16 eeer_value; /* Use defines from ixgbe_aci_get_phy_caps */\n+\tu8 link_fec_opt; /* Use defines from ixgbe_aci_get_phy_caps */\n+\tu8 module_compliance_enforcement;\n+};\n+\n+IXGBE_CHECK_STRUCT_LEN(24, ixgbe_aci_cmd_set_phy_cfg_data);\n+\n+/* Restart AN command data structure (direct 0x0605)\n+ * Also used for response, with only the lport_num field present.\n+ */\n+struct ixgbe_aci_cmd_restart_an {\n+\tu8 reserved[2];\n+\tu8 cmd_flags;\n+#define IXGBE_ACI_RESTART_AN_LINK_RESTART\tBIT(1)\n+#define IXGBE_ACI_RESTART_AN_LINK_ENABLE\tBIT(2)\n+\tu8 reserved2[13];\n+};\n+\n+IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_restart_an);\n+\n+#pragma pack(1)\n+/* Get link status (indirect 0x0607), also used for Link Status Event */\n+struct ixgbe_aci_cmd_get_link_status {\n+\tu8 reserved[2];\n+\tu8 cmd_flags;\n+#define IXGBE_ACI_LSE_M\t\t\t\t0x3\n+#define IXGBE_ACI_LSE_NOP\t\t\t0x0\n+#define IXGBE_ACI_LSE_DIS\t\t\t0x2\n+#define IXGBE_ACI_LSE_ENA\t\t\t0x3\n+\t/* only response uses this flag */\n+#define IXGBE_ACI_LSE_IS_ENABLED\t\t0x1\n+\tu8 reserved2[5];\n+\t__le32 addr_high;\n+\t__le32 addr_low;\n+};\n+\n+IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_get_link_status);\n+\n+/* Get link status response data structure, also used for Link Status Event */\n+struct ixgbe_aci_cmd_get_link_status_data {\n+\tu8 topo_media_conflict;\n+#define IXGBE_ACI_LINK_TOPO_CONFLICT\t\tBIT(0)\n+#define IXGBE_ACI_LINK_MEDIA_CONFLICT\t\tBIT(1)\n+#define IXGBE_ACI_LINK_TOPO_CORRUPT\t\tBIT(2)\n+#define IXGBE_ACI_LINK_TOPO_UNREACH_PRT\t\tBIT(4)\n+#define IXGBE_ACI_LINK_TOPO_UNDRUTIL_PRT\tBIT(5)\n+#define IXGBE_ACI_LINK_TOPO_UNDRUTIL_MEDIA\tBIT(6)\n+#define IXGBE_ACI_LINK_TOPO_UNSUPP_MEDIA\tBIT(7)\n+\tu8 link_cfg_err;\n+#define IXGBE_ACI_LINK_CFG_ERR\t\t\t\tBIT(0)\n+#define IXGBE_ACI_LINK_CFG_COMPLETED\t\t\tBIT(1)\n+#define IXGBE_ACI_LINK_ACT_PORT_OPT_INVAL\t\tBIT(2)\n+#define IXGBE_ACI_LINK_FEAT_ID_OR_CONFIG_ID_INVAL\tBIT(3)\n+#define IXGBE_ACI_LINK_TOPO_CRITICAL_SDP_ERR\t\tBIT(4)\n+#define IXGBE_ACI_LINK_MODULE_POWER_UNSUPPORTED\t\tBIT(5)\n+#define IXGBE_ACI_LINK_EXTERNAL_PHY_LOAD_FAILURE\tBIT(6)\n+#define IXGBE_ACI_LINK_INVAL_MAX_POWER_LIMIT\t\tBIT(7)\n+\tu8 link_info;\n+#define IXGBE_ACI_LINK_UP\t\tBIT(0)\t/* Link Status */\n+#define IXGBE_ACI_LINK_FAULT\t\tBIT(1)\n+#define IXGBE_ACI_LINK_FAULT_TX\t\tBIT(2)\n+#define IXGBE_ACI_LINK_FAULT_RX\t\tBIT(3)\n+#define IXGBE_ACI_LINK_FAULT_REMOTE\tBIT(4)\n+#define IXGBE_ACI_LINK_UP_PORT\t\tBIT(5)\t/* External Port Link Status */\n+#define IXGBE_ACI_MEDIA_AVAILABLE\tBIT(6)\n+#define IXGBE_ACI_SIGNAL_DETECT\t\tBIT(7)\n+\tu8 an_info;\n+#define IXGBE_ACI_AN_COMPLETED\t\tBIT(0)\n+#define IXGBE_ACI_LP_AN_ABILITY\t\tBIT(1)\n+#define IXGBE_ACI_PD_FAULT\t\tBIT(2)\t/* Parallel Detection Fault */\n+#define IXGBE_ACI_FEC_EN\t\tBIT(3)\n+#define IXGBE_ACI_PHY_LOW_POWER\t\tBIT(4)\t/* Low Power State */\n+#define IXGBE_ACI_LINK_PAUSE_TX\t\tBIT(5)\n+#define IXGBE_ACI_LINK_PAUSE_RX\t\tBIT(6)\n+#define IXGBE_ACI_QUALIFIED_MODULE\tBIT(7)\n+\tu8 ext_info;\n+#define IXGBE_ACI_LINK_PHY_TEMP_ALARM\tBIT(0)\n+#define IXGBE_ACI_LINK_EXCESSIVE_ERRORS\tBIT(1)\t/* Excessive Link Errors */\n+\t/* Port Tx Suspended */\n+#define IXGBE_ACI_LINK_TX_S\t\t2\n+#define IXGBE_ACI_LINK_TX_M\t\t(0x03 << IXGBE_ACI_LINK_TX_S)\n+#define IXGBE_ACI_LINK_TX_ACTIVE\t0\n+#define IXGBE_ACI_LINK_TX_DRAINED\t1\n+#define IXGBE_ACI_LINK_TX_FLUSHED\t3\n+\tu8 lb_status;\n+#define IXGBE_ACI_LINK_LB_PHY_LCL\tBIT(0)\n+#define IXGBE_ACI_LINK_LB_PHY_RMT\tBIT(1)\n+#define IXGBE_ACI_LINK_LB_MAC_LCL\tBIT(2)\n+#define IXGBE_ACI_LINK_LB_PHY_IDX_S\t3\n+#define IXGBE_ACI_LINK_LB_PHY_IDX_M\t(0x7 << IXGBE_ACI_LB_PHY_IDX_S)\n+\t__le16 max_frame_size;\n+\tu8 cfg;\n+#define IXGBE_ACI_LINK_25G_KR_FEC_EN\t\tBIT(0)\n+#define IXGBE_ACI_LINK_25G_RS_528_FEC_EN\tBIT(1)\n+#define IXGBE_ACI_LINK_25G_RS_544_FEC_EN\tBIT(2)\n+#define IXGBE_ACI_FEC_MASK\t\t\tMAKEMASK(0x7, 0)\n+\t/* Pacing Config */\n+#define IXGBE_ACI_CFG_PACING_S\t\t3\n+#define IXGBE_ACI_CFG_PACING_M\t\t(0xF << IXGBE_ACI_CFG_PACING_S)\n+#define IXGBE_ACI_CFG_PACING_TYPE_M\tBIT(7)\n+#define IXGBE_ACI_CFG_PACING_TYPE_AVG\t0\n+#define IXGBE_ACI_CFG_PACING_TYPE_FIXED\tIXGBE_ACI_CFG_PACING_TYPE_M\n+\t/* External Device Power Ability */\n+\tu8 power_desc;\n+#define IXGBE_ACI_PWR_CLASS_M\t\t\t0x3F\n+#define IXGBE_ACI_LINK_PWR_BASET_LOW_HIGH\t0\n+#define IXGBE_ACI_LINK_PWR_BASET_HIGH\t\t1\n+#define IXGBE_ACI_LINK_PWR_QSFP_CLASS_1\t\t0\n+#define IXGBE_ACI_LINK_PWR_QSFP_CLASS_2\t\t1\n+#define IXGBE_ACI_LINK_PWR_QSFP_CLASS_3\t\t2\n+#define IXGBE_ACI_LINK_PWR_QSFP_CLASS_4\t\t3\n+\t__le16 link_speed;\n+#define IXGBE_ACI_LINK_SPEED_M\t\t\t0x7FF\n+#define IXGBE_ACI_LINK_SPEED_10MB\t\tBIT(0)\n+#define IXGBE_ACI_LINK_SPEED_100MB\t\tBIT(1)\n+#define IXGBE_ACI_LINK_SPEED_1000MB\t\tBIT(2)\n+#define IXGBE_ACI_LINK_SPEED_2500MB\t\tBIT(3)\n+#define IXGBE_ACI_LINK_SPEED_5GB\t\tBIT(4)\n+#define IXGBE_ACI_LINK_SPEED_10GB\t\tBIT(5)\n+#define IXGBE_ACI_LINK_SPEED_20GB\t\tBIT(6)\n+#define IXGBE_ACI_LINK_SPEED_25GB\t\tBIT(7)\n+#define IXGBE_ACI_LINK_SPEED_40GB\t\tBIT(8)\n+#define IXGBE_ACI_LINK_SPEED_50GB\t\tBIT(9)\n+#define IXGBE_ACI_LINK_SPEED_100GB\t\tBIT(10)\n+#define IXGBE_ACI_LINK_SPEED_200GB\t\tBIT(11)\n+#define IXGBE_ACI_LINK_SPEED_UNKNOWN\t\tBIT(15)\n+\t__le16 reserved3; /* Aligns next field to 8-byte boundary */\n+\tu8 ext_fec_status;\n+#define IXGBE_ACI_LINK_RS_272_FEC_EN\tBIT(0) /* RS 272 FEC enabled */\n+\tu8 reserved4;\n+\t__le64 phy_type_low; /* Use values from IXGBE_PHY_TYPE_LOW_* */\n+\t__le64 phy_type_high; /* Use values from IXGBE_PHY_TYPE_HIGH_* */\n+\t/* Get link status version 2 link partner data */\n+\t__le64 lp_phy_type_low; /* Use values from IXGBE_PHY_TYPE_LOW_* */\n+\t__le64 lp_phy_type_high; /* Use values from IXGBE_PHY_TYPE_HIGH_* */\n+\tu8 lp_fec_adv;\n+#define IXGBE_ACI_LINK_LP_10G_KR_FEC_CAP\tBIT(0)\n+#define IXGBE_ACI_LINK_LP_25G_KR_FEC_CAP\tBIT(1)\n+#define IXGBE_ACI_LINK_LP_RS_528_FEC_CAP\tBIT(2)\n+#define IXGBE_ACI_LINK_LP_50G_KR_272_FEC_CAP\tBIT(3)\n+#define IXGBE_ACI_LINK_LP_100G_KR_272_FEC_CAP\tBIT(4)\n+#define IXGBE_ACI_LINK_LP_200G_KR_272_FEC_CAP\tBIT(5)\n+\tu8 lp_fec_req;\n+#define IXGBE_ACI_LINK_LP_10G_KR_FEC_REQ\tBIT(0)\n+#define IXGBE_ACI_LINK_LP_25G_KR_FEC_REQ\tBIT(1)\n+#define IXGBE_ACI_LINK_LP_RS_528_FEC_REQ\tBIT(2)\n+#define IXGBE_ACI_LINK_LP_KR_272_FEC_REQ\tBIT(3)\n+\tu8 lp_flowcontrol;\n+#define IXGBE_ACI_LINK_LP_PAUSE_ADV\t\tBIT(0)\n+#define IXGBE_ACI_LINK_LP_ASM_DIR_ADV\t\tBIT(1)\n+\tu8 reserved5[5];\n+};\n+#pragma pack()\n+\n+IXGBE_CHECK_STRUCT_LEN(56, ixgbe_aci_cmd_get_link_status_data);\n+\n+/* Set event mask command (direct 0x0613) */\n+struct ixgbe_aci_cmd_set_event_mask {\n+\tu8\treserved[8];\n+\t__le16\tevent_mask;\n+#define IXGBE_ACI_LINK_EVENT_UPDOWN\t\tBIT(1)\n+#define IXGBE_ACI_LINK_EVENT_MEDIA_NA\t\tBIT(2)\n+#define IXGBE_ACI_LINK_EVENT_LINK_FAULT\t\tBIT(3)\n+#define IXGBE_ACI_LINK_EVENT_PHY_TEMP_ALARM\tBIT(4)\n+#define IXGBE_ACI_LINK_EVENT_EXCESSIVE_ERRORS\tBIT(5)\n+#define IXGBE_ACI_LINK_EVENT_SIGNAL_DETECT\tBIT(6)\n+#define IXGBE_ACI_LINK_EVENT_AN_COMPLETED\tBIT(7)\n+#define IXGBE_ACI_LINK_EVENT_MODULE_QUAL_FAIL\tBIT(8)\n+#define IXGBE_ACI_LINK_EVENT_PORT_TX_SUSPENDED\tBIT(9)\n+#define IXGBE_ACI_LINK_EVENT_TOPO_CONFLICT\tBIT(10)\n+#define IXGBE_ACI_LINK_EVENT_MEDIA_CONFLICT\tBIT(11)\n+#define IXGBE_ACI_LINK_EVENT_PHY_FW_LOAD_FAIL\tBIT(12)\n+\tu8\treserved1[6];\n+};\n+\n+IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_set_event_mask);\n+\n+struct ixgbe_aci_cmd_link_topo_params {\n+\tu8 lport_num;\n+\tu8 lport_num_valid;\n+#define IXGBE_ACI_LINK_TOPO_PORT_NUM_VALID\tBIT(0)\n+\tu8 node_type_ctx;\n+#define IXGBE_ACI_LINK_TOPO_NODE_TYPE_S\t\t0\n+#define IXGBE_ACI_LINK_TOPO_NODE_TYPE_M\t\t(0xF << IXGBE_ACI_LINK_TOPO_NODE_TYPE_S)\n+#define IXGBE_ACI_LINK_TOPO_NODE_TYPE_PHY\t0\n+#define IXGBE_ACI_LINK_TOPO_NODE_TYPE_GPIO_CTRL\t1\n+#define IXGBE_ACI_LINK_TOPO_NODE_TYPE_MUX_CTRL\t2\n+#define IXGBE_ACI_LINK_TOPO_NODE_TYPE_LED_CTRL\t3\n+#define IXGBE_ACI_LINK_TOPO_NODE_TYPE_LED\t4\n+#define IXGBE_ACI_LINK_TOPO_NODE_TYPE_THERMAL\t5\n+#define IXGBE_ACI_LINK_TOPO_NODE_TYPE_CAGE\t6\n+#define IXGBE_ACI_LINK_TOPO_NODE_TYPE_MEZZ\t7\n+#define IXGBE_ACI_LINK_TOPO_NODE_TYPE_ID_EEPROM\t8\n+#define IXGBE_ACI_LINK_TOPO_NODE_TYPE_GPS\t11\n+#define IXGBE_ACI_LINK_TOPO_NODE_CTX_S\t\t4\n+#define IXGBE_ACI_LINK_TOPO_NODE_CTX_M\t\t\\\n+\t\t\t\t(0xF << IXGBE_ACI_LINK_TOPO_NODE_CTX_S)\n+#define IXGBE_ACI_LINK_TOPO_NODE_CTX_GLOBAL\t\t\t0\n+#define IXGBE_ACI_LINK_TOPO_NODE_CTX_BOARD\t\t\t1\n+#define IXGBE_ACI_LINK_TOPO_NODE_CTX_PORT\t\t\t2\n+#define IXGBE_ACI_LINK_TOPO_NODE_CTX_NODE\t\t\t3\n+#define IXGBE_ACI_LINK_TOPO_NODE_CTX_NODE_HANDLE\t\t4\n+#define IXGBE_ACI_LINK_TOPO_NODE_CTX_DIRECT_BUS_ACCESS\t\t5\n+#define IXGBE_ACI_LINK_TOPO_NODE_CTX_NODE_HANDLE_BUS_ADDRESS\t6\n+\tu8 index;\n+};\n+\n+IXGBE_CHECK_STRUCT_LEN(4, ixgbe_aci_cmd_link_topo_params);\n+\n+struct ixgbe_aci_cmd_link_topo_addr {\n+\tstruct ixgbe_aci_cmd_link_topo_params topo_params;\n+\t__le16 handle;\n+#define IXGBE_ACI_LINK_TOPO_HANDLE_S\t0\n+#define IXGBE_ACI_LINK_TOPO_HANDLE_M\t(0x3FF << IXGBE_ACI_LINK_TOPO_HANDLE_S)\n+/* Used to decode the handle field */\n+#define IXGBE_ACI_LINK_TOPO_HANDLE_BRD_TYPE_M\t\tBIT(9)\n+#define IXGBE_ACI_LINK_TOPO_HANDLE_BRD_TYPE_LOM\t\tBIT(9)\n+#define IXGBE_ACI_LINK_TOPO_HANDLE_BRD_TYPE_MEZZ\t0\n+#define IXGBE_ACI_LINK_TOPO_HANDLE_NODE_S\t\t0\n+/* In case of a Mezzanine type */\n+#define IXGBE_ACI_LINK_TOPO_HANDLE_MEZZ_NODE_M\t\\\n+\t\t\t\t(0x3F << IXGBE_ACI_LINK_TOPO_HANDLE_NODE_S)\n+#define IXGBE_ACI_LINK_TOPO_HANDLE_MEZZ_S\t6\n+#define IXGBE_ACI_LINK_TOPO_HANDLE_MEZZ_M\t\\\n+\t\t\t\t(0x7 << IXGBE_ACI_LINK_TOPO_HANDLE_MEZZ_S)\n+/* In case of a LOM type */\n+#define IXGBE_ACI_LINK_TOPO_HANDLE_LOM_NODE_M\t\\\n+\t\t\t\t(0x1FF << IXGBE_ACI_LINK_TOPO_HANDLE_NODE_S)\n+};\n+\n+IXGBE_CHECK_STRUCT_LEN(6, ixgbe_aci_cmd_link_topo_addr);\n+\n+/* Get Link Topology Handle (direct, 0x06E0) */\n+struct ixgbe_aci_cmd_get_link_topo {\n+\tstruct ixgbe_aci_cmd_link_topo_addr addr;\n+\tu8 node_part_num;\n+#define IXGBE_ACI_GET_LINK_TOPO_NODE_NR_PCA9575\t\t0x21\n+#define IXGBE_ACI_GET_LINK_TOPO_NODE_NR_GEN_GPS\t\t0x48\n+#define IXGBE_ACI_GET_LINK_TOPO_NODE_NR_E610_PTC\t0x49\n+\tu8 rsvd[9];\n+};\n+\n+IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_get_link_topo);\n+\n+/* Get Link Topology Pin (direct, 0x06E1) */\n+struct ixgbe_aci_cmd_get_link_topo_pin {\n+\tstruct ixgbe_aci_cmd_link_topo_addr addr;\n+\tu8 input_io_params;\n+#define IXGBE_ACI_LINK_TOPO_INPUT_IO_FUNC_S\t0\n+#define IXGBE_ACI_LINK_TOPO_INPUT_IO_FUNC_M\t\\\n+\t\t\t\t(0x1F << IXGBE_ACI_LINK_TOPO_INPUT_IO_FUNC_S)\n+#define IXGBE_ACI_LINK_TOPO_IO_FUNC_GPIO\t0\n+#define IXGBE_ACI_LINK_TOPO_IO_FUNC_RESET_N\t1\n+#define IXGBE_ACI_LINK_TOPO_IO_FUNC_INT_N\t2\n+#define IXGBE_ACI_LINK_TOPO_IO_FUNC_PRESENT_N\t3\n+#define IXGBE_ACI_LINK_TOPO_IO_FUNC_TX_DIS\t4\n+#define IXGBE_ACI_LINK_TOPO_IO_FUNC_MODSEL_N\t5\n+#define IXGBE_ACI_LINK_TOPO_IO_FUNC_LPMODE\t6\n+#define IXGBE_ACI_LINK_TOPO_IO_FUNC_TX_FAULT\t7\n+#define IXGBE_ACI_LINK_TOPO_IO_FUNC_RX_LOSS\t8\n+#define IXGBE_ACI_LINK_TOPO_IO_FUNC_RS0\t\t9\n+#define IXGBE_ACI_LINK_TOPO_IO_FUNC_RS1\t\t10\n+#define IXGBE_ACI_LINK_TOPO_IO_FUNC_EEPROM_WP\t11\n+/* 12 repeats intentionally due to two different uses depending on context */\n+#define IXGBE_ACI_LINK_TOPO_IO_FUNC_LED\t\t12\n+#define IXGBE_ACI_LINK_TOPO_IO_FUNC_RED_LED\t12\n+#define IXGBE_ACI_LINK_TOPO_IO_FUNC_GREEN_LED\t13\n+#define IXGBE_ACI_LINK_TOPO_IO_FUNC_BLUE_LED\t14\n+#define IXGBE_ACI_LINK_TOPO_INPUT_IO_TYPE_S\t5\n+#define IXGBE_ACI_LINK_TOPO_INPUT_IO_TYPE_M\t\\\n+\t\t\t(0x7 << IXGBE_ACI_LINK_TOPO_INPUT_IO_TYPE_S)\n+#define IXGBE_ACI_LINK_TOPO_INPUT_IO_TYPE_GPIO\t3\n+/* Use IXGBE_ACI_LINK_TOPO_NODE_TYPE_* for the type values */\n+\tu8 output_io_params;\n+#define IXGBE_ACI_LINK_TOPO_OUTPUT_IO_FUNC_S\t0\n+#define IXGBE_ACI_LINK_TOPO_OUTPUT_IO_FUNC_M\t\\\n+\t\t\t(0x1F << \\ IXGBE_ACI_LINK_TOPO_INPUT_IO_FUNC_NUM_S)\n+/* Use IXGBE_ACI_LINK_TOPO_IO_FUNC_* for the non-numerical options */\n+#define IXGBE_ACI_LINK_TOPO_OUTPUT_IO_TYPE_S\t5\n+#define IXGBE_ACI_LINK_TOPO_OUTPUT_IO_TYPE_M\t\\\n+\t\t\t(0x7 << IXGBE_ACI_LINK_TOPO_INPUT_IO_TYPE_S)\n+/* Use IXGBE_ACI_LINK_TOPO_NODE_TYPE_* for the type values */\n+\tu8 output_io_flags;\n+#define IXGBE_ACI_LINK_TOPO_OUTPUT_SPEED_S\t0\n+#define IXGBE_ACI_LINK_TOPO_OUTPUT_SPEED_M\t\\\n+\t\t\t(0x7 << IXGBE_ACI_LINK_TOPO_OUTPUT_SPEED_S)\n+#define IXGBE_ACI_LINK_TOPO_OUTPUT_INT_S\t3\n+#define IXGBE_ACI_LINK_TOPO_OUTPUT_INT_M\t\\\n+\t\t\t(0x3 << IXGBE_ACI_LINK_TOPO_OUTPUT_INT_S)\n+#define IXGBE_ACI_LINK_TOPO_OUTPUT_POLARITY\tBIT(5)\n+#define IXGBE_ACI_LINK_TOPO_OUTPUT_VALUE\tBIT(6)\n+#define IXGBE_ACI_LINK_TOPO_OUTPUT_DRIVEN\tBIT(7)\n+\tu8 rsvd[7];\n+};\n+\n+IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_get_link_topo_pin);\n+\n+/* Read/Write I2C (direct, 0x06E2/0x06E3) */\n+struct ixgbe_aci_cmd_i2c {\n+\tstruct ixgbe_aci_cmd_link_topo_addr topo_addr;\n+\t__le16 i2c_addr;\n+\tu8 i2c_params;\n+#define IXGBE_ACI_I2C_DATA_SIZE_S\t\t0\n+#define IXGBE_ACI_I2C_DATA_SIZE_M\t\t(0xF << IXGBE_ACI_I2C_DATA_SIZE_S)\n+#define IXGBE_ACI_I2C_ADDR_TYPE_M\t\tBIT(4)\n+#define IXGBE_ACI_I2C_ADDR_TYPE_7BIT\t\t0\n+#define IXGBE_ACI_I2C_ADDR_TYPE_10BIT\t\tIXGBE_ACI_I2C_ADDR_TYPE_M\n+#define IXGBE_ACI_I2C_DATA_OFFSET_S\t\t5\n+#define IXGBE_ACI_I2C_DATA_OFFSET_M\t\t(0x3 << IXGBE_ACI_I2C_DATA_OFFSET_S)\n+#define IXGBE_ACI_I2C_USE_REPEATED_START\tBIT(7)\n+\tu8 rsvd;\n+\t__le16 i2c_bus_addr;\n+#define IXGBE_ACI_I2C_ADDR_7BIT_MASK\t\t0x7F\n+#define IXGBE_ACI_I2C_ADDR_10BIT_MASK\t\t0x3FF\n+\tu8 i2c_data[4]; /* Used only by write command, reserved in read. */\n+};\n+\n+IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_i2c);\n+\n+/* Read I2C Response (direct, 0x06E2) */\n+struct ixgbe_aci_cmd_read_i2c_resp {\n+\tu8 i2c_data[16];\n+};\n+\n+IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_read_i2c_resp);\n+\n+/* Read/Write MDIO (direct, 0x06E4/0x06E5) */\n+struct ixgbe_aci_cmd_mdio {\n+\tstruct ixgbe_aci_cmd_link_topo_addr topo_addr;\n+\tu8 mdio_device_addr;\n+#define IXGBE_ACI_MDIO_DEV_S\t\t0\n+#define IXGBE_ACI_MDIO_DEV_M\t\t(0x1F << IXGBE_ACI_MDIO_DEV_S)\n+#define IXGBE_ACI_MDIO_CLAUSE_22\tBIT(5)\n+#define IXGBE_ACI_MDIO_CLAUSE_45\tBIT(6)\n+\tu8 mdio_bus_address;\n+#define IXGBE_ACI_MDIO_BUS_ADDR_S 0\n+#define IXGBE_ACI_MDIO_BUS_ADDR_M (0x1F << IXGBE_ACI_MDIO_BUS_ADDR_S)\n+\t__le16 offset;\n+\t__le16 data; /* Input in write cmd, output in read cmd. */\n+\tu8 rsvd1[4];\n+};\n+\n+IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_mdio);\n+\n+/* Set/Get GPIO By Function (direct, 0x06E6/0x06E7) */\n+struct ixgbe_aci_cmd_gpio_by_func {\n+\tstruct ixgbe_aci_cmd_link_topo_addr topo_addr;\n+\tu8 io_func_num;\n+#define IXGBE_ACI_GPIO_FUNC_S\t0\n+#define IXGBE_ACI_GPIO_FUNC_M\t(0x1F << IXGBE_ACI_GPIO_IO_FUNC_NUM_S)\n+\tu8 io_value; /* Input in write cmd, output in read cmd. */\n+#define IXGBE_ACI_GPIO_ON\tBIT(0)\n+#define IXGBE_ACI_GPIO_OFF\t0\n+\tu8 rsvd[8];\n+};\n+\n+IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_gpio_by_func);\n+\n+/* Set/Get GPIO (direct, 0x06EC/0x06ED) */\n+struct ixgbe_aci_cmd_gpio {\n+\t__le16 gpio_ctrl_handle;\n+#define IXGBE_ACI_GPIO_HANDLE_S\t0\n+#define IXGBE_ACI_GPIO_HANDLE_M\t(0x3FF << IXGBE_ACI_GPIO_HANDLE_S)\n+\tu8 gpio_num;\n+\tu8 gpio_val;\n+\tu8 rsvd[12];\n+};\n+\n+IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_gpio);\n+\n+/* Read/Write SFF EEPROM command (indirect 0x06EE) */\n+struct ixgbe_aci_cmd_sff_eeprom {\n+\tu8 lport_num;\n+\tu8 lport_num_valid;\n+#define IXGBE_ACI_SFF_PORT_NUM_VALID\t\tBIT(0)\n+\t__le16 i2c_bus_addr;\n+#define IXGBE_ACI_SFF_I2CBUS_7BIT_M\t\t0x7F\n+#define IXGBE_ACI_SFF_I2CBUS_10BIT_M\t\t0x3FF\n+#define IXGBE_ACI_SFF_I2CBUS_TYPE_M\t\tBIT(10)\n+#define IXGBE_ACI_SFF_I2CBUS_TYPE_7BIT\t\t0\n+#define IXGBE_ACI_SFF_I2CBUS_TYPE_10BIT\t\tIXGBE_ACI_SFF_I2CBUS_TYPE_M\n+#define IXGBE_ACI_SFF_PAGE_BANK_CTRL_S\t\t11\n+#define IXGBE_ACI_SFF_PAGE_BANK_CTRL_M\t\t(0x3 << IXGBE_ACI_SFF_PAGE_BANK_CTRL_S)\n+#define IXGBE_ACI_SFF_NO_PAGE_BANK_UPDATE\t0\n+#define IXGBE_ACI_SFF_UPDATE_PAGE\t\t1\n+#define IXGBE_ACI_SFF_UPDATE_BANK\t\t2\n+#define IXGBE_ACI_SFF_UPDATE_PAGE_BANK\t\t3\n+#define IXGBE_ACI_SFF_IS_WRITE\t\t\tBIT(15)\n+\t__le16 i2c_offset;\n+\tu8 module_bank;\n+\tu8 module_page;\n+\t__le32 addr_high;\n+\t__le32 addr_low;\n+};\n+\n+IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_sff_eeprom);\n+\n+/* Program Topology Device NVM (direct, 0x06F2) */\n+struct ixgbe_aci_cmd_prog_topo_dev_nvm {\n+\tstruct ixgbe_aci_cmd_link_topo_params topo_params;\n+\tu8 rsvd[12];\n+};\n+\n+IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_prog_topo_dev_nvm);\n+\n+/* Read Topology Device NVM (direct, 0x06F3) */\n+struct ixgbe_aci_cmd_read_topo_dev_nvm {\n+\tstruct ixgbe_aci_cmd_link_topo_params topo_params;\n+\t__le32 start_address;\n+#define IXGBE_ACI_READ_TOPO_DEV_NVM_DATA_READ_SIZE 8\n+\tu8 data_read[IXGBE_ACI_READ_TOPO_DEV_NVM_DATA_READ_SIZE];\n+};\n+\n+IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_read_topo_dev_nvm);\n+\n+/* NVM Read command (indirect 0x0701)\n+ * NVM Erase commands (direct 0x0702)\n+ * NVM Write commands (indirect 0x0703)\n+ * NVM Write Activate commands (direct 0x0707)\n+ * NVM Shadow RAM Dump commands (direct 0x0707)\n+ */\n+struct ixgbe_aci_cmd_nvm {\n+#define IXGBE_ACI_NVM_MAX_OFFSET\t0xFFFFFF\n+\t__le16 offset_low;\n+\tu8 offset_high; /* For Write Activate offset_high is used as flags2 */\n+\tu8 cmd_flags;\n+#define IXGBE_ACI_NVM_LAST_CMD\t\tBIT(0)\n+#define IXGBE_ACI_NVM_PCIR_REQ\t\tBIT(0)\t/* Used by NVM Write reply */\n+#define IXGBE_ACI_NVM_PRESERVATION_S\t1 /* Used by NVM Write Activate only */\n+#define IXGBE_ACI_NVM_PRESERVATION_M\t(3 << IXGBE_ACI_NVM_PRESERVATION_S)\n+#define IXGBE_ACI_NVM_NO_PRESERVATION\t(0 << IXGBE_ACI_NVM_PRESERVATION_S)\n+#define IXGBE_ACI_NVM_PRESERVE_ALL\tBIT(1)\n+#define IXGBE_ACI_NVM_FACTORY_DEFAULT\t(2 << IXGBE_ACI_NVM_PRESERVATION_S)\n+#define IXGBE_ACI_NVM_PRESERVE_SELECTED\t(3 << IXGBE_ACI_NVM_PRESERVATION_S)\n+#define IXGBE_ACI_NVM_ACTIV_SEL_NVM\tBIT(3) /* Write Activate/SR Dump only */\n+#define IXGBE_ACI_NVM_ACTIV_SEL_OROM\tBIT(4)\n+#define IXGBE_ACI_NVM_ACTIV_SEL_NETLIST\tBIT(5)\n+#define IXGBE_ACI_NVM_SPECIAL_UPDATE\tBIT(6)\n+#define IXGBE_ACI_NVM_REVERT_LAST_ACTIV\tBIT(6) /* Write Activate only */\n+#define IXGBE_ACI_NVM_ACTIV_SEL_MASK\tMAKEMASK(0x7, 3)\n+#define IXGBE_ACI_NVM_FLASH_ONLY\t\tBIT(7)\n+#define IXGBE_ACI_NVM_RESET_LVL_M\t\tMAKEMASK(0x3, 0) /* Write reply only */\n+#define IXGBE_ACI_NVM_POR_FLAG\t\t0\n+#define IXGBE_ACI_NVM_PERST_FLAG\t1\n+#define IXGBE_ACI_NVM_EMPR_FLAG\t\t2\n+#define IXGBE_ACI_NVM_EMPR_ENA\t\tBIT(0) /* Write Activate reply only */\n+\t/* For Write Activate, several flags are sent as part of a separate\n+\t * flags2 field using a separate byte. For simplicity of the software\n+\t * interface, we pass the flags as a 16 bit value so these flags are\n+\t * all offset by 8 bits\n+\t */\n+#define IXGBE_ACI_NVM_ACTIV_REQ_EMPR\tBIT(8) /* NVM Write Activate only */\n+\t__le16 module_typeid;\n+\t__le16 length;\n+#define IXGBE_ACI_NVM_ERASE_LEN\t0xFFFF\n+\t__le32 addr_high;\n+\t__le32 addr_low;\n+};\n+\n+/* NVM Module_Type ID, needed offset and read_len for struct ixgbe_aci_cmd_nvm. */\n+#define IXGBE_ACI_NVM_START_POINT\t\t0\n+\n+IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_nvm);\n+\n+/* Used for 0x0704 as well as for 0x0705 commands */\n+struct ixgbe_aci_cmd_nvm_cfg {\n+\tu8\tcmd_flags;\n+#define IXGBE_ACI_ANVM_MULTIPLE_ELEMS\tBIT(0)\n+#define IXGBE_ACI_ANVM_IMMEDIATE_FIELD\tBIT(1)\n+#define IXGBE_ACI_ANVM_NEW_CFG\t\tBIT(2)\n+\tu8\treserved;\n+\t__le16 count;\n+\t__le16 id;\n+\tu8 reserved1[2];\n+\t__le32 addr_high;\n+\t__le32 addr_low;\n+};\n+\n+IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_nvm_cfg);\n+\n+/* NVM Checksum Command (direct, 0x0706) */\n+struct ixgbe_aci_cmd_nvm_checksum {\n+\tu8 flags;\n+#define IXGBE_ACI_NVM_CHECKSUM_VERIFY\tBIT(0)\n+#define IXGBE_ACI_NVM_CHECKSUM_RECALC\tBIT(1)\n+\tu8 rsvd;\n+\t__le16 checksum; /* Used only by response */\n+#define IXGBE_ACI_NVM_CHECKSUM_CORRECT\t0xBABA\n+\tu8 rsvd2[12];\n+};\n+\n+IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_nvm_checksum);\n+\n+/* Used for NVM Sanitization command - 0x070C */\n+struct ixgbe_aci_cmd_nvm_sanitization {\n+\tu8 cmd_flags;\n+#define IXGBE_ACI_SANITIZE_REQ_READ\t\t\t0\n+#define IXGBE_ACI_SANITIZE_REQ_OPERATE\t\t\tBIT(0)\n+\n+#define IXGBE_ACI_SANITIZE_READ_SUBJECT_NVM_BITS\t0\n+#define IXGBE_ACI_SANITIZE_READ_SUBJECT_NVM_STATE\tBIT(1)\n+#define IXGBE_ACI_SANITIZE_OPERATE_SUBJECT_CLEAR\t0\n+\tu8 values;\n+#define IXGBE_ACI_SANITIZE_NVM_BITS_HOST_CLEAN_SUPPORT\tBIT(0)\n+#define IXGBE_ACI_SANITIZE_NVM_BITS_BMC_CLEAN_SUPPORT\tBIT(2)\n+#define IXGBE_ACI_SANITIZE_NVM_STATE_HOST_CLEAN_DONE\tBIT(0)\n+#define IXGBE_ACI_SANITIZE_NVM_STATE_HOST_CLEAN_SUCCESS\tBIT(1)\n+#define IXGBE_ACI_SANITIZE_NVM_STATE_BMC_CLEAN_DONE\tBIT(2)\n+#define IXGBE_ACI_SANITIZE_NVM_STATE_BMC_CLEAN_SUCCESS\tBIT(3)\n+#define IXGBE_ACI_SANITIZE_OPERATE_HOST_CLEAN_DONE\tBIT(0)\n+#define IXGBE_ACI_SANITIZE_OPERATE_HOST_CLEAN_SUCCESS\tBIT(1)\n+#define IXGBE_ACI_SANITIZE_OPERATE_BMC_CLEAN_DONE\tBIT(2)\n+#define IXGBE_ACI_SANITIZE_OPERATE_BMC_CLEAN_SUCCESS\tBIT(3)\n+\tu8 reserved[14];\n+};\n+\n+IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_nvm_sanitization);\n+\n+/* Write/Read Alternate - Direct (direct 0x0900/0x0902) */\n+struct ixgbe_aci_cmd_read_write_alt_direct {\n+\t__le32 dword0_addr;\n+\t__le32 dword0_value;\n+\t__le32 dword1_addr;\n+\t__le32 dword1_value;\n+};\n+\n+IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_read_write_alt_direct);\n+\n+/* Write/Read Alternate - Indirect (indirect 0x0901/0x0903) */\n+struct ixgbe_aci_cmd_read_write_alt_indirect {\n+\t__le32 base_dword_addr;\n+\t__le32 num_dwords;\n+\t__le32 addr_high;\n+\t__le32 addr_low;\n+};\n+\n+IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_read_write_alt_indirect);\n+\n+/* Done Alternate Write (direct 0x0904) */\n+struct ixgbe_aci_cmd_done_alt_write {\n+\tu8 flags;\n+#define IXGBE_ACI_CMD_UEFI_BIOS_MODE\tBIT(0)\n+#define IXGBE_ACI_RESP_RESET_NEEDED\tBIT(1)\n+\tu8 reserved[15];\n+};\n+\n+IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_done_alt_write);\n+\n+/* Clear Port Alternate Write (direct 0x0906) */\n+struct ixgbe_aci_cmd_clear_port_alt_write {\n+\tu8 reserved[16];\n+};\n+\n+IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_clear_port_alt_write);\n+\n+/* Debug Dump Internal Data (indirect 0xFF08) */\n+struct ixgbe_aci_cmd_debug_dump_internals {\n+\t__le16 cluster_id; /* Expresses next cluster ID in response */\n+#define IXGBE_ACI_DBG_DUMP_CLUSTER_ID_LINK\t\t0\n+#define IXGBE_ACI_DBG_DUMP_CLUSTER_ID_FULL_CSR_SPACE\t1\n+\t__le16 table_id; /* Used only for non-memory clusters */\n+\t__le32 idx; /* In table entries for tables, in bytes for memory */\n+\t__le32 addr_high;\n+\t__le32 addr_low;\n+};\n+\n+IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_debug_dump_internals);\n+\n+/* Set Health Status (direct 0xFF20) */\n+struct ixgbe_aci_cmd_set_health_status_config {\n+\tu8 event_source;\n+#define IXGBE_ACI_HEALTH_STATUS_SET_PF_SPECIFIC_MASK\tBIT(0)\n+#define IXGBE_ACI_HEALTH_STATUS_SET_ALL_PF_MASK\t\tBIT(1)\n+#define IXGBE_ACI_HEALTH_STATUS_SET_GLOBAL_MASK\t\tBIT(2)\n+\tu8 reserved[15];\n+};\n+\n+IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_set_health_status_config);\n+\n+#define IXGBE_ACI_HEALTH_STATUS_ERR_UNKNOWN_MOD_STRICT\t\t0x101\n+#define IXGBE_ACI_HEALTH_STATUS_ERR_MOD_TYPE\t\t\t0x102\n+#define IXGBE_ACI_HEALTH_STATUS_ERR_MOD_QUAL\t\t\t0x103\n+#define IXGBE_ACI_HEALTH_STATUS_ERR_MOD_COMM\t\t\t0x104\n+#define IXGBE_ACI_HEALTH_STATUS_ERR_MOD_CONFLICT\t\t0x105\n+#define IXGBE_ACI_HEALTH_STATUS_ERR_MOD_NOT_PRESENT\t\t0x106\n+#define IXGBE_ACI_HEALTH_STATUS_INFO_MOD_UNDERUTILIZED\t\t0x107\n+#define IXGBE_ACI_HEALTH_STATUS_ERR_UNKNOWN_MOD_LENIENT\t\t0x108\n+#define IXGBE_ACI_HEALTH_STATUS_ERR_MOD_DIAGNOSTIC_FEATURE\t0x109\n+#define IXGBE_ACI_HEALTH_STATUS_ERR_INVALID_LINK_CFG\t\t0x10B\n+#define IXGBE_ACI_HEALTH_STATUS_ERR_PORT_ACCESS\t\t\t0x10C\n+#define IXGBE_ACI_HEALTH_STATUS_ERR_PORT_UNREACHABLE\t\t0x10D\n+#define IXGBE_ACI_HEALTH_STATUS_INFO_PORT_SPEED_MOD_LIMITED\t0x10F\n+#define IXGBE_ACI_HEALTH_STATUS_ERR_PARALLEL_FAULT\t\t0x110\n+#define IXGBE_ACI_HEALTH_STATUS_INFO_PORT_SPEED_PHY_LIMITED\t0x111\n+#define IXGBE_ACI_HEALTH_STATUS_ERR_NETLIST_TOPO\t\t0x112\n+#define IXGBE_ACI_HEALTH_STATUS_ERR_NETLIST\t\t\t0x113\n+#define IXGBE_ACI_HEALTH_STATUS_ERR_TOPO_CONFLICT\t\t0x114\n+#define IXGBE_ACI_HEALTH_STATUS_ERR_LINK_HW_ACCESS\t\t0x115\n+#define IXGBE_ACI_HEALTH_STATUS_ERR_LINK_RUNTIME\t\t0x116\n+#define IXGBE_ACI_HEALTH_STATUS_ERR_DNL_INIT\t\t\t0x117\n+#define IXGBE_ACI_HEALTH_STATUS_ERR_PHY_NVM_PROG\t\t0x120\n+#define IXGBE_ACI_HEALTH_STATUS_ERR_PHY_FW_LOAD\t\t\t0x121\n+#define IXGBE_ACI_HEALTH_STATUS_INFO_RECOVERY\t\t\t0x500\n+#define IXGBE_ACI_HEALTH_STATUS_ERR_FLASH_ACCESS\t\t0x501\n+#define IXGBE_ACI_HEALTH_STATUS_ERR_NVM_AUTH\t\t\t0x502\n+#define IXGBE_ACI_HEALTH_STATUS_ERR_OROM_AUTH\t\t\t0x503\n+#define IXGBE_ACI_HEALTH_STATUS_ERR_DDP_AUTH\t\t\t0x504\n+#define IXGBE_ACI_HEALTH_STATUS_ERR_NVM_COMPAT\t\t\t0x505\n+#define IXGBE_ACI_HEALTH_STATUS_ERR_OROM_COMPAT\t\t\t0x506\n+#define IXGBE_ACI_HEALTH_STATUS_ERR_NVM_SEC_VIOLATION\t\t0x507\n+#define IXGBE_ACI_HEALTH_STATUS_ERR_OROM_SEC_VIOLATION\t\t0x508\n+#define IXGBE_ACI_HEALTH_STATUS_ERR_DCB_MIB\t\t\t0x509\n+#define IXGBE_ACI_HEALTH_STATUS_ERR_MNG_TIMEOUT\t\t\t0x50A\n+#define IXGBE_ACI_HEALTH_STATUS_ERR_BMC_RESET\t\t\t0x50B\n+#define IXGBE_ACI_HEALTH_STATUS_ERR_LAST_MNG_FAIL\t\t0x50C\n+#define IXGBE_ACI_HEALTH_STATUS_ERR_RESOURCE_ALLOC_FAIL\t\t0x50D\n+#define IXGBE_ACI_HEALTH_STATUS_ERR_FW_LOOP\t\t\t0x1000\n+#define IXGBE_ACI_HEALTH_STATUS_ERR_FW_PFR_FAIL\t\t\t0x1001\n+#define IXGBE_ACI_HEALTH_STATUS_ERR_LAST_FAIL_AQ\t\t0x1002\n+\n+/* Get Health Status codes (indirect 0xFF21) */\n+struct ixgbe_aci_cmd_get_supported_health_status_codes {\n+\t__le16 health_code_count;\n+\tu8 reserved[6];\n+\t__le32 addr_high;\n+\t__le32 addr_low;\n+};\n+\n+IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_get_supported_health_status_codes);\n+\n+/* Get Health Status (indirect 0xFF22) */\n+struct ixgbe_aci_cmd_get_health_status {\n+\t__le16 health_status_count;\n+\tu8 reserved[6];\n+\t__le32 addr_high;\n+\t__le32 addr_low;\n+};\n+\n+IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_get_health_status);\n+\n+/* Get Health Status event buffer entry, (0xFF22)\n+ * repeated per reported health status\n+ */\n+struct ixgbe_aci_cmd_health_status_elem {\n+\t__le16 health_status_code;\n+\t__le16 event_source;\n+#define IXGBE_ACI_HEALTH_STATUS_PF\t\t(0x1)\n+#define IXGBE_ACI_HEALTH_STATUS_PORT\t\t(0x2)\n+#define IXGBE_ACI_HEALTH_STATUS_GLOBAL\t\t(0x3)\n+\t__le32 internal_data1;\n+#define IXGBE_ACI_HEALTH_STATUS_UNDEFINED_DATA\t(0xDEADBEEF)\n+\t__le32 internal_data2;\n+};\n+\n+IXGBE_CHECK_STRUCT_LEN(12, ixgbe_aci_cmd_health_status_elem);\n+\n+/* Clear Health Status (direct 0xFF23) */\n+struct ixgbe_aci_cmd_clear_health_status {\n+\t__le32 reserved[4];\n+};\n+\n+IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_clear_health_status);\n+\n+/**\n+ * struct ixgbe_aq_desc - Admin Command (AC) descriptor\n+ * @flags: IXGBE_ACI_FLAG_* flags\n+ * @opcode: Admin command opcode\n+ * @datalen: length in bytes of indirect/external data buffer\n+ * @retval: return value from firmware\n+ * @cookie_high: opaque data high-half\n+ * @cookie_low: opaque data low-half\n+ * @params: command-specific parameters\n+ *\n+ * Descriptor format for commands the driver posts via the Admin Command Interface\n+ * (ACI). The firmware writes back onto the command descriptor and returns\n+ * the result of the command. Asynchronous events that are not an immediate\n+ * result of the command are written to the Admin Command Interface (ACI) using\n+ * the same descriptor format. Descriptors are in little-endian notation with\n+ * 32-bit words.\n+ */\n+struct ixgbe_aci_desc {\n+\t__le16 flags;\n+\t__le16 opcode;\n+\t__le16 datalen;\n+\t__le16 retval;\n+\t__le32 cookie_high;\n+\t__le32 cookie_low;\n+\tunion {\n+\t\tu8 raw[16];\n+\t\tstruct ixgbe_aci_cmd_generic generic;\n+\t\tstruct ixgbe_aci_cmd_get_ver get_ver;\n+\t\tstruct ixgbe_aci_cmd_driver_ver driver_ver;\n+\t\tstruct ixgbe_aci_cmd_get_exp_err exp_err;\n+\t\tstruct ixgbe_aci_cmd_req_res res_owner;\n+\t\tstruct ixgbe_aci_cmd_list_caps get_cap;\n+\t\tstruct ixgbe_aci_cmd_disable_rxen disable_rxen;\n+\t\tstruct ixgbe_aci_cmd_get_fw_event get_fw_event;\n+\t\tstruct ixgbe_aci_cmd_get_phy_caps get_phy;\n+\t\tstruct ixgbe_aci_cmd_set_phy_cfg set_phy;\n+\t\tstruct ixgbe_aci_cmd_restart_an restart_an;\n+\t\tstruct ixgbe_aci_cmd_get_link_status get_link_status;\n+\t\tstruct ixgbe_aci_cmd_set_event_mask set_event_mask;\n+\t\tstruct ixgbe_aci_cmd_get_link_topo get_link_topo;\n+\t\tstruct ixgbe_aci_cmd_get_link_topo_pin get_link_topo_pin;\n+\t\tstruct ixgbe_aci_cmd_i2c read_write_i2c;\n+\t\tstruct ixgbe_aci_cmd_read_i2c_resp read_i2c_resp;\n+\t\tstruct ixgbe_aci_cmd_mdio read_write_mdio;\n+\t\tstruct ixgbe_aci_cmd_mdio read_mdio;\n+\t\tstruct ixgbe_aci_cmd_mdio write_mdio;\n+\t\tstruct ixgbe_aci_cmd_gpio_by_func read_write_gpio_by_func;\n+\t\tstruct ixgbe_aci_cmd_gpio read_write_gpio;\n+\t\tstruct ixgbe_aci_cmd_sff_eeprom read_write_sff_param;\n+\t\tstruct ixgbe_aci_cmd_prog_topo_dev_nvm prog_topo_dev_nvm;\n+\t\tstruct ixgbe_aci_cmd_read_topo_dev_nvm read_topo_dev_nvm;\n+\t\tstruct ixgbe_aci_cmd_nvm nvm;\n+\t\tstruct ixgbe_aci_cmd_nvm_cfg nvm_cfg;\n+\t\tstruct ixgbe_aci_cmd_nvm_checksum nvm_checksum;\n+\t\tstruct ixgbe_aci_cmd_read_write_alt_direct read_write_alt_direct;\n+\t\tstruct ixgbe_aci_cmd_read_write_alt_indirect read_write_alt_indirect;\n+\t\tstruct ixgbe_aci_cmd_done_alt_write done_alt_write;\n+\t\tstruct ixgbe_aci_cmd_clear_port_alt_write clear_port_alt_write;\n+\t\tstruct ixgbe_aci_cmd_debug_dump_internals debug_dump;\n+\t\tstruct ixgbe_aci_cmd_set_health_status_config\n+\t\t\tset_health_status_config;\n+\t\tstruct ixgbe_aci_cmd_get_supported_health_status_codes\n+\t\t\tget_supported_health_status_codes;\n+\t\tstruct ixgbe_aci_cmd_get_health_status get_health_status;\n+\t\tstruct ixgbe_aci_cmd_clear_health_status clear_health_status;\n+\t\tstruct ixgbe_aci_cmd_nvm_sanitization nvm_sanitization;\n+\t} params;\n+};\n+\n+/* E610-specific adapter context structures */\n+\n+struct ixgbe_link_status {\n+\t/* Refer to ixgbe_aci_phy_type for bits definition */\n+\tu64 phy_type_low;\n+\tu64 phy_type_high;\n+\tu8 topo_media_conflict;\n+\tu16 max_frame_size;\n+\tu16 link_speed;\n+\tu16 req_speeds;\n+\tu8 link_cfg_err;\n+\tu8 lse_ena;\t/* Link Status Event notification */\n+\tu8 link_info;\n+\tu8 an_info;\n+\tu8 ext_info;\n+\tu8 fec_info;\n+\tu8 pacing;\n+\t/* Refer to #define from module_type[IXGBE_ACI_MODULE_TYPE_TOTAL_BYTE] of\n+\t * ixgbe_aci_get_phy_caps structure\n+\t */\n+\tu8 module_type[IXGBE_ACI_MODULE_TYPE_TOTAL_BYTE];\n+};\n+\n+/* Common HW capabilities for SW use */\n+struct ixgbe_hw_common_caps {\n+\t/* Write CSR protection */\n+\tu64 wr_csr_prot;\n+\tu32 switching_mode;\n+\t/* switching mode supported - EVB switching (including cloud) */\n+#define IXGBE_NVM_IMAGE_TYPE_EVB\t\t0x0\n+\n+\t/* Manageability mode & supported protocols over MCTP */\n+\tu32 mgmt_mode;\n+#define IXGBE_MGMT_MODE_PASS_THRU_MODE_M\t0xF\n+#define IXGBE_MGMT_MODE_CTL_INTERFACE_M\t\t0xF0\n+#define IXGBE_MGMT_MODE_REDIR_SB_INTERFACE_M\t0xF00\n+\n+\tu32 mgmt_protocols_mctp;\n+#define IXGBE_MGMT_MODE_PROTO_RSVD\tBIT(0)\n+#define IXGBE_MGMT_MODE_PROTO_PLDM\tBIT(1)\n+#define IXGBE_MGMT_MODE_PROTO_OEM\tBIT(2)\n+#define IXGBE_MGMT_MODE_PROTO_NC_SI\tBIT(3)\n+\n+\tu32 os2bmc;\n+\tu32 valid_functions;\n+\t/* DCB capabilities */\n+\tu32 active_tc_bitmap;\n+\tu32 maxtc;\n+\n+\t/* RSS related capabilities */\n+\tu32 rss_table_size;\t\t/* 512 for PFs and 64 for VFs */\n+\tu32 rss_table_entry_width;\t/* RSS Entry width in bits */\n+\n+\t/* Tx/Rx queues */\n+\tu32 num_rxq;\t\t\t/* Number/Total Rx queues */\n+\tu32 rxq_first_id;\t\t/* First queue ID for Rx queues */\n+\tu32 num_txq;\t\t\t/* Number/Total Tx queues */\n+\tu32 txq_first_id;\t\t/* First queue ID for Tx queues */\n+\n+\t/* MSI-X vectors */\n+\tu32 num_msix_vectors;\n+\tu32 msix_vector_first_id;\n+\n+\t/* Max MTU for function or device */\n+\tu32 max_mtu;\n+\n+\t/* WOL related */\n+\tu32 num_wol_proxy_fltr;\n+\tu32 wol_proxy_vsi_seid;\n+\n+\t/* LED/SDP pin count */\n+\tu32 led_pin_num;\n+\tu32 sdp_pin_num;\n+\n+\t/* LED/SDP - Supports up to 12 LED pins and 8 SDP signals */\n+#define IXGBE_MAX_SUPPORTED_GPIO_LED\t12\n+#define IXGBE_MAX_SUPPORTED_GPIO_SDP\t8\n+\tu8 led[IXGBE_MAX_SUPPORTED_GPIO_LED];\n+\tu8 sdp[IXGBE_MAX_SUPPORTED_GPIO_SDP];\n+\t/* VMDQ */\n+\tu8 vmdq;\t\t\t/* VMDQ supported */\n+\n+\t/* EVB capabilities */\n+\tu8 evb_802_1_qbg;\t\t/* Edge Virtual Bridging */\n+\tu8 evb_802_1_qbh;\t\t/* Bridge Port Extension */\n+\n+\tu8 dcb;\n+\tu8 iscsi;\n+\tu8 ieee_1588;\n+\tu8 mgmt_cem;\n+\n+\t/* WoL and APM support */\n+#define IXGBE_WOL_SUPPORT_M\t\tBIT(0)\n+#define IXGBE_ACPI_PROG_MTHD_M\t\tBIT(1)\n+#define IXGBE_PROXY_SUPPORT_M\t\tBIT(2)\n+\tu8 apm_wol_support;\n+\tu8 acpi_prog_mthd;\n+\tu8 proxy_support;\n+\tbool sec_rev_disabled;\n+\tbool update_disabled;\n+\tbool nvm_unified_update;\n+\tbool netlist_auth;\n+#define IXGBE_NVM_MGMT_SEC_REV_DISABLED\t\tBIT(0)\n+#define IXGBE_NVM_MGMT_UPDATE_DISABLED\t\tBIT(1)\n+#define IXGBE_NVM_MGMT_UNIFIED_UPD_SUPPORT\tBIT(3)\n+#define IXGBE_NVM_MGMT_NETLIST_AUTH_SUPPORT\tBIT(5)\n+\tbool no_drop_policy_support;\n+\t/* PCIe reset avoidance */\n+\tbool pcie_reset_avoidance; /* false: not supported, true: supported */\n+\t/* Post update reset restriction */\n+\tbool reset_restrict_support; /* false: not supported, true: supported */\n+\n+\t/* External topology device images within the NVM */\n+#define IXGBE_EXT_TOPO_DEV_IMG_COUNT\t4\n+\tu32 ext_topo_dev_img_ver_high[IXGBE_EXT_TOPO_DEV_IMG_COUNT];\n+\tu32 ext_topo_dev_img_ver_low[IXGBE_EXT_TOPO_DEV_IMG_COUNT];\n+\tu8 ext_topo_dev_img_part_num[IXGBE_EXT_TOPO_DEV_IMG_COUNT];\n+#define IXGBE_EXT_TOPO_DEV_IMG_PART_NUM_S\t8\n+#define IXGBE_EXT_TOPO_DEV_IMG_PART_NUM_M\t\\\n+\t\tMAKEMASK(0xFF, IXGBE_EXT_TOPO_DEV_IMG_PART_NUM_S)\n+\tbool ext_topo_dev_img_load_en[IXGBE_EXT_TOPO_DEV_IMG_COUNT];\n+#define IXGBE_EXT_TOPO_DEV_IMG_LOAD_EN\tBIT(0)\n+\tbool ext_topo_dev_img_prog_en[IXGBE_EXT_TOPO_DEV_IMG_COUNT];\n+#define IXGBE_EXT_TOPO_DEV_IMG_PROG_EN\tBIT(1)\n+\tbool next_cluster_id_support;\n+};\n+\n+/* IEEE 1588 TIME_SYNC specific info */\n+/* Function specific definitions */\n+#define IXGBE_TS_FUNC_ENA_M\t\tBIT(0)\n+#define IXGBE_TS_SRC_TMR_OWND_M\t\tBIT(1)\n+#define IXGBE_TS_TMR_ENA_M\t\tBIT(2)\n+#define IXGBE_TS_TMR_IDX_OWND_S\t\t4\n+#define IXGBE_TS_TMR_IDX_OWND_M\t\tBIT(4)\n+#define IXGBE_TS_CLK_FREQ_S\t\t16\n+#define IXGBE_TS_CLK_FREQ_M\t\tMAKEMASK(0x7, IXGBE_TS_CLK_FREQ_S)\n+#define IXGBE_TS_CLK_SRC_S\t\t20\n+#define IXGBE_TS_CLK_SRC_M\t\tBIT(20)\n+#define IXGBE_TS_TMR_IDX_ASSOC_S\t24\n+#define IXGBE_TS_TMR_IDX_ASSOC_M\tBIT(24)\n+\n+/* TIME_REF clock rate specification */\n+enum ixgbe_time_ref_freq {\n+\tIXGBE_TIME_REF_FREQ_25_000\t= 0,\n+\tIXGBE_TIME_REF_FREQ_122_880\t= 1,\n+\tIXGBE_TIME_REF_FREQ_125_000\t= 2,\n+\tIXGBE_TIME_REF_FREQ_153_600\t= 3,\n+\tIXGBE_TIME_REF_FREQ_156_250\t= 4,\n+\tIXGBE_TIME_REF_FREQ_245_760\t= 5,\n+\n+\tNUM_IXGBE_TIME_REF_FREQ\n+};\n+\n+struct ixgbe_ts_func_info {\n+\t/* Function specific info */\n+\tenum ixgbe_time_ref_freq time_ref;\n+\tu8 clk_freq;\n+\tu8 clk_src;\n+\tu8 tmr_index_assoc;\n+\tu8 ena;\n+\tu8 tmr_index_owned;\n+\tu8 src_tmr_owned;\n+\tu8 tmr_ena;\n+};\n+\n+/* Device specific definitions */\n+#define IXGBE_TS_TMR0_OWNR_M\t\t0x7\n+#define IXGBE_TS_TMR0_OWND_M\t\tBIT(3)\n+#define IXGBE_TS_TMR1_OWNR_S\t\t4\n+#define IXGBE_TS_TMR1_OWNR_M\t\tMAKEMASK(0x7, IXGBE_TS_TMR1_OWNR_S)\n+#define IXGBE_TS_TMR1_OWND_M\t\tBIT(7)\n+#define IXGBE_TS_DEV_ENA_M\t\tBIT(24)\n+#define IXGBE_TS_TMR0_ENA_M\t\tBIT(25)\n+#define IXGBE_TS_TMR1_ENA_M\t\tBIT(26)\n+\n+struct ixgbe_ts_dev_info {\n+\t/* Device specific info */\n+\tu32 ena_ports;\n+\tu32 tmr_own_map;\n+\tu32 tmr0_owner;\n+\tu32 tmr1_owner;\n+\tu8 tmr0_owned;\n+\tu8 tmr1_owned;\n+\tu8 ena;\n+\tu8 tmr0_ena;\n+\tu8 tmr1_ena;\n+};\n+\n+/* Function specific capabilities */\n+struct ixgbe_hw_func_caps {\n+\tstruct ixgbe_hw_common_caps common_cap;\n+\tu32 guar_num_vsi;\n+\tstruct ixgbe_ts_func_info ts_func_info;\n+\tbool no_drop_policy_ena;\n+};\n+\n+/* Device wide capabilities */\n+struct ixgbe_hw_dev_caps {\n+\tstruct ixgbe_hw_common_caps common_cap;\n+\tu32 num_vsi_allocd_to_host;\t/* Excluding EMP VSI */\n+\tu32 num_flow_director_fltr;\t/* Number of FD filters available */\n+\tstruct ixgbe_ts_dev_info ts_dev_info;\n+\tu32 num_funcs;\n+};\n+\n+/* ACI event information */\n+struct ixgbe_aci_event {\n+\tstruct ixgbe_aci_desc desc;\n+\tu16 msg_len;\n+\tu16 buf_len;\n+\tu8 *msg_buf;\n+};\n+\n+struct ixgbe_aci_info {\n+\tenum ixgbe_aci_err last_status;\t/* last status of sent admin command */\n+\tstruct ixgbe_lock lock;\t\t/* admin command interface lock */\n+};\n+\n+/* Option ROM version information */\n+struct ixgbe_orom_info {\n+\tu8 major;\t\t\t/* Major version of OROM */\n+\tu8 patch;\t\t\t/* Patch version of OROM */\n+\tu16 build;\t\t\t/* Build version of OROM */\n+\tu32 srev;\t\t\t/* Security revision */\n+};\n+\n+/* NVM version information */\n+struct ixgbe_nvm_info {\n+\tu32 eetrack;\n+\tu32 srev;\n+\tu8 major;\n+\tu8 minor;\n+};\n+\n+/* Enumeration of possible flash banks for the NVM, OROM, and Netlist modules\n+ * of the flash image.\n+ */\n+enum ixgbe_flash_bank {\n+\tIXGBE_INVALID_FLASH_BANK,\n+\tIXGBE_1ST_FLASH_BANK,\n+\tIXGBE_2ND_FLASH_BANK,\n+};\n+\n+/* information for accessing NVM, OROM, and Netlist flash banks */\n+struct ixgbe_bank_info {\n+\tu32 nvm_ptr;\t\t\t\t/* Pointer to 1st NVM bank */\n+\tu32 nvm_size;\t\t\t\t/* Size of NVM bank */\n+\tu32 orom_ptr;\t\t\t\t/* Pointer to 1st OROM bank */\n+\tu32 orom_size;\t\t\t\t/* Size of OROM bank */\n+\tu32 netlist_ptr;\t\t\t/* Pointer to 1st Netlist bank */\n+\tu32 netlist_size;\t\t\t/* Size of Netlist bank */\n+\tenum ixgbe_flash_bank nvm_bank;\t\t/* Active NVM bank */\n+\tenum ixgbe_flash_bank orom_bank;\t/* Active OROM bank */\n+\tenum ixgbe_flash_bank netlist_bank;\t/* Active Netlist bank */\n+};\n+\n+/* Flash Chip Information */\n+struct ixgbe_flash_info {\n+\tstruct ixgbe_orom_info orom;\t\t/* Option ROM version info */\n+\tstruct ixgbe_nvm_info nvm;\t\t/* NVM version information */\n+\tstruct ixgbe_bank_info banks;\t\t/* Flash Bank information */\n+\tu16 sr_words;\t\t\t\t/* Shadow RAM size in words */\n+\tu32 flash_size;\t\t\t\t/* Size of available flash in bytes */\n+\tu8 blank_nvm_mode;\t\t\t/* is NVM empty (no FW present) */\n+};\n+\n+#endif /* _IXGBE_TYPE_E610_H_ */\ndiff --git a/drivers/net/ixgbe/base/meson.build b/drivers/net/ixgbe/base/meson.build\nindex f6497014da..7e4fbdfa0f 100644\n--- a/drivers/net/ixgbe/base/meson.build\n+++ b/drivers/net/ixgbe/base/meson.build\n@@ -1,5 +1,5 @@\n # SPDX-License-Identifier: BSD-3-Clause\n-# Copyright(c) 2017-2020 Intel Corporation\n+# Copyright(c) 2017-2024 Intel Corporation\n \n sources = [\n         'ixgbe_82598.c',\n@@ -9,8 +9,10 @@ sources = [\n         'ixgbe_dcb_82598.c',\n         'ixgbe_dcb_82599.c',\n         'ixgbe_dcb.c',\n+        'ixgbe_e610.c',\n         'ixgbe_hv_vf.c',\n         'ixgbe_mbx.c',\n+        'ixgbe_osdep.c',\n         'ixgbe_phy.c',\n         'ixgbe_vf.c',\n         'ixgbe_x540.c',\n",
    "prefixes": [
        "v2",
        "22/27"
    ]
}