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GET /api/patches/139854/?format=api
{ "id": 139854, "url": "http://patchwork.dpdk.org/api/patches/139854/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/ddc7b3e6aad8ea87e589b268ed19cbd7b0985be9.1714744629.git.anatoly.burakov@intel.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<ddc7b3e6aad8ea87e589b268ed19cbd7b0985be9.1714744629.git.anatoly.burakov@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/ddc7b3e6aad8ea87e589b268ed19cbd7b0985be9.1714744629.git.anatoly.burakov@intel.com", "date": "2024-05-03T13:57:57", "name": "[v2,26/27] net/ixgbe/base: enable E610 device support", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "a9f6e7a1e8c1b27f81011814ef42a8491de5aa8c", "submitter": { "id": 4, "url": "http://patchwork.dpdk.org/api/people/4/?format=api", "name": "Burakov, Anatoly", "email": "anatoly.burakov@intel.com" }, "delegate": null, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/ddc7b3e6aad8ea87e589b268ed19cbd7b0985be9.1714744629.git.anatoly.burakov@intel.com/mbox/", "series": [ { "id": 31875, "url": "http://patchwork.dpdk.org/api/series/31875/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=31875", "date": "2024-05-03T13:57:31", "name": "Update IXGBE base driver", "version": 2, "mbox": "http://patchwork.dpdk.org/series/31875/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/139854/comments/", "check": "warning", "checks": "http://patchwork.dpdk.org/api/patches/139854/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id CD1CD43F76;\n\tFri, 3 May 2024 16:01:33 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id BE6AB40F16;\n\tFri, 3 May 2024 15:59:18 +0200 (CEST)", "from mgamail.intel.com (mgamail.intel.com [192.198.163.15])\n by mails.dpdk.org (Postfix) with ESMTP id E4300410F6\n for <dev@dpdk.org>; Fri, 3 May 2024 15:59:15 +0200 (CEST)", "from fmviesa002.fm.intel.com ([10.60.135.142])\n by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 03 May 2024 06:59:15 -0700", "from silpixa00401119.ir.intel.com ([10.55.129.167])\n by fmviesa002.fm.intel.com with ESMTP; 03 May 2024 06:59:13 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1714744756; x=1746280756;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=6lz5DPW1ztBmvG+iUavmSFs7XBbGnv1KVS9QjjzzRLc=;\n b=Nn9F27GsPuuYIJ2g1shqSpB6IJYwdgpQugopqHa73oNhLKFSK2nr9M00\n +hxE23zyYZNGOTNQqAAJib9IwwlHlnooM33n5yyofU+YWimLABq+8CvgI\n eF6tjpDTckxVsHb+zQHFISakY8c7oocxPbdPv9d7mPCNKk/ABn1qsGcTb\n 9lZDFY8O+0gJwuPJQ3ZNCmOmTavKCbhp8MBY7smmIpvGCInOfAAw7/Ela\n FZbLv1ZVbOeiPEmQfu/dUckv7ZroEil6bAFqYWF2CesEwO310h0J3WLJ/\n leH1dT6TPL0/oEfLMsOsFm3ui/FvINlaAVo77nCYPJ9dAfasRaeNw9+rD A==;", "X-CSE-ConnectionGUID": [ "z+LLx8EPQhmsZkwbDqxsqA==", "F3GhBSqoRW6SZ4XXajEGvw==" ], "X-CSE-MsgGUID": [ "ZhHOI6DqQj2YgOdj62XzLQ==", "/S9fopt/R/K41jpgTveUNw==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6600,9927,11063\"; a=\"10714986\"", "E=Sophos;i=\"6.07,251,1708416000\"; d=\"scan'208\";a=\"10714986\"", "E=Sophos;i=\"6.07,251,1708416000\"; d=\"scan'208\";a=\"50642065\"" ], "X-ExtLoop1": "1", "From": "Anatoly Burakov <anatoly.burakov@intel.com>", "To": "dev@dpdk.org", "Cc": "Piotr Kwapulinski <piotr.kwapulinski@intel.com>,\n bruce.richardson@intel.com, vladimir.medvedkin@intel.com,\n Carolyn Wyborny <carolyn.wyborny@intel.com>,\n Jedrzej Jagielski <jedrzej.jagielski@intel.com>", "Subject": "[PATCH v2 26/27] net/ixgbe/base: enable E610 device support", "Date": "Fri, 3 May 2024 14:57:57 +0100", "Message-ID": "\n <ddc7b3e6aad8ea87e589b268ed19cbd7b0985be9.1714744629.git.anatoly.burakov@intel.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<cover.1714744628.git.anatoly.burakov@intel.com>", "References": "<cover.1713964707.git.anatoly.burakov@intel.com>\n <cover.1714744628.git.anatoly.burakov@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Piotr Kwapulinski <piotr.kwapulinski@intel.com>\n\nAdd high level link management support for E610 device, as well as\nenable all code paths related to E610 initialization. This makes it so\nthat E610 can be brought up using ixgbe driver.\n\nSigned-off-by: Carolyn Wyborny <carolyn.wyborny@intel.com>\nSigned-off-by: Jedrzej Jagielski <jedrzej.jagielski@intel.com>\nSigned-off-by: Piotr Kwapulinski <piotr.kwapulinski@intel.com>\nSigned-off-by: Anatoly Burakov <anatoly.burakov@intel.com>\n---\n drivers/net/ixgbe/base/ixgbe_82599.c | 7 +-\n drivers/net/ixgbe/base/ixgbe_api.c | 60 +-\n drivers/net/ixgbe/base/ixgbe_api.h | 7 +-\n drivers/net/ixgbe/base/ixgbe_common.c | 31 +-\n drivers/net/ixgbe/base/ixgbe_e610.c | 1061 ++++++++++++++++++++++\n drivers/net/ixgbe/base/ixgbe_e610.h | 16 +\n drivers/net/ixgbe/base/ixgbe_hv_vf.c | 5 +-\n drivers/net/ixgbe/base/ixgbe_mbx.c | 5 +-\n drivers/net/ixgbe/base/ixgbe_phy.c | 6 +-\n drivers/net/ixgbe/base/ixgbe_type.h | 6 +\n drivers/net/ixgbe/base/ixgbe_type_e610.h | 102 +++\n 11 files changed, 1283 insertions(+), 23 deletions(-)", "diff": "diff --git a/drivers/net/ixgbe/base/ixgbe_82599.c b/drivers/net/ixgbe/base/ixgbe_82599.c\nindex 562034b242..c4ad906f0f 100644\n--- a/drivers/net/ixgbe/base/ixgbe_82599.c\n+++ b/drivers/net/ixgbe/base/ixgbe_82599.c\n@@ -1,5 +1,5 @@\n /* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(c) 2001-2020 Intel Corporation\n+ * Copyright(c) 2001-2024 Intel Corporation\n */\n \n #include \"ixgbe_type.h\"\n@@ -1389,7 +1389,8 @@ void ixgbe_set_fdir_drop_queue_82599(struct ixgbe_hw *hw, u8 dropqueue)\n \tfdirctrl |= (dropqueue << IXGBE_FDIRCTRL_DROP_Q_SHIFT);\n \tif ((hw->mac.type == ixgbe_mac_X550) ||\n \t (hw->mac.type == ixgbe_mac_X550EM_x) ||\n-\t (hw->mac.type == ixgbe_mac_X550EM_a))\n+\t (hw->mac.type == ixgbe_mac_X550EM_a) ||\n+\t (hw->mac.type == ixgbe_mac_E610))\n \t\tfdirctrl |= IXGBE_FDIRCTRL_DROP_NO_MATCH;\n \n \tIXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,\n@@ -1804,6 +1805,7 @@ s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,\n \t\tcase ixgbe_mac_X550:\n \t\tcase ixgbe_mac_X550EM_x:\n \t\tcase ixgbe_mac_X550EM_a:\n+\t\tcase ixgbe_mac_E610:\n \t\t\tIXGBE_WRITE_REG(hw, IXGBE_FDIRSCTPM, 0xFFFFFFFF);\n \t\t\tbreak;\n \t\tdefault:\n@@ -1827,6 +1829,7 @@ s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,\n \t\tcase ixgbe_mac_X550:\n \t\tcase ixgbe_mac_X550EM_x:\n \t\tcase ixgbe_mac_X550EM_a:\n+\t\tcase ixgbe_mac_E610:\n \t\t\tIXGBE_WRITE_REG(hw, IXGBE_FDIRSCTPM, ~fdirtcpm);\n \t\t\tbreak;\n \t\tdefault:\ndiff --git a/drivers/net/ixgbe/base/ixgbe_api.c b/drivers/net/ixgbe/base/ixgbe_api.c\nindex d2b74cdffc..c8f9a6d9f1 100644\n--- a/drivers/net/ixgbe/base/ixgbe_api.c\n+++ b/drivers/net/ixgbe/base/ixgbe_api.c\n@@ -1,5 +1,5 @@\n /* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(c) 2001-2020 Intel Corporation\n+ * Copyright(c) 2001-2024 Intel Corporation\n */\n \n #include \"ixgbe_api.h\"\n@@ -89,6 +89,9 @@ s32 ixgbe_init_shared_code(struct ixgbe_hw *hw)\n \tcase ixgbe_mac_X550EM_a_vf:\n \t\tstatus = ixgbe_init_ops_vf(hw);\n \t\tbreak;\n+\tcase ixgbe_mac_E610:\n+\t\tstatus = ixgbe_init_ops_E610(hw);\n+\t\tbreak;\n \tdefault:\n \t\tstatus = IXGBE_ERR_DEVICE_NOT_SUPPORTED;\n \t\tbreak;\n@@ -208,6 +211,14 @@ s32 ixgbe_set_mac_type(struct ixgbe_hw *hw)\n \t\thw->mac.type = ixgbe_mac_X550EM_a_vf;\n \t\thw->mvals = ixgbe_mvals_X550EM_a;\n \t\tbreak;\n+\tcase IXGBE_DEV_ID_E610_BACKPLANE:\n+\tcase IXGBE_DEV_ID_E610_SFP:\n+\tcase IXGBE_DEV_ID_E610_10G_T:\n+\tcase IXGBE_DEV_ID_E610_2_5G_T:\n+\tcase IXGBE_DEV_ID_E610_SGMII:\n+\t\thw->mac.type = ixgbe_mac_E610;\n+\t\thw->mvals = ixgbe_mvals_X550EM_a;\n+\t\tbreak;\n \tdefault:\n \t\tret_val = IXGBE_ERR_DEVICE_NOT_SUPPORTED;\n \t\tERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED,\n@@ -445,7 +456,8 @@ s32 ixgbe_stop_adapter(struct ixgbe_hw *hw)\n **/\n s32 ixgbe_read_pba_string(struct ixgbe_hw *hw, u8 *pba_num, u32 pba_num_size)\n {\n-\treturn ixgbe_read_pba_string_generic(hw, pba_num, pba_num_size);\n+\treturn ixgbe_call_func(hw, hw->eeprom.ops.read_pba_string, (hw, pba_num,\n+\t\t\t pba_num_size), IXGBE_NOT_IMPLEMENTED);\n }\n \n /**\n@@ -1141,6 +1153,19 @@ s32 ixgbe_set_fw_drv_ver(struct ixgbe_hw *hw, u8 maj, u8 min, u8 build,\n \t\t\t IXGBE_NOT_IMPLEMENTED);\n }\n \n+/**\n+ * ixgbe_get_fw_tsam_mode - Returns information whether TSAM is enabled\n+ * @hw: pointer to hardware structure\n+ *\n+ * Checks Thermal Sensor Autonomous Mode by reading the value of the\n+ * dedicated register.\n+ * Returns True if TSAM is enabled, False if TSAM is disabled.\n+ */\n+bool ixgbe_get_fw_tsam_mode(struct ixgbe_hw *hw)\n+{\n+\treturn ixgbe_call_func(hw, hw->mac.ops.get_fw_tsam_mode, (hw),\n+\t\t\t IXGBE_NOT_IMPLEMENTED);\n+}\n \n /**\n * ixgbe_get_thermal_sensor_data - Gathers thermal sensor data\n@@ -1684,3 +1709,34 @@ void ixgbe_set_rate_select_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed)\n \tif (hw->mac.ops.set_rate_select_speed)\n \t\thw->mac.ops.set_rate_select_speed(hw, speed);\n }\n+\n+/**\n+ * ixgbe_get_fw_version - get FW version\n+ * @hw: pointer to hardware structure\n+ *\n+ * Get the current FW version.\n+ *\n+ * Return: the exit code of the operation or IXGBE_NOT_IMPLEMENTED\n+ * if the function is not implemented.\n+ */\n+s32 ixgbe_get_fw_version(struct ixgbe_hw *hw)\n+{\n+\treturn ixgbe_call_func(hw, hw->mac.ops.get_fw_version,\n+\t\t\t (hw), IXGBE_NOT_IMPLEMENTED);\n+}\n+\n+/**\n+ * ixgbe_get_nvm_ver - get NVM version\n+ * @hw: pointer to hardware structure\n+ * @nvm: pointer to NVM info structure\n+ *\n+ * Get the current NVM version.\n+ *\n+ * Return: the exit code of the operation or IXGBE_NOT_IMPLEMENTED\n+ * if the function is not implemented.\n+ */\n+s32 ixgbe_get_nvm_ver(struct ixgbe_hw* hw, struct ixgbe_nvm_info *nvm)\n+{\n+\treturn ixgbe_call_func(hw, hw->mac.ops.get_nvm_version,\n+\t\t\t (hw, nvm), IXGBE_NOT_IMPLEMENTED);\n+}\ndiff --git a/drivers/net/ixgbe/base/ixgbe_api.h b/drivers/net/ixgbe/base/ixgbe_api.h\nindex 51decc5fae..5d2b2313eb 100644\n--- a/drivers/net/ixgbe/base/ixgbe_api.h\n+++ b/drivers/net/ixgbe/base/ixgbe_api.h\n@@ -1,5 +1,5 @@\n /* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(c) 2001-2020 Intel Corporation\n+ * Copyright(c) 2001-2024 Intel Corporation\n */\n \n #ifndef _IXGBE_API_H_\n@@ -18,6 +18,7 @@ extern s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw);\n extern s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw);\n extern s32 ixgbe_init_ops_X550EM_x(struct ixgbe_hw *hw);\n extern s32 ixgbe_init_ops_X550EM_a(struct ixgbe_hw *hw);\n+extern s32 ixgbe_init_ops_E610(struct ixgbe_hw *hw);\n extern s32 ixgbe_init_ops_vf(struct ixgbe_hw *hw);\n \n s32 ixgbe_set_mac_type(struct ixgbe_hw *hw);\n@@ -105,6 +106,7 @@ s32 ixgbe_fc_enable(struct ixgbe_hw *hw);\n s32 ixgbe_setup_fc(struct ixgbe_hw *hw);\n s32 ixgbe_set_fw_drv_ver(struct ixgbe_hw *hw, u8 maj, u8 min, u8 build,\n \t\t\t u8 ver, u16 len, char *driver_ver);\n+bool ixgbe_get_fw_tsam_mode(struct ixgbe_hw *hw);\n s32 ixgbe_get_thermal_sensor_data(struct ixgbe_hw *hw);\n s32 ixgbe_init_thermal_sensor_thresh(struct ixgbe_hw *hw);\n void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr);\n@@ -192,5 +194,6 @@ void ixgbe_disable_rx(struct ixgbe_hw *hw);\n void ixgbe_enable_rx(struct ixgbe_hw *hw);\n s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,\n \t\t\tu32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm);\n-\n+s32 ixgbe_get_fw_version(struct ixgbe_hw *hw);\n+s32 ixgbe_get_nvm_ver(struct ixgbe_hw *hw, struct ixgbe_nvm_info *nvm);\n #endif /* _IXGBE_API_H_ */\ndiff --git a/drivers/net/ixgbe/base/ixgbe_common.c b/drivers/net/ixgbe/base/ixgbe_common.c\nindex 73b5935d88..d6425c5b78 100644\n--- a/drivers/net/ixgbe/base/ixgbe_common.c\n+++ b/drivers/net/ixgbe/base/ixgbe_common.c\n@@ -1,5 +1,5 @@\n /* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(c) 2001-2020 Intel Corporation\n+ * Copyright(c) 2001-2024 Intel Corporation\n */\n \n #include \"ixgbe_common.h\"\n@@ -61,6 +61,7 @@ s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw)\n \t\t\t\t ixgbe_validate_eeprom_checksum_generic;\n \teeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_generic;\n \teeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_generic;\n+\teeprom->ops.read_pba_string = ixgbe_read_pba_string_generic;\n \n \t/* MAC */\n \tmac->ops.init_hw = ixgbe_init_hw_generic;\n@@ -146,6 +147,7 @@ bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw)\n \t\tcase IXGBE_DEV_ID_X550EM_A_SFP_N:\n \t\tcase IXGBE_DEV_ID_X550EM_A_QSFP:\n \t\tcase IXGBE_DEV_ID_X550EM_A_QSFP_N:\n+\t\tcase IXGBE_DEV_ID_E610_SFP:\n \t\t\tsupported = false;\n \t\t\tbreak;\n \t\tdefault:\n@@ -177,6 +179,8 @@ bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw)\n \t\tcase IXGBE_DEV_ID_X550EM_A_10G_T:\n \t\tcase IXGBE_DEV_ID_X550EM_A_1G_T:\n \t\tcase IXGBE_DEV_ID_X550EM_A_1G_T_L:\n+\t\tcase IXGBE_DEV_ID_E610_10G_T:\n+\t\tcase IXGBE_DEV_ID_E610_2_5G_T:\n \t\t\tsupported = true;\n \t\t\tbreak;\n \t\tdefault:\n@@ -577,17 +581,11 @@ s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)\n \t\t}\n \t}\n \n-\tif (hw->mac.type == ixgbe_mac_X550 || hw->mac.type == ixgbe_mac_X540) {\n+\tif (hw->mac.type == ixgbe_mac_X540 ||\n+\t hw->mac.type == ixgbe_mac_X550 ||\n+\t hw->mac.type == ixgbe_mac_E610) {\n \t\tif (hw->phy.id == 0)\n \t\t\tixgbe_identify_phy(hw);\n-\t\thw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL,\n-\t\t\t\t IXGBE_MDIO_PCS_DEV_TYPE, &i);\n-\t\thw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH,\n-\t\t\t\t IXGBE_MDIO_PCS_DEV_TYPE, &i);\n-\t\thw->phy.ops.read_reg(hw, IXGBE_LDPCECL,\n-\t\t\t\t IXGBE_MDIO_PCS_DEV_TYPE, &i);\n-\t\thw->phy.ops.read_reg(hw, IXGBE_LDPCECH,\n-\t\t\t\t IXGBE_MDIO_PCS_DEV_TYPE, &i);\n \t}\n \n \treturn IXGBE_SUCCESS;\n@@ -998,6 +996,9 @@ void ixgbe_set_pci_config_data_generic(struct ixgbe_hw *hw, u16 link_status)\n \tcase IXGBE_PCI_LINK_SPEED_8000:\n \t\thw->bus.speed = ixgbe_bus_speed_8000;\n \t\tbreak;\n+\tcase IXGBE_PCI_LINK_SPEED_16000:\n+\t\thw->bus.speed = ixgbe_bus_speed_16000;\n+\t\tbreak;\n \tdefault:\n \t\thw->bus.speed = ixgbe_bus_speed_unknown;\n \t\tbreak;\n@@ -1020,7 +1021,9 @@ s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)\n \tDEBUGFUNC(\"ixgbe_get_bus_info_generic\");\n \n \t/* Get the negotiated link width and speed from PCI config space */\n-\tlink_status = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_LINK_STATUS);\n+\tlink_status = IXGBE_READ_PCIE_WORD(hw, hw->mac.type == ixgbe_mac_E610 ?\n+\t\t\t\t\t IXGBE_PCI_LINK_STATUS_E610 :\n+\t\t\t\t\t IXGBE_PCI_LINK_STATUS);\n \n \tixgbe_set_pci_config_data_generic(hw, link_status);\n \n@@ -3653,6 +3656,10 @@ u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)\n \t\tpcie_offset = IXGBE_PCIE_MSIX_82599_CAPS;\n \t\tmax_msix_count = IXGBE_MAX_MSIX_VECTORS_82599;\n \t\tbreak;\n+\tcase ixgbe_mac_E610:\n+\t\tpcie_offset = IXGBE_PCIE_MSIX_E610_CAPS;\n+\t\tmax_msix_count = IXGBE_MAX_MSIX_VECTORS_82599;\n+\t\tbreak;\n \tdefault:\n \t\treturn msix_count;\n \t}\n@@ -4228,7 +4235,7 @@ s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed,\n \t\tbreak;\n \tcase IXGBE_LINKS_SPEED_100_82599:\n \t\t*speed = IXGBE_LINK_SPEED_100_FULL;\n-\t\tif (hw->mac.type == ixgbe_mac_X550) {\n+\t\tif (hw->mac.type == ixgbe_mac_X550 || hw->mac.type == ixgbe_mac_E610) {\n \t\t\tif (links_reg & IXGBE_LINKS_SPEED_NON_STD)\n \t\t\t\t*speed = IXGBE_LINK_SPEED_5GB_FULL;\n \t\t}\ndiff --git a/drivers/net/ixgbe/base/ixgbe_e610.c b/drivers/net/ixgbe/base/ixgbe_e610.c\nindex a197c6274e..6618c21cef 100644\n--- a/drivers/net/ixgbe/base/ixgbe_e610.c\n+++ b/drivers/net/ixgbe/base/ixgbe_e610.c\n@@ -404,6 +404,79 @@ void ixgbe_fill_dflt_direct_cmd_desc(struct ixgbe_aci_desc *desc, u16 opcode)\n \tdesc->flags = IXGBE_CPU_TO_LE16(IXGBE_ACI_FLAG_SI);\n }\n \n+/**\n+ * ixgbe_aci_get_fw_ver - get the firmware version\n+ * @hw: pointer to the HW struct\n+ *\n+ * Get the firmware version using ACI command (0x0001).\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_aci_get_fw_ver(struct ixgbe_hw *hw)\n+{\n+\tstruct ixgbe_aci_cmd_get_ver *resp;\n+\tstruct ixgbe_aci_desc desc;\n+\ts32 status;\n+\n+\tresp = &desc.params.get_ver;\n+\n+\tixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_get_ver);\n+\n+\tstatus = ixgbe_aci_send_cmd(hw, &desc, NULL, 0);\n+\n+\tif (!status) {\n+\t\thw->fw_branch = resp->fw_branch;\n+\t\thw->fw_maj_ver = resp->fw_major;\n+\t\thw->fw_min_ver = resp->fw_minor;\n+\t\thw->fw_patch = resp->fw_patch;\n+\t\thw->fw_build = IXGBE_LE32_TO_CPU(resp->fw_build);\n+\t\thw->api_branch = resp->api_branch;\n+\t\thw->api_maj_ver = resp->api_major;\n+\t\thw->api_min_ver = resp->api_minor;\n+\t\thw->api_patch = resp->api_patch;\n+\t}\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ixgbe_aci_send_driver_ver - send the driver version to firmware\n+ * @hw: pointer to the HW struct\n+ * @dv: driver's major, minor version\n+ *\n+ * Send the driver version to the firmware\n+ * using the ACI command (0x0002).\n+ *\n+ * Return: the exit code of the operation.\n+ * Returns IXGBE_ERR_PARAM, if dv is NULL.\n+ */\n+s32 ixgbe_aci_send_driver_ver(struct ixgbe_hw *hw, struct ixgbe_driver_ver *dv)\n+{\n+\tstruct ixgbe_aci_cmd_driver_ver *cmd;\n+\tstruct ixgbe_aci_desc desc;\n+\tu16 len;\n+\n+\tcmd = &desc.params.driver_ver;\n+\n+\tif (!dv)\n+\t\treturn IXGBE_ERR_PARAM;\n+\n+\tixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_driver_ver);\n+\n+\tdesc.flags |= IXGBE_CPU_TO_LE16(IXGBE_ACI_FLAG_RD);\n+\tcmd->major_ver = dv->major_ver;\n+\tcmd->minor_ver = dv->minor_ver;\n+\tcmd->build_ver = dv->build_ver;\n+\tcmd->subbuild_ver = dv->subbuild_ver;\n+\n+\tlen = 0;\n+\twhile (len < sizeof(dv->driver_string) &&\n+\t IS_ASCII(dv->driver_string[len]) && dv->driver_string[len])\n+\t\tlen++;\n+\n+\treturn ixgbe_aci_send_cmd(hw, &desc, dv->driver_string, len);\n+}\n+\n /**\n * ixgbe_aci_req_res - request a common resource\n * @hw: pointer to the HW struct\n@@ -1823,6 +1896,300 @@ s32 ixgbe_nvm_validate_checksum(struct ixgbe_hw *hw)\n \treturn status;\n }\n \n+/**\n+ * ixgbe_get_flash_bank_offset - Get offset into requested flash bank\n+ * @hw: pointer to the HW structure\n+ * @bank: whether to read from the active or inactive flash bank\n+ * @module: the module to read from\n+ *\n+ * Based on the module, lookup the module offset from the beginning of the\n+ * flash.\n+ *\n+ * Return: the flash offset. Note that a value of zero is invalid and must be\n+ * treated as an error.\n+ */\n+static u32 ixgbe_get_flash_bank_offset(struct ixgbe_hw *hw,\n+\t\t\t\t enum ixgbe_bank_select bank,\n+\t\t\t\t u16 module)\n+{\n+\tstruct ixgbe_bank_info *banks = &hw->flash.banks;\n+\tenum ixgbe_flash_bank active_bank;\n+\tbool second_bank_active;\n+\tu32 offset, size;\n+\n+\tswitch (module) {\n+\tcase E610_SR_1ST_NVM_BANK_PTR:\n+\t\toffset = banks->nvm_ptr;\n+\t\tsize = banks->nvm_size;\n+\t\tactive_bank = banks->nvm_bank;\n+\t\tbreak;\n+\tcase E610_SR_1ST_OROM_BANK_PTR:\n+\t\toffset = banks->orom_ptr;\n+\t\tsize = banks->orom_size;\n+\t\tactive_bank = banks->orom_bank;\n+\t\tbreak;\n+\tcase E610_SR_NETLIST_BANK_PTR:\n+\t\toffset = banks->netlist_ptr;\n+\t\tsize = banks->netlist_size;\n+\t\tactive_bank = banks->netlist_bank;\n+\t\tbreak;\n+\tdefault:\n+\t\treturn 0;\n+\t}\n+\n+\tswitch (active_bank) {\n+\tcase IXGBE_1ST_FLASH_BANK:\n+\t\tsecond_bank_active = false;\n+\t\tbreak;\n+\tcase IXGBE_2ND_FLASH_BANK:\n+\t\tsecond_bank_active = true;\n+\t\tbreak;\n+\tdefault:\n+\t\treturn 0;\n+ }\n+\n+\t/* The second flash bank is stored immediately following the first\n+\t * bank. Based on whether the 1st or 2nd bank is active, and whether\n+\t * we want the active or inactive bank, calculate the desired offset.\n+\t */\n+\tswitch (bank) {\n+\tcase IXGBE_ACTIVE_FLASH_BANK:\n+\t\treturn offset + (second_bank_active ? size : 0);\n+\tcase IXGBE_INACTIVE_FLASH_BANK:\n+\t\treturn offset + (second_bank_active ? 0 : size);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * ixgbe_read_flash_module - Read a word from one of the main NVM modules\n+ * @hw: pointer to the HW structure\n+ * @bank: which bank of the module to read\n+ * @module: the module to read\n+ * @offset: the offset into the module in bytes\n+ * @data: storage for the word read from the flash\n+ * @length: bytes of data to read\n+ *\n+ * Read data from the specified flash module. The bank parameter indicates\n+ * whether or not to read from the active bank or the inactive bank of that\n+ * module.\n+ *\n+ * The word will be read using flat NVM access, and relies on the\n+ * hw->flash.banks data being setup by ixgbe_determine_active_flash_banks()\n+ * during initialization.\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+static s32 ixgbe_read_flash_module(struct ixgbe_hw *hw,\n+\t\t\t\t enum ixgbe_bank_select bank,\n+\t\t\t\t u16 module, u32 offset, u8 *data, u32 length)\n+{\n+\ts32 status;\n+\tu32 start;\n+\n+\tstart = ixgbe_get_flash_bank_offset(hw, bank, module);\n+\tif (!start) {\n+\t\treturn IXGBE_ERR_PARAM;\n+\t}\n+\n+\tstatus = ixgbe_acquire_nvm(hw, IXGBE_RES_READ);\n+\tif (status)\n+\t\treturn status;\n+\n+\tstatus = ixgbe_read_flat_nvm(hw, start + offset, &length, data, false);\n+\n+\tixgbe_release_nvm(hw);\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ixgbe_read_nvm_module - Read from the active main NVM module\n+ * @hw: pointer to the HW structure\n+ * @bank: whether to read from active or inactive NVM module\n+ * @offset: offset into the NVM module to read, in words\n+ * @data: storage for returned word value\n+ *\n+ * Read the specified word from the active NVM module. This includes the CSS\n+ * header at the start of the NVM module.\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+static s32 ixgbe_read_nvm_module(struct ixgbe_hw *hw,\n+\t\t\t\t enum ixgbe_bank_select bank,\n+\t\t\t\t u32 offset, u16 *data)\n+{\n+\t__le16 data_local;\n+\ts32 status;\n+\n+\tstatus = ixgbe_read_flash_module(hw, bank, E610_SR_1ST_NVM_BANK_PTR,\n+\t\t\t\t\t offset * sizeof(u16),\n+\t\t\t\t\t (u8 *)&data_local,\n+\t\t\t\t\t sizeof(u16));\n+\tif (!status)\n+\t\t*data = IXGBE_LE16_TO_CPU(data_local);\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ixgbe_get_nvm_css_hdr_len - Read the CSS header length from the\n+ * NVM CSS header\n+ * @hw: pointer to the HW struct\n+ * @bank: whether to read from the active or inactive flash bank\n+ * @hdr_len: storage for header length in words\n+ *\n+ * Read the CSS header length from the NVM CSS header and add the\n+ * Authentication header size, and then convert to words.\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+static s32 ixgbe_get_nvm_css_hdr_len(struct ixgbe_hw *hw,\n+\t\t\t\t enum ixgbe_bank_select bank,\n+\t\t\t\t u32 *hdr_len)\n+{\n+\tu16 hdr_len_l, hdr_len_h;\n+\tu32 hdr_len_dword;\n+\ts32 status;\n+\n+\tstatus = ixgbe_read_nvm_module(hw, bank, IXGBE_NVM_CSS_HDR_LEN_L,\n+\t\t\t\t &hdr_len_l);\n+\tif (status)\n+\t\treturn status;\n+\n+\tstatus = ixgbe_read_nvm_module(hw, bank, IXGBE_NVM_CSS_HDR_LEN_H,\n+\t\t\t\t &hdr_len_h);\n+\tif (status)\n+\t\treturn status;\n+\n+\t/* CSS header length is in DWORD, so convert to words and add\n+\t * authentication header size\n+\t */\n+\thdr_len_dword = hdr_len_h << 16 | hdr_len_l;\n+\t*hdr_len = (hdr_len_dword * 2) + IXGBE_NVM_AUTH_HEADER_LEN;\n+\n+\treturn IXGBE_SUCCESS;\n+}\n+\n+/**\n+ * ixgbe_read_nvm_sr_copy - Read a word from the Shadow RAM copy in the NVM bank\n+ * @hw: pointer to the HW structure\n+ * @bank: whether to read from the active or inactive NVM module\n+ * @offset: offset into the Shadow RAM copy to read, in words\n+ * @data: storage for returned word value\n+ *\n+ * Read the specified word from the copy of the Shadow RAM found in the\n+ * specified NVM module.\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+static s32 ixgbe_read_nvm_sr_copy(struct ixgbe_hw *hw,\n+\t\t\t\t enum ixgbe_bank_select bank,\n+\t\t\t\t u32 offset, u16 *data)\n+{\n+\tu32 hdr_len;\n+\ts32 status;\n+\n+\tstatus = ixgbe_get_nvm_css_hdr_len(hw, bank, &hdr_len);\n+\tif (status)\n+\t\treturn status;\n+\n+\thdr_len = ROUND_UP(hdr_len, 32);\n+\n+\treturn ixgbe_read_nvm_module(hw, bank, hdr_len + offset, data);\n+}\n+\n+/**\n+ * ixgbe_get_nvm_srev - Read the security revision from the NVM CSS header\n+ * @hw: pointer to the HW struct\n+ * @bank: whether to read from the active or inactive flash bank\n+ * @srev: storage for security revision\n+ *\n+ * Read the security revision out of the CSS header of the active NVM module\n+ * bank.\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+static s32 ixgbe_get_nvm_srev(struct ixgbe_hw *hw,\n+\t\t\t enum ixgbe_bank_select bank, u32 *srev)\n+{\n+\tu16 srev_l, srev_h;\n+\ts32 status;\n+\n+\tstatus = ixgbe_read_nvm_module(hw, bank, IXGBE_NVM_CSS_SREV_L, &srev_l);\n+\tif (status)\n+\t\treturn status;\n+\n+\tstatus = ixgbe_read_nvm_module(hw, bank, IXGBE_NVM_CSS_SREV_H, &srev_h);\n+\tif (status)\n+\t\treturn status;\n+\n+\t*srev = srev_h << 16 | srev_l;\n+\n+\treturn IXGBE_SUCCESS;\n+}\n+\n+/**\n+ * ixgbe_get_nvm_ver_info - Read NVM version information\n+ * @hw: pointer to the HW struct\n+ * @bank: whether to read from the active or inactive flash bank\n+ * @nvm: pointer to NVM info structure\n+ *\n+ * Read the NVM EETRACK ID and map version of the main NVM image bank, filling\n+ * in the nvm info structure.\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+static s32 ixgbe_get_nvm_ver_info(struct ixgbe_hw *hw,\n+\t\t\t\t enum ixgbe_bank_select bank,\n+\t\t\t\t struct ixgbe_nvm_info *nvm)\n+{\n+\tu16 eetrack_lo, eetrack_hi, ver;\n+\ts32 status;\n+\n+\tstatus = ixgbe_read_nvm_sr_copy(hw, bank,\n+\t\t\t\t\tE610_SR_NVM_DEV_STARTER_VER, &ver);\n+\tif (status) {\n+\t\treturn status;\n+\t}\n+\n+\tnvm->major = (ver & E610_NVM_VER_HI_MASK) >> E610_NVM_VER_HI_SHIFT;\n+\tnvm->minor = (ver & E610_NVM_VER_LO_MASK) >> E610_NVM_VER_LO_SHIFT;\n+\n+\tstatus = ixgbe_read_nvm_sr_copy(hw, bank, E610_SR_NVM_EETRACK_LO,\n+\t\t\t\t\t&eetrack_lo);\n+\tif (status) {\n+\t\treturn status;\n+\t}\n+\tstatus = ixgbe_read_nvm_sr_copy(hw, bank, E610_SR_NVM_EETRACK_HI,\n+\t\t\t\t\t&eetrack_hi);\n+\tif (status) {\n+\t\treturn status;\n+\t}\n+\n+\tnvm->eetrack = (eetrack_hi << 16) | eetrack_lo;\n+\n+\tstatus = ixgbe_get_nvm_srev(hw, bank, &nvm->srev);\n+\n+\treturn IXGBE_SUCCESS;\n+}\n+\n+/**\n+ * ixgbe_get_active_nvm_ver - Read Option ROM version from the active bank\n+ * @hw: pointer to the HW structure\n+ * @nvm: storage for Option ROM version information\n+ *\n+ * Reads the NVM EETRACK ID, Map version, and security revision of the\n+ * active NVM bank.\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_get_active_nvm_ver(struct ixgbe_hw *hw, struct ixgbe_nvm_info *nvm)\n+{\n+\treturn ixgbe_get_nvm_ver_info(hw, IXGBE_ACTIVE_FLASH_BANK, nvm);\n+}\n+\n /**\n * ixgbe_read_sr_word_aci - Reads Shadow RAM via ACI\n * @hw: pointer to the HW structure\n@@ -1848,6 +2215,34 @@ s32 ixgbe_read_sr_word_aci(struct ixgbe_hw *hw, u16 offset, u16 *data)\n \treturn IXGBE_SUCCESS;\n }\n \n+/**\n+ * ixgbe_read_sr_buf_aci - Reads Shadow RAM buf via ACI\n+ * @hw: pointer to the HW structure\n+ * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)\n+ * @words: (in) number of words to read; (out) number of words actually read\n+ * @data: words read from the Shadow RAM\n+ *\n+ * Reads 16 bit words (data buf) from the Shadow RAM. Ownership of the NVM is\n+ * taken before reading the buffer and later released.\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_read_sr_buf_aci(struct ixgbe_hw *hw, u16 offset, u16 *words,\n+\t\t\t u16 *data)\n+{\n+\tu32 bytes = *words * 2, i;\n+\ts32 status;\n+\n+\tstatus = ixgbe_read_flat_nvm(hw, offset * 2, &bytes, (u8 *)data, true);\n+\n+\t*words = bytes / 2;\n+\n+\tfor (i = 0; i < *words; i++)\n+\t\tdata[i] = IXGBE_LE16_TO_CPU(((__le16 *)data)[i]);\n+\n+\treturn status;\n+}\n+\n /**\n * ixgbe_read_flat_nvm - Read portion of NVM by flat offset\n * @hw: pointer to the HW struct\n@@ -1915,6 +2310,213 @@ s32 ixgbe_read_flat_nvm(struct ixgbe_hw *hw, u32 offset, u32 *length,\n \treturn status;\n }\n \n+/**\n+ * ixgbe_init_ops_E610 - Inits func ptrs and MAC type\n+ * @hw: pointer to hardware structure\n+ *\n+ * Initialize the function pointers and assign the MAC type for E610.\n+ * Does not touch the hardware.\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_init_ops_E610(struct ixgbe_hw *hw)\n+{\n+\tstruct ixgbe_eeprom_info *eeprom = &hw->eeprom;\n+\tstruct ixgbe_mac_info *mac = &hw->mac;\n+\tstruct ixgbe_phy_info *phy = &hw->phy;\n+\ts32 ret_val;\n+\n+\tret_val = ixgbe_init_ops_X550(hw);\n+\t/* TODO Additional ops overrides for e610 to go here */\n+\n+\t/* MAC */\n+\tmac->ops.reset_hw = ixgbe_reset_hw_E610;\n+\tmac->ops.start_hw = ixgbe_start_hw_E610;\n+\tmac->ops.get_media_type = ixgbe_get_media_type_E610;\n+\tmac->ops.get_supported_physical_layer =\n+\t\tixgbe_get_supported_physical_layer_E610;\n+\tmac->ops.get_san_mac_addr = NULL;\n+\tmac->ops.set_san_mac_addr = NULL;\n+\tmac->ops.get_wwn_prefix = NULL;\n+\tmac->ops.setup_link = ixgbe_setup_link_E610;\n+\tmac->ops.check_link = ixgbe_check_link_E610;\n+\tmac->ops.get_link_capabilities = ixgbe_get_link_capabilities_E610;\n+\tmac->ops.setup_fc = ixgbe_setup_fc_E610;\n+\tmac->ops.fc_autoneg = ixgbe_fc_autoneg_E610;\n+\tmac->ops.set_fw_drv_ver = ixgbe_set_fw_drv_ver_E610;\n+\tmac->ops.disable_rx = ixgbe_disable_rx_E610;\n+\tmac->ops.setup_eee = ixgbe_setup_eee_E610;\n+\tmac->ops.fw_recovery_mode = ixgbe_fw_recovery_mode_E610;\n+\tmac->ops.get_fw_tsam_mode = ixgbe_get_fw_tsam_mode_E610;\n+\tmac->ops.get_fw_version = ixgbe_aci_get_fw_ver;\n+\tmac->ops.get_nvm_version = ixgbe_get_active_nvm_ver;\n+\n+\t/* PHY */\n+\tphy->ops.init = ixgbe_init_phy_ops_E610;\n+\tphy->ops.identify = ixgbe_identify_phy_E610;\n+\tphy->eee_speeds_supported = IXGBE_LINK_SPEED_10_FULL |\n+\t\t\t\t IXGBE_LINK_SPEED_100_FULL |\n+\t\t\t\t IXGBE_LINK_SPEED_1GB_FULL;\n+\tphy->eee_speeds_advertised = phy->eee_speeds_supported;\n+\n+\t/* Additional ops overrides for e610 to go here */\n+\teeprom->ops.init_params = ixgbe_init_eeprom_params_E610;\n+\teeprom->ops.read = ixgbe_read_ee_aci_E610;\n+\teeprom->ops.read_buffer = ixgbe_read_ee_aci_buffer_E610;\n+\teeprom->ops.write = NULL;\n+\teeprom->ops.write_buffer = NULL;\n+\teeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_E610;\n+\teeprom->ops.update_checksum = NULL;\n+\teeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_E610;\n+\teeprom->ops.read_pba_string = ixgbe_read_pba_string_E610;\n+\n+\t/* Initialize bus function number */\n+\thw->mac.ops.set_lan_id(hw);\n+\n+\treturn ret_val;\n+}\n+\n+/**\n+ * ixgbe_reset_hw_E610 - Perform hardware reset\n+ * @hw: pointer to hardware structure\n+ *\n+ * Resets the hardware by resetting the transmit and receive units, masks\n+ * and clears all interrupts, and perform a reset.\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_reset_hw_E610(struct ixgbe_hw *hw)\n+{\n+\tu32 swfw_mask = hw->phy.phy_semaphore_mask;\n+\tu32 ctrl, i;\n+\ts32 status;\n+\n+\tDEBUGFUNC(\"ixgbe_reset_hw_E610\");\n+\n+\t/* Call adapter stop to disable tx/rx and clear interrupts */\n+\tstatus = hw->mac.ops.stop_adapter(hw);\n+\tif (status != IXGBE_SUCCESS)\n+\t\tgoto reset_hw_out;\n+\n+\t/* flush pending Tx transactions */\n+\tixgbe_clear_tx_pending(hw);\n+\n+\tstatus = hw->phy.ops.init(hw);\n+\tif (status != IXGBE_SUCCESS)\n+\t\tDEBUGOUT1(\"Failed to initialize PHY ops, STATUS = %d\\n\",\n+\t\t\t status);\n+mac_reset_top:\n+\tstatus = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);\n+\tif (status != IXGBE_SUCCESS) {\n+\t\tERROR_REPORT2(IXGBE_ERROR_CAUTION,\n+\t\t\t \"semaphore failed with %d\", status);\n+\t\treturn IXGBE_ERR_SWFW_SYNC;\n+\t}\n+\tctrl = IXGBE_CTRL_RST;\n+\tctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);\n+\tIXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);\n+\tIXGBE_WRITE_FLUSH(hw);\n+\thw->mac.ops.release_swfw_sync(hw, swfw_mask);\n+\n+\t/* Poll for reset bit to self-clear indicating reset is complete */\n+\tfor (i = 0; i < 10; i++) {\n+\t\tusec_delay(1);\n+\t\tctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);\n+\t\tif (!(ctrl & IXGBE_CTRL_RST_MASK))\n+\t\t\tbreak;\n+\t}\n+\n+\tif (ctrl & IXGBE_CTRL_RST_MASK) {\n+\t\tstatus = IXGBE_ERR_RESET_FAILED;\n+\t\tERROR_REPORT1(IXGBE_ERROR_POLLING,\n+\t\t\t \"Reset polling failed to complete.\\n\");\n+\t}\n+\tmsec_delay(100);\n+\n+\t/*\n+\t * Double resets are required for recovery from certain error\n+\t * conditions. Between resets, it is necessary to stall to allow time\n+\t * for any pending HW events to complete.\n+\t */\n+\tif (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {\n+\t\thw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;\n+\t\tgoto mac_reset_top;\n+\t}\n+\n+\t/* Set the Rx packet buffer size. */\n+\tIXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), 384 << IXGBE_RXPBSIZE_SHIFT);\n+\n+\t/* Store the permanent mac address */\n+\thw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);\n+\n+\t/*\n+\t * Store MAC address from RAR0, clear receive address registers, and\n+\t * clear the multicast table. Also reset num_rar_entries to 128,\n+\t * since we modify this value when programming the SAN MAC address.\n+\t */\n+\thw->mac.num_rar_entries = 128;\n+\thw->mac.ops.init_rx_addrs(hw);\n+\n+reset_hw_out:\n+\treturn status;\n+}\n+/**\n+ * ixgbe_fw_ver_check - Check the reported FW API version\n+ * @hw: pointer to the hardware structure\n+ *\n+ * Checks if the driver should load on a given FW API version.\n+ *\n+ * Return: 'true' if the driver should attempt to load. 'false' otherwise.\n+ */\n+static bool ixgbe_fw_ver_check(struct ixgbe_hw *hw)\n+{\n+\tif (hw->api_maj_ver > IXGBE_FW_API_VER_MAJOR) {\n+\t\tERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED, \"The driver for the device stopped because the NVM image is newer than expected. You must install the most recent version of the network driver.\\n\");\n+\t\treturn false;\n+\t} else if (hw->api_maj_ver == IXGBE_FW_API_VER_MAJOR) {\n+\t\tif (hw->api_min_ver >\n+\t\t (IXGBE_FW_API_VER_MINOR + IXGBE_FW_API_VER_DIFF_ALLOWED)) {\n+\t\t\tERROR_REPORT1(IXGBE_ERROR_CAUTION, \"The driver for the device detected a newer version of the NVM image than expected. Please install the most recent version of the network driver.\\n\");\n+\t\t} else if ((hw->api_min_ver + IXGBE_FW_API_VER_DIFF_ALLOWED) <\n+\t\t\t IXGBE_FW_API_VER_MINOR) {\n+\t\t\tERROR_REPORT1(IXGBE_ERROR_CAUTION, \"The driver for the device detected an older version of the NVM image than expected. Please update the NVM image.\\n\");\n+\t\t}\n+\t} else {\n+\t\tERROR_REPORT1(IXGBE_ERROR_CAUTION, \"The driver for the device detected an older version of the NVM image than expected. Please update the NVM image.\\n\");\n+\t}\n+\treturn true;\n+}\n+/**\n+ * ixgbe_start_hw_E610 - Prepare hardware for Tx/Rx\n+ * @hw: pointer to hardware structure\n+ *\n+ * Gets firmware version and if API version matches it\n+ * starts the hardware using the generic start_hw function\n+ * and the generation start_hw function.\n+ * Then performs revision-specific operations, if any.\n+ **/\n+s32 ixgbe_start_hw_E610(struct ixgbe_hw *hw)\n+{\n+\ts32 ret_val = IXGBE_SUCCESS;\n+\n+\tret_val = hw->mac.ops.get_fw_version(hw);\n+\tif (ret_val)\n+\t\tgoto out;\n+\n+\tif (!ixgbe_fw_ver_check(hw)) {\n+\t\tret_val = IXGBE_ERR_FW_API_VER;\n+\t\tgoto out;\n+\t}\n+\tret_val = ixgbe_start_hw_generic(hw);\n+\tif (ret_val != IXGBE_SUCCESS)\n+\t\tgoto out;\n+\n+\tixgbe_start_hw_gen2(hw);\n+\n+out:\n+\treturn ret_val;\n+}\n+\n /**\n * ixgbe_get_media_type_E610 - Gets media type\n * @hw: pointer to the HW struct\n@@ -1985,6 +2587,57 @@ enum ixgbe_media_type ixgbe_get_media_type_E610(struct ixgbe_hw *hw)\n \treturn hw->phy.media_type;\n }\n \n+/**\n+ * ixgbe_get_supported_physical_layer_E610 - Returns physical layer type\n+ * @hw: pointer to hardware structure\n+ *\n+ * Determines physical layer capabilities of the current configuration.\n+ *\n+ * Return: the exit code of the operation.\n+ **/\n+u64 ixgbe_get_supported_physical_layer_E610(struct ixgbe_hw *hw)\n+{\n+\tu64 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;\n+\tstruct ixgbe_aci_cmd_get_phy_caps_data pcaps;\n+\tu64 phy_type;\n+\ts32 rc;\n+\n+\trc = ixgbe_aci_get_phy_caps(hw, false, IXGBE_ACI_REPORT_TOPO_CAP_MEDIA,\n+\t\t\t\t &pcaps);\n+\tif (rc)\n+\t\treturn IXGBE_PHYSICAL_LAYER_UNKNOWN;\n+\n+\tphy_type = IXGBE_LE64_TO_CPU(pcaps.phy_type_low);\n+\tif(phy_type & IXGBE_PHY_TYPE_LOW_10GBASE_T)\n+\t\tphysical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;\n+\tif(phy_type & IXGBE_PHY_TYPE_LOW_1000BASE_T)\n+\t\tphysical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;\n+\tif(phy_type & IXGBE_PHY_TYPE_LOW_100BASE_TX)\n+\t\tphysical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;\n+\tif(phy_type & IXGBE_PHY_TYPE_LOW_10GBASE_LR)\n+\t\tphysical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_LR;\n+\tif(phy_type & IXGBE_PHY_TYPE_LOW_10GBASE_SR)\n+\t\tphysical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_SR;\n+\tif(phy_type & IXGBE_PHY_TYPE_LOW_1000BASE_KX)\n+\t\tphysical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;\n+\tif(phy_type & IXGBE_PHY_TYPE_LOW_10GBASE_KR_CR1)\n+\t\tphysical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR;\n+\tif(phy_type & IXGBE_PHY_TYPE_LOW_1000BASE_SX)\n+\t\tphysical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_SX;\n+\tif(phy_type & IXGBE_PHY_TYPE_LOW_2500BASE_KX)\n+\t\tphysical_layer |= IXGBE_PHYSICAL_LAYER_2500BASE_KX;\n+\tif(phy_type & IXGBE_PHY_TYPE_LOW_2500BASE_T)\n+\t\tphysical_layer |= IXGBE_PHYSICAL_LAYER_2500BASE_T;\n+\tif(phy_type & IXGBE_PHY_TYPE_LOW_5GBASE_T)\n+\t\tphysical_layer |= IXGBE_PHYSICAL_LAYER_5000BASE_T;\n+\n+\tphy_type = IXGBE_LE64_TO_CPU(pcaps.phy_type_high);\n+\tif(phy_type & IXGBE_PHY_TYPE_HIGH_10BASE_T)\n+\t\tphysical_layer |= IXGBE_PHYSICAL_LAYER_10BASE_T;\n+\n+\treturn physical_layer;\n+}\n+\n /**\n * ixgbe_setup_link_E610 - Set up link\n * @hw: pointer to hardware structure\n@@ -2253,6 +2906,47 @@ void ixgbe_fc_autoneg_E610(struct ixgbe_hw *hw)\n \t}\n }\n \n+/**\n+ * ixgbe_set_fw_drv_ver_E610 - Send driver version to FW\n+ * @hw: pointer to the HW structure\n+ * @maj: driver version major number\n+ * @minor: driver version minor number\n+ * @build: driver version build number\n+ * @sub: driver version sub build number\n+ * @len: length of driver_ver string\n+ * @driver_ver: driver string\n+ *\n+ * Send driver version number to Firmware using ACI command (0x0002).\n+ *\n+ * Return: the exit code of the operation.\n+ * IXGBE_SUCCESS - OK\n+ * IXGBE_ERR_PARAM - incorrect parameters were given\n+ * IXGBE_ERR_ACI_ERROR - encountered an error during sending the command\n+ * IXGBE_ERR_ACI_TIMEOUT - a timeout occurred\n+ * IXGBE_ERR_OUT_OF_MEM - ran out of memory\n+ */\n+s32 ixgbe_set_fw_drv_ver_E610(struct ixgbe_hw *hw, u8 maj, u8 minor, u8 build,\n+\t\t\t u8 sub, u16 len, const char *driver_ver)\n+{\n+\tsize_t limited_len = min(len, (u16)IXGBE_DRV_VER_STR_LEN_E610);\n+\tstruct ixgbe_driver_ver dv;\n+\n+\tDEBUGFUNC(\"ixgbe_set_fw_drv_ver_E610\");\n+\n+\tif (!len || !driver_ver)\n+\t\treturn IXGBE_ERR_PARAM;\n+\n+\tdv.major_ver = maj;\n+\tdv.minor_ver = minor;\n+\tdv.build_ver = build;\n+\tdv.subbuild_ver = sub;\n+\n+\tmemset(dv.driver_string, 0, IXGBE_DRV_VER_STR_LEN_E610);\n+\tmemcpy(dv.driver_string, driver_ver, limited_len);\n+\n+\treturn ixgbe_aci_send_driver_ver(hw, &dv);\n+}\n+\n /**\n * ixgbe_disable_rx_E610 - Disable RX unit\n * @hw: pointer to hardware structure\n@@ -2294,6 +2988,92 @@ void ixgbe_disable_rx_E610(struct ixgbe_hw *hw)\n \t}\n }\n \n+/**\n+ * ixgbe_setup_eee_E610 - Enable/disable EEE support\n+ * @hw: pointer to the HW structure\n+ * @enable_eee: boolean flag to enable EEE\n+ *\n+ * Enables/disable EEE based on enable_eee flag.\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_setup_eee_E610(struct ixgbe_hw *hw, bool enable_eee)\n+{\n+\tstruct ixgbe_aci_cmd_get_phy_caps_data phy_caps = { 0 };\n+\tstruct ixgbe_aci_cmd_set_phy_cfg_data phy_cfg = { 0 };\n+\tu16 eee_cap = 0;\n+\ts32 status;\n+\n+\tstatus = ixgbe_aci_get_phy_caps(hw, false,\n+\t\tIXGBE_ACI_REPORT_ACTIVE_CFG, &phy_caps);\n+\tif (status != IXGBE_SUCCESS)\n+\t\treturn status;\n+\n+\tixgbe_copy_phy_caps_to_cfg(&phy_caps, &phy_cfg);\n+\n+\tphy_cfg.caps |= IXGBE_ACI_PHY_ENA_LINK;\n+\tphy_cfg.caps |= IXGBE_ACI_PHY_ENA_AUTO_LINK_UPDT;\n+\n+\tif (enable_eee) {\n+\t\tif (phy_caps.phy_type_low & IXGBE_PHY_TYPE_LOW_100BASE_TX)\n+\t\t\teee_cap |= IXGBE_ACI_PHY_EEE_EN_100BASE_TX;\n+\t\tif (phy_caps.phy_type_low & IXGBE_PHY_TYPE_LOW_1000BASE_T)\n+\t\t\teee_cap |= IXGBE_ACI_PHY_EEE_EN_1000BASE_T;\n+\t\tif (phy_caps.phy_type_low & IXGBE_PHY_TYPE_LOW_1000BASE_KX)\n+\t\t\teee_cap |= IXGBE_ACI_PHY_EEE_EN_1000BASE_KX;\n+\t\tif (phy_caps.phy_type_low & IXGBE_PHY_TYPE_LOW_10GBASE_T)\n+\t\t\teee_cap |= IXGBE_ACI_PHY_EEE_EN_10GBASE_T;\n+\t\tif (phy_caps.phy_type_low & IXGBE_PHY_TYPE_LOW_10GBASE_KR_CR1)\n+\t\t\teee_cap |= IXGBE_ACI_PHY_EEE_EN_10GBASE_KR;\n+\t\tif (phy_caps.phy_type_low & IXGBE_PHY_TYPE_LOW_25GBASE_KR ||\n+\t\t phy_caps.phy_type_low & IXGBE_PHY_TYPE_LOW_25GBASE_KR_S ||\n+\t\t phy_caps.phy_type_low & IXGBE_PHY_TYPE_LOW_25GBASE_KR1)\n+\t\t\teee_cap |= IXGBE_ACI_PHY_EEE_EN_25GBASE_KR;\n+\n+\t\tif (phy_caps.phy_type_high & IXGBE_PHY_TYPE_HIGH_10BASE_T)\n+\t\t\teee_cap |= IXGBE_ACI_PHY_EEE_EN_10BASE_T;\n+\t}\n+\n+\t/* Set EEE capability for particular PHY types */\n+\tphy_cfg.eee_cap = IXGBE_CPU_TO_LE16(eee_cap);\n+\n+\tstatus = ixgbe_aci_set_phy_cfg(hw, &phy_cfg);\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ixgbe_fw_recovery_mode_E610 - Check FW NVM recovery mode\n+ * @hw: pointer to hardware structure\n+ *\n+ * Checks FW NVM recovery mode by\n+ * reading the value of the dedicated register.\n+ *\n+ * Return: true if FW is in recovery mode, otherwise false.\n+ */\n+bool ixgbe_fw_recovery_mode_E610(struct ixgbe_hw *hw)\n+{\n+\tu32 fwsm = IXGBE_READ_REG(hw, GL_MNG_FWSM);\n+\n+\treturn !!(fwsm & GL_MNG_FWSM_FW_MODES_RECOVERY_M);\n+}\n+\n+/**\n+ * ixgbe_get_fw_tsam_mode_E610 - Check FW NVM Thermal Sensor Autonomous Mode\n+ * @hw: pointer to hardware structure\n+ *\n+ * Checks Thermal Sensor Autonomous Mode by reading the\n+ * value of the dedicated register.\n+ *\n+ * Return: true if FW is in TSAM, otherwise false.\n+ */\n+bool ixgbe_get_fw_tsam_mode_E610(struct ixgbe_hw *hw)\n+{\n+\tu32 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM_X550EM_a);\n+\n+\treturn !!(fwsm & IXGBE_FWSM_TS_ENABLED);\n+}\n+\n /**\n * ixgbe_init_phy_ops_E610 - PHY specific init\n * @hw: pointer to hardware structure\n@@ -2757,6 +3537,38 @@ s32 ixgbe_enter_lplu_E610(struct ixgbe_hw *hw)\n \treturn status;\n }\n \n+/**\n+ * ixgbe_init_eeprom_params_E610 - Initialize EEPROM params\n+ * @hw: pointer to hardware structure\n+ *\n+ * Initializes the EEPROM parameters ixgbe_eeprom_info within the\n+ * ixgbe_hw struct in order to set up EEPROM access.\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_init_eeprom_params_E610(struct ixgbe_hw *hw)\n+{\n+\tstruct ixgbe_eeprom_info *eeprom = &hw->eeprom;\n+\tu32 gens_stat;\n+\tu8 sr_size;\n+\n+\tif (eeprom->type == ixgbe_eeprom_uninitialized) {\n+\t\teeprom->type = ixgbe_flash;\n+\n+\t\tgens_stat = IXGBE_READ_REG(hw, GLNVM_GENS);\n+\t\tsr_size = (gens_stat & GLNVM_GENS_SR_SIZE_M) >>\n+\t\t\t GLNVM_GENS_SR_SIZE_S;\n+\n+\t\t/* Switching to words (sr_size contains power of 2) */\n+\t\teeprom->word_size = BIT(sr_size) * IXGBE_SR_WORDS_IN_1KB;\n+\n+\t\tDEBUGOUT2(\"Eeprom params: type = %d, size = %d\\n\",\n+\t\t\t eeprom->type, eeprom->word_size);\n+\t}\n+\n+\treturn IXGBE_SUCCESS;\n+}\n+\n /**\n * ixgbe_read_ee_aci_E610 - Read EEPROM word using the admin command.\n * @hw: pointer to hardware structure\n@@ -2790,6 +3602,134 @@ s32 ixgbe_read_ee_aci_E610(struct ixgbe_hw *hw, u16 offset, u16 *data)\n \treturn status;\n }\n \n+/**\n+ * ixgbe_read_ee_aci_buffer_E610- Read EEPROM word(s) using admin commands.\n+ * @hw: pointer to hardware structure\n+ * @offset: offset of word in the EEPROM to read\n+ * @words: number of words\n+ * @data: word(s) read from the EEPROM\n+ *\n+ * Reads a 16 bit word(s) from the EEPROM using the ACI.\n+ * If the EEPROM params are not initialized, the function\n+ * initialize them before proceeding with reading.\n+ * The function acquires and then releases the NVM ownership.\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_read_ee_aci_buffer_E610(struct ixgbe_hw *hw, u16 offset,\n+\t\t\t\t u16 words, u16 *data)\n+{\n+\ts32 status;\n+\n+\tif (hw->eeprom.type == ixgbe_eeprom_uninitialized) {\n+\t\tstatus = ixgbe_init_eeprom_params(hw);\n+\t\tif (status)\n+\t\t\treturn status;\n+\t}\n+\n+\tstatus = ixgbe_acquire_nvm(hw, IXGBE_RES_READ);\n+\tif (status)\n+\t\treturn status;\n+\n+\tstatus = ixgbe_read_sr_buf_aci(hw, offset, &words, data);\n+\tixgbe_release_nvm(hw);\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ixgbe_calc_eeprom_checksum_E610 - Calculates and returns the checksum\n+ * @hw: pointer to hardware structure\n+ *\n+ * Calculate SW Checksum that covers the whole 64kB shadow RAM\n+ * except the VPD and PCIe ALT Auto-load modules. The structure and size of VPD\n+ * is customer specific and unknown. Therefore, this function skips all maximum\n+ * possible size of VPD (1kB).\n+ * If the EEPROM params are not initialized, the function\n+ * initializes them before proceeding.\n+ * The function acquires and then releases the NVM ownership.\n+ *\n+ * Return: the negative error code on error, or the 16-bit checksum\n+ */\n+s32 ixgbe_calc_eeprom_checksum_E610(struct ixgbe_hw *hw)\n+{\n+\tbool nvm_acquired = false;\n+\tu16 pcie_alt_module = 0;\n+\tu16 checksum_local = 0;\n+\tu16 checksum = 0;\n+\tu16 vpd_module;\n+\tvoid *vmem;\n+\ts32 status;\n+\tu16 *data;\n+\tu16 i;\n+\n+\tif (hw->eeprom.type == ixgbe_eeprom_uninitialized) {\n+\t\tstatus = ixgbe_init_eeprom_params(hw);\n+\t\tif (status)\n+\t\t\treturn status;\n+\t}\n+\n+\tvmem = ixgbe_calloc(hw, IXGBE_SR_SECTOR_SIZE_IN_WORDS, sizeof(u16));\n+\tif (!vmem)\n+\t\treturn IXGBE_ERR_OUT_OF_MEM;\n+\tdata = (u16 *)vmem;\n+\tstatus = ixgbe_acquire_nvm(hw, IXGBE_RES_READ);\n+\tif (status)\n+\t\tgoto ixgbe_calc_sr_checksum_exit;\n+\tnvm_acquired = true;\n+\n+\t/* read pointer to VPD area */\n+\tstatus = ixgbe_read_sr_word_aci(hw, E610_SR_VPD_PTR, &vpd_module);\n+\tif (status)\n+\t\tgoto ixgbe_calc_sr_checksum_exit;\n+\n+\t/* read pointer to PCIe Alt Auto-load module */\n+\tstatus = ixgbe_read_sr_word_aci(hw, E610_SR_PCIE_ALT_AUTO_LOAD_PTR,\n+\t\t\t\t\t&pcie_alt_module);\n+\tif (status)\n+\t\tgoto ixgbe_calc_sr_checksum_exit;\n+\n+\t/* Calculate SW checksum that covers the whole 64kB shadow RAM\n+\t * except the VPD and PCIe ALT Auto-load modules\n+\t */\n+\tfor (i = 0; i < hw->eeprom.word_size; i++) {\n+\t\t/* Read SR page */\n+\t\tif ((i % IXGBE_SR_SECTOR_SIZE_IN_WORDS) == 0) {\n+\t\t\tu16 words = IXGBE_SR_SECTOR_SIZE_IN_WORDS;\n+\n+\t\t\tstatus = ixgbe_read_sr_buf_aci(hw, i, &words, data);\n+\t\t\tif (status != IXGBE_SUCCESS)\n+\t\t\t\tgoto ixgbe_calc_sr_checksum_exit;\n+\t\t}\n+\n+\t\t/* Skip Checksum word */\n+\t\tif (i == E610_SR_SW_CHECKSUM_WORD)\n+\t\t\tcontinue;\n+\t\t/* Skip VPD module (convert byte size to word count) */\n+\t\tif (i >= (u32)vpd_module &&\n+\t\t i < ((u32)vpd_module + E610_SR_VPD_SIZE_WORDS))\n+\t\t\tcontinue;\n+\t\t/* Skip PCIe ALT module (convert byte size to word count) */\n+\t\tif (i >= (u32)pcie_alt_module &&\n+\t\t i < ((u32)pcie_alt_module + E610_SR_PCIE_ALT_SIZE_WORDS))\n+\t\t\tcontinue;\n+\n+\t\tchecksum_local += data[i % IXGBE_SR_SECTOR_SIZE_IN_WORDS];\n+\t}\n+\n+\tchecksum = (u16)IXGBE_SR_SW_CHECKSUM_BASE - checksum_local;\n+\n+ixgbe_calc_sr_checksum_exit:\n+\tif(nvm_acquired)\n+\t\tixgbe_release_nvm(hw);\n+\tixgbe_free(hw, vmem);\n+\n+\tif(!status)\n+\t\treturn (s32)checksum;\n+\telse\n+\t\treturn status;\n+}\n+\n /**\n * ixgbe_validate_eeprom_checksum_E610 - Validate EEPROM checksum\n * @hw: pointer to hardware structure\n@@ -2834,3 +3774,124 @@ s32 ixgbe_validate_eeprom_checksum_E610(struct ixgbe_hw *hw, u16 *checksum_val)\n \n \treturn status;\n }\n+\n+/**\n+ * ixgbe_get_pfa_module_tlv - Reads sub module TLV from NVM PFA\n+ * @hw: pointer to hardware structure\n+ * @module_tlv: pointer to module TLV to return\n+ * @module_tlv_len: pointer to module TLV length to return\n+ * @module_type: module type requested\n+ *\n+ * Finds the requested sub module TLV type from the Preserved Field\n+ * Area (PFA) and returns the TLV pointer and length. The caller can\n+ * use these to read the variable length TLV value.\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+STATIC s32 ixgbe_get_pfa_module_tlv(struct ixgbe_hw *hw, u16 *module_tlv,\n+\t\t\t\t u16 *module_tlv_len, u16 module_type)\n+{\n+\tu16 pfa_len, pfa_ptr, pfa_end_ptr;\n+\tu16 next_tlv;\n+\ts32 status;\n+\n+\tstatus = ixgbe_read_ee_aci_E610(hw, E610_SR_PFA_PTR, &pfa_ptr);\n+\tif (status != IXGBE_SUCCESS) {\n+\t\treturn status;\n+\t}\n+\tstatus = ixgbe_read_ee_aci_E610(hw, pfa_ptr, &pfa_len);\n+\tif (status != IXGBE_SUCCESS) {\n+\t\treturn status;\n+\t}\n+\t/* Starting with first TLV after PFA length, iterate through the list\n+\t * of TLVs to find the requested one.\n+\t */\n+\tnext_tlv = pfa_ptr + 1;\n+\tpfa_end_ptr = pfa_ptr + pfa_len;\n+\twhile (next_tlv < pfa_end_ptr) {\n+\t\tu16 tlv_sub_module_type, tlv_len;\n+\n+\t\t/* Read TLV type */\n+\t\tstatus = ixgbe_read_ee_aci_E610(hw, next_tlv,\n+\t\t\t\t\t\t&tlv_sub_module_type);\n+\t\tif (status != IXGBE_SUCCESS) {\n+\t\t\tbreak;\n+\t\t}\n+\t\t/* Read TLV length */\n+\t\tstatus = ixgbe_read_ee_aci_E610(hw, next_tlv + 1, &tlv_len);\n+\t\tif (status != IXGBE_SUCCESS) {\n+\t\t\tbreak;\n+\t\t}\n+\t\tif (tlv_sub_module_type == module_type) {\n+\t\t\tif (tlv_len) {\n+\t\t\t\t*module_tlv = next_tlv;\n+\t\t\t\t*module_tlv_len = tlv_len;\n+\t\t\t\treturn IXGBE_SUCCESS;\n+\t\t\t}\n+\t\t\treturn IXGBE_ERR_INVAL_SIZE;\n+\t\t}\n+\t\t/* Check next TLV, i.e. current TLV pointer + length + 2 words\n+\t\t * (for current TLV's type and length)\n+\t\t */\n+\t\tnext_tlv = next_tlv + tlv_len + 2;\n+\t}\n+\t/* Module does not exist */\n+\treturn IXGBE_ERR_DOES_NOT_EXIST;\n+}\n+\n+/**\n+ * ixgbe_read_pba_string_E610 - Reads part number string from NVM\n+ * @hw: pointer to hardware structure\n+ * @pba_num: stores the part number string from the NVM\n+ * @pba_num_size: part number string buffer length\n+ *\n+ * Reads the part number string from the NVM.\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_read_pba_string_E610(struct ixgbe_hw *hw, u8 *pba_num,\n+\t\t\t u32 pba_num_size)\n+{\n+\tu16 pba_tlv, pba_tlv_len;\n+\tu16 pba_word, pba_size;\n+\ts32 status;\n+\tu16 i;\n+\n+\tstatus = ixgbe_get_pfa_module_tlv(hw, &pba_tlv, &pba_tlv_len,\n+\t\t\t\t\tE610_SR_PBA_BLOCK_PTR);\n+\tif (status != IXGBE_SUCCESS) {\n+\t\treturn status;\n+\t}\n+\n+\t/* pba_size is the next word */\n+\tstatus = ixgbe_read_ee_aci_E610(hw, (pba_tlv + 2), &pba_size);\n+\tif (status != IXGBE_SUCCESS) {\n+\t\treturn status;\n+\t}\n+\n+\tif (pba_tlv_len < pba_size) {\n+\t\treturn IXGBE_ERR_INVAL_SIZE;\n+\t}\n+\n+\t/* Subtract one to get PBA word count (PBA Size word is included in\n+\t * total size)\n+\t */\n+\tpba_size--;\n+\tif (pba_num_size < (((u32)pba_size * 2) + 1)) {\n+\t\treturn IXGBE_ERR_PARAM;\n+\t}\n+\n+\tfor (i = 0; i < pba_size; i++) {\n+\t\tstatus = ixgbe_read_ee_aci_E610(hw, (pba_tlv + 2 + 1) + i,\n+\t\t\t\t\t\t&pba_word);\n+\t\tif (status != IXGBE_SUCCESS) {\n+\t\t\treturn status;\n+\t\t}\n+\n+\t\tpba_num[(i * 2)] = (pba_word >> 8) & 0xFF;\n+\t\tpba_num[(i * 2) + 1] = pba_word & 0xFF;\n+\t}\n+\tpba_num[(pba_size * 2)] = '\\0';\n+\n+\treturn status;\n+}\ndiff --git a/drivers/net/ixgbe/base/ixgbe_e610.h b/drivers/net/ixgbe/base/ixgbe_e610.h\nindex 2c6e6b1bde..608d60bfee 100644\n--- a/drivers/net/ixgbe/base/ixgbe_e610.h\n+++ b/drivers/net/ixgbe/base/ixgbe_e610.h\n@@ -19,6 +19,7 @@ s32 ixgbe_aci_get_event(struct ixgbe_hw *hw, struct ixgbe_aci_event *e,\n void ixgbe_fill_dflt_direct_cmd_desc(struct ixgbe_aci_desc *desc, u16 opcode);\n \n s32 ixgbe_aci_get_fw_ver(struct ixgbe_hw *hw);\n+s32 ixgbe_aci_send_driver_ver(struct ixgbe_hw *hw, struct ixgbe_driver_ver *dv);\n s32 ixgbe_acquire_res(struct ixgbe_hw *hw, enum ixgbe_aci_res_ids res,\n \t\t enum ixgbe_aci_res_access_type access, u32 timeout);\n void ixgbe_release_res(struct ixgbe_hw *hw, enum ixgbe_aci_res_ids res);\n@@ -54,9 +55,14 @@ s32 ixgbe_aci_read_nvm(struct ixgbe_hw *hw, u16 module_typeid, u32 offset,\n \t\t bool read_shadow_ram);\n \n s32 ixgbe_nvm_validate_checksum(struct ixgbe_hw *hw);\n+s32 ixgbe_get_active_nvm_ver(struct ixgbe_hw *hw, struct ixgbe_nvm_info *nvm);\n s32 ixgbe_read_sr_word_aci(struct ixgbe_hw *hw, u16 offset, u16 *data);\n+s32 ixgbe_read_sr_buf_aci(struct ixgbe_hw *hw, u16 offset, u16 *words, u16 *data);\n s32 ixgbe_read_flat_nvm(struct ixgbe_hw *hw, u32 offset, u32 *length,\n \t\t\tu8 *data, bool read_shadow_ram);\n+/* E610 operations */\n+s32 ixgbe_reset_hw_E610(struct ixgbe_hw *hw);\n+s32 ixgbe_start_hw_E610(struct ixgbe_hw *hw);\n enum ixgbe_media_type ixgbe_get_media_type_E610(struct ixgbe_hw *hw);\n u64 ixgbe_get_supported_physical_layer_E610(struct ixgbe_hw *hw);\n s32 ixgbe_setup_link_E610(struct ixgbe_hw *hw, ixgbe_link_speed speed,\n@@ -71,7 +77,12 @@ s32 ixgbe_cfg_phy_fc(struct ixgbe_hw *hw,\n \t\t enum ixgbe_fc_mode req_mode);\n s32 ixgbe_setup_fc_E610(struct ixgbe_hw *hw);\n void ixgbe_fc_autoneg_E610(struct ixgbe_hw *hw);\n+s32 ixgbe_set_fw_drv_ver_E610(struct ixgbe_hw *hw, u8 maj, u8 min, u8 build,\n+\t\t\t u8 sub, u16 len, const char *driver_ver);\n void ixgbe_disable_rx_E610(struct ixgbe_hw *hw);\n+s32 ixgbe_setup_eee_E610(struct ixgbe_hw *hw, bool enable_eee);\n+bool ixgbe_fw_recovery_mode_E610(struct ixgbe_hw *hw);\n+bool ixgbe_get_fw_tsam_mode_E610(struct ixgbe_hw *hw);\n s32 ixgbe_init_phy_ops_E610(struct ixgbe_hw *hw);\n s32 ixgbe_identify_phy_E610(struct ixgbe_hw *hw);\n s32 ixgbe_identify_module_E610(struct ixgbe_hw *hw);\n@@ -90,7 +101,12 @@ s32 ixgbe_enter_lplu_E610(struct ixgbe_hw *hw);\n s32 ixgbe_aci_get_netlist_node(struct ixgbe_hw *hw,\n \t\t\t struct ixgbe_aci_cmd_get_link_topo *cmd,\n \t\t\t u8 *node_part_number, u16 *node_handle);\n+s32 ixgbe_init_eeprom_params_E610(struct ixgbe_hw *hw);\n s32 ixgbe_read_ee_aci_E610(struct ixgbe_hw *hw, u16 offset, u16 *data);\n+s32 ixgbe_read_ee_aci_buffer_E610(struct ixgbe_hw *hw, u16 offset,\n+\t\t\t\t u16 words, u16 *data);\n+s32 ixgbe_calc_eeprom_checksum_E610(struct ixgbe_hw *hw);\n s32 ixgbe_validate_eeprom_checksum_E610(struct ixgbe_hw *hw, u16 *checksum_val);\n+s32 ixgbe_read_pba_string_E610(struct ixgbe_hw *hw, u8 *pba_num, u32 pba_num_size);\n \n #endif /* _IXGBE_E610_H_ */\ndiff --git a/drivers/net/ixgbe/base/ixgbe_hv_vf.c b/drivers/net/ixgbe/base/ixgbe_hv_vf.c\nindex 1279659926..7d02802186 100644\n--- a/drivers/net/ixgbe/base/ixgbe_hv_vf.c\n+++ b/drivers/net/ixgbe/base/ixgbe_hv_vf.c\n@@ -1,5 +1,5 @@\n /* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(c) 2001-2020 Intel Corporation\n+ * Copyright(c) 2001-2024 Intel Corporation\n */\n \n #include \"ixgbe_vf.h\"\n@@ -136,7 +136,8 @@ static s32 ixgbevf_hv_check_mac_link_vf(struct ixgbe_hw *hw,\n \t\tbreak;\n \tcase IXGBE_LINKS_SPEED_100_82599:\n \t\t*speed = IXGBE_LINK_SPEED_100_FULL;\n-\t\tif (hw->mac.type == ixgbe_mac_X550) {\n+\t\tif (hw->mac.type == ixgbe_mac_X550 ||\n+\t\t hw->mac.type == ixgbe_mac_E610) {\n \t\t\tif (links_reg & IXGBE_LINKS_SPEED_NON_STD)\n \t\t\t\t*speed = IXGBE_LINK_SPEED_5GB_FULL;\n \t\t}\ndiff --git a/drivers/net/ixgbe/base/ixgbe_mbx.c b/drivers/net/ixgbe/base/ixgbe_mbx.c\nindex 2dab347396..444a0d339d 100644\n--- a/drivers/net/ixgbe/base/ixgbe_mbx.c\n+++ b/drivers/net/ixgbe/base/ixgbe_mbx.c\n@@ -1,5 +1,5 @@\n /* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(c) 2001-2020 Intel Corporation\n+ * Copyright(c) 2001-2024 Intel Corporation\n */\n \n #include \"ixgbe_type.h\"\n@@ -777,6 +777,7 @@ STATIC s32 ixgbe_check_for_rst_pf(struct ixgbe_hw *hw, u16 vf_id)\n \tcase ixgbe_mac_X550EM_x:\n \tcase ixgbe_mac_X550EM_a:\n \tcase ixgbe_mac_X540:\n+\tcase ixgbe_mac_E610:\n \t\tvflre = IXGBE_READ_REG(hw, IXGBE_PFVFLREC(index));\n \t\tbreak;\n \tdefault:\n@@ -1061,6 +1062,7 @@ void ixgbe_init_mbx_params_pf(struct ixgbe_hw *hw)\n \t hw->mac.type != ixgbe_mac_X550 &&\n \t hw->mac.type != ixgbe_mac_X550EM_x &&\n \t hw->mac.type != ixgbe_mac_X550EM_a &&\n+\t hw->mac.type != ixgbe_mac_E610 &&\n \t hw->mac.type != ixgbe_mac_X540)\n \t\treturn;\n \n@@ -1103,6 +1105,7 @@ void ixgbe_upgrade_mbx_params_pf(struct ixgbe_hw *hw, u16 vf_id)\n \t hw->mac.type != ixgbe_mac_X550 &&\n \t hw->mac.type != ixgbe_mac_X550EM_x &&\n \t hw->mac.type != ixgbe_mac_X550EM_a &&\n+\t hw->mac.type != ixgbe_mac_E610 &&\n \t hw->mac.type != ixgbe_mac_X540)\n \t\treturn;\n \ndiff --git a/drivers/net/ixgbe/base/ixgbe_phy.c b/drivers/net/ixgbe/base/ixgbe_phy.c\nindex 8a7712c8f2..2f74764eee 100644\n--- a/drivers/net/ixgbe/base/ixgbe_phy.c\n+++ b/drivers/net/ixgbe/base/ixgbe_phy.c\n@@ -1,5 +1,5 @@\n /* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(c) 2001-2020 Intel Corporation\n+ * Copyright(c) 2001-2024 Intel Corporation\n */\n \n #include \"ixgbe_api.h\"\n@@ -800,7 +800,8 @@ s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)\n \t\t\t IXGBE_MDIO_AUTO_NEG_DEV_TYPE,\n \t\t\t &autoneg_reg);\n \n-\tif (hw->mac.type == ixgbe_mac_X550) {\n+\tif ((hw->mac.type == ixgbe_mac_X550) ||\n+\t (hw->mac.type == ixgbe_mac_E610)) {\n \t\t/* Set or unset auto-negotiation 5G advertisement */\n \t\tautoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE;\n \t\tif ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_5GB_FULL) &&\n@@ -915,6 +916,7 @@ static s32 ixgbe_get_copper_speeds_supported(struct ixgbe_hw *hw)\n \n \tswitch (hw->mac.type) {\n \tcase ixgbe_mac_X550:\n+\tcase ixgbe_mac_E610:\n \t\thw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL;\n \t\thw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL;\n \t\tbreak;\ndiff --git a/drivers/net/ixgbe/base/ixgbe_type.h b/drivers/net/ixgbe/base/ixgbe_type.h\nindex 5ba15fc721..d86049426e 100644\n--- a/drivers/net/ixgbe/base/ixgbe_type.h\n+++ b/drivers/net/ixgbe/base/ixgbe_type.h\n@@ -2511,6 +2511,7 @@ enum {\n #define IXGBE_PCI_LINK_SPEED_2500\t0x1\n #define IXGBE_PCI_LINK_SPEED_5000\t0x2\n #define IXGBE_PCI_LINK_SPEED_8000\t0x3\n+#define IXGBE_PCI_LINK_SPEED_16000\t0x4\n #define IXGBE_PCI_HEADER_TYPE_REGISTER\t0x0E\n #define IXGBE_PCI_HEADER_TYPE_MULTIFUNC\t0x80\n #define IXGBE_PCI_DEVICE_CONTROL2_16ms\t0x0005\n@@ -3798,6 +3799,7 @@ enum ixgbe_bus_speed {\n \tixgbe_bus_speed_2500\t= 2500,\n \tixgbe_bus_speed_5000\t= 5000,\n \tixgbe_bus_speed_8000\t= 8000,\n+\tixgbe_bus_speed_16000 = 16000,\n \tixgbe_bus_speed_reserved\n };\n \n@@ -3942,6 +3944,7 @@ struct ixgbe_eeprom_operations {\n \ts32 (*validate_checksum)(struct ixgbe_hw *, u16 *);\n \ts32 (*update_checksum)(struct ixgbe_hw *);\n \ts32 (*calc_checksum)(struct ixgbe_hw *);\n+\ts32 (*read_pba_string)(struct ixgbe_hw *, u8 *, u32);\n };\n \n struct ixgbe_mac_operations {\n@@ -4048,6 +4051,9 @@ struct ixgbe_mac_operations {\n \tvoid (*mdd_event)(struct ixgbe_hw *hw, u32 *vf_bitmap);\n \tvoid (*restore_mdd_vf)(struct ixgbe_hw *hw, u32 vf);\n \tbool (*fw_recovery_mode)(struct ixgbe_hw *hw);\n+\tbool (*get_fw_tsam_mode)(struct ixgbe_hw *hw);\n+\ts32 (*get_fw_version)(struct ixgbe_hw *hw);\n+\ts32 (*get_nvm_version)(struct ixgbe_hw *hw, struct ixgbe_nvm_info *nvm);\n };\n \n struct ixgbe_phy_operations {\ndiff --git a/drivers/net/ixgbe/base/ixgbe_type_e610.h b/drivers/net/ixgbe/base/ixgbe_type_e610.h\nindex a50603d1b7..b366ea571a 100644\n--- a/drivers/net/ixgbe/base/ixgbe_type_e610.h\n+++ b/drivers/net/ixgbe/base/ixgbe_type_e610.h\n@@ -84,8 +84,73 @@\n /* General E610 defines */\n #define IXGBE_MAX_VSI\t\t\t768\n \n+/* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */\n+#define E610_SR_VPD_SIZE_WORDS\t\t512\n+#define E610_SR_PCIE_ALT_SIZE_WORDS\t512\n+\n /* Checksum and Shadow RAM pointers */\n+#define E610_SR_NVM_DEV_STARTER_VER\t\t0x18\n+#define E610_NVM_VER_LO_SHIFT\t\t\t0\n+#define E610_NVM_VER_LO_MASK\t\t\t(0xff << E610_NVM_VER_LO_SHIFT)\n+#define E610_NVM_VER_HI_SHIFT\t\t\t12\n+#define E610_NVM_VER_HI_MASK\t\t\t(0xf << E610_NVM_VER_HI_SHIFT)\n+#define E610_SR_NVM_MAP_VER\t\t\t0x29\n+#define E610_SR_NVM_EETRACK_LO\t\t\t0x2D\n+#define E610_SR_NVM_EETRACK_HI\t\t\t0x2E\n+#define E610_SR_VPD_PTR\t\t\t\t0x2F\n+#define E610_SR_PCIE_ALT_AUTO_LOAD_PTR\t\t0x3E\n #define E610_SR_SW_CHECKSUM_WORD\t\t0x3F\n+#define E610_SR_PFA_PTR\t\t\t\t0x40\n+#define E610_SR_1ST_NVM_BANK_PTR\t\t0x42\n+#define E610_SR_NVM_BANK_SIZE\t\t\t0x43\n+#define E610_SR_1ST_OROM_BANK_PTR\t\t0x44\n+#define E610_SR_OROM_BANK_SIZE\t\t\t0x45\n+#define E610_SR_NETLIST_BANK_PTR\t\t0x46\n+#define E610_SR_NETLIST_BANK_SIZE\t\t0x47\n+#define E610_SR_POINTER_TYPE_BIT\t\tBIT(15)\n+#define E610_SR_POINTER_MASK\t\t\t0x7fff\n+#define E610_SR_HALF_4KB_SECTOR_UNITS\t\t2048\n+#define E610_GET_PFA_POINTER_IN_WORDS(offset)\t\t\t\t \\\n+ ((offset & E610_SR_POINTER_TYPE_BIT) == E610_SR_POINTER_TYPE_BIT) ? \\\n+ ((offset & E610_SR_POINTER_MASK) * E610_SR_HALF_4KB_SECTOR_UNITS) : \\\n+ (offset & E610_SR_POINTER_MASK)\n+\n+/* Checksum and Shadow RAM pointers */\n+#define E610_SR_NVM_CTRL_WORD\t\t0x00\n+#define E610_SR_PBA_BLOCK_PTR\t\t0x16\n+\n+/* CSS Header words */\n+#define IXGBE_NVM_CSS_HDR_LEN_L\t\t\t0x02\n+#define IXGBE_NVM_CSS_HDR_LEN_H\t\t\t0x03\n+#define IXGBE_NVM_CSS_SREV_L\t\t\t0x14\n+#define IXGBE_NVM_CSS_SREV_H\t\t\t0x15\n+\n+/* Length of Authentication header section in words */\n+#define IXGBE_NVM_AUTH_HEADER_LEN\t\t0x08\n+\n+/* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */\n+#define IXGBE_SR_CTRL_WORD_1_S\t\t0x06\n+#define IXGBE_SR_CTRL_WORD_1_M\t\t(0x03 << IXGBE_SR_CTRL_WORD_1_S)\n+#define IXGBE_SR_CTRL_WORD_VALID\t0x1\n+#define IXGBE_SR_CTRL_WORD_OROM_BANK\tBIT(3)\n+#define IXGBE_SR_CTRL_WORD_NETLIST_BANK\tBIT(4)\n+#define IXGBE_SR_CTRL_WORD_NVM_BANK\tBIT(5)\n+#define IXGBE_SR_NVM_PTR_4KB_UNITS\tBIT(15)\n+\n+/* These macros strip from NVM Image Revision the particular part of NVM ver:\n+ major ver, minor ver and image id */\n+#define E610_NVM_MAJOR_VER(x)\t((x & 0xF000) >> 12)\n+#define E610_NVM_MINOR_VER(x)\t(x & 0x00FF)\n+\n+/* Minimal Security Revision */\n+\n+/* Shadow RAM related */\n+#define IXGBE_SR_SECTOR_SIZE_IN_WORDS\t\t0x800\n+#define IXGBE_SR_WORDS_IN_1KB\t\t\t512\n+/* Checksum should be calculated such that after adding all the words,\n+ * including the checksum word itself, the sum should be 0xBABA.\n+ */\n+#define IXGBE_SR_SW_CHECKSUM_BASE\t\t0xBABA\n \n /* General registers */\n \n@@ -137,6 +202,26 @@\n #define GL_MNG_FWSM_RSV5_S\t\t\t30\n #define GL_MNG_FWSM_RSV5_M\t\t\tMAKEMASK(0x3, 30)\n \n+/* FW mode indications */\n+#define GL_MNG_FWSM_FW_MODES_DEBUG_M BIT(0)\n+#define GL_MNG_FWSM_FW_MODES_RECOVERY_M BIT(1)\n+#define GL_MNG_FWSM_FW_MODES_ROLLBACK_M BIT(2)\n+\n+/* PF - Manageability Registers */\n+\n+/* Global NVM General Status Register */\n+#define GLNVM_GENS\t\t\t\t0x000B6100 /* Reset Source: POR */\n+#define GLNVM_GENS_NVM_PRES_S\t\t\t0\n+#define GLNVM_GENS_NVM_PRES_M\t\t\tBIT(0)\n+#define GLNVM_GENS_SR_SIZE_S\t\t\t5\n+#define GLNVM_GENS_SR_SIZE_M\t\t\tMAKEMASK(0x7, 5)\n+#define GLNVM_GENS_BANK1VAL_S\t\t\t8\n+#define GLNVM_GENS_BANK1VAL_M\t\t\tBIT(8)\n+#define GLNVM_GENS_ALT_PRST_S\t\t\t23\n+#define GLNVM_GENS_ALT_PRST_M\t\t\tBIT(23)\n+#define GLNVM_GENS_FL_AUTO_RD_S\t\t\t25\n+#define GLNVM_GENS_FL_AUTO_RD_M\t\t\tBIT(25)\n+\n /* Flash Access Register */\n #define GLNVM_FLA\t\t\t\t0x000B6108 /* Reset Source: POR */\n #define GLNVM_FLA_LOCKED_S\t\t\t6\n@@ -153,6 +238,14 @@\n #define PF_HICR_SV\t\t\tBIT(2)\n #define PF_HICR_EV\t\t\tBIT(3)\n \n+/* Admin Command Interface (ACI) defines */\n+/* Defines that help manage the driver vs FW API checks.\n+ */\n+#define IXGBE_FW_API_VER_BRANCH\t\t0x00\n+#define IXGBE_FW_API_VER_MAJOR\t\t0x01\n+#define IXGBE_FW_API_VER_MINOR\t\t0x05\n+#define IXGBE_FW_API_VER_DIFF_ALLOWED\t0x02\n+\n #define IXGBE_ACI_DESC_SIZE\t\t32\n #define IXGBE_ACI_DESC_SIZE_IN_DWORDS\tIXGBE_ACI_DESC_SIZE / BYTES_PER_DWORD\n \n@@ -1631,6 +1724,15 @@ struct ixgbe_aci_info {\n \tstruct ixgbe_lock lock;\t\t/* admin command interface lock */\n };\n \n+/* Enumeration of which flash bank is desired to read from, either the active\n+ * bank or the inactive bank. Used to abstract 1st and 2nd bank notion from\n+ * code which just wants to read the active or inactive flash bank.\n+ */\n+enum ixgbe_bank_select {\n+\tIXGBE_ACTIVE_FLASH_BANK,\n+\tIXGBE_INACTIVE_FLASH_BANK,\n+};\n+\n /* Option ROM version information */\n struct ixgbe_orom_info {\n \tu8 major;\t\t\t/* Major version of OROM */\n", "prefixes": [ "v2", "26/27" ] }