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{ "id": 139870, "url": "http://patchwork.dpdk.org/api/patches/139870/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20240505083737.118649-6-mattias.ronnblom@ericsson.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240505083737.118649-6-mattias.ronnblom@ericsson.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240505083737.118649-6-mattias.ronnblom@ericsson.com", "date": "2024-05-05T08:37:36", "name": "[RFC,v7,5/6] eal: add atomic bit operations", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "fe21fb8bf0d22a33a79ae7af1aced6010669d262", "submitter": { "id": 1077, "url": "http://patchwork.dpdk.org/api/people/1077/?format=api", "name": "Mattias Rönnblom", "email": "mattias.ronnblom@ericsson.com" }, "delegate": { "id": 1, "url": "http://patchwork.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20240505083737.118649-6-mattias.ronnblom@ericsson.com/mbox/", "series": [ { "id": 31882, "url": "http://patchwork.dpdk.org/api/series/31882/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=31882", "date": "2024-05-05T08:37:31", "name": "Improve EAL bit operations API", "version": 7, "mbox": "http://patchwork.dpdk.org/series/31882/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/139870/comments/", "check": "warning", "checks": "http://patchwork.dpdk.org/api/patches/139870/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 23FCE43FAE;\n\tSun, 5 May 2024 10:48:28 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 537E840395;\n\tSun, 5 May 2024 10:48:06 +0200 (CEST)", "from EUR05-AM6-obe.outbound.protection.outlook.com\n (mail-am6eur05on2057.outbound.protection.outlook.com [40.107.22.57])\n by mails.dpdk.org (Postfix) with ESMTP id 37478402E4\n for <dev@dpdk.org>; Sun, 5 May 2024 10:48:01 +0200 (CEST)", "from DU7P195CA0005.EURP195.PROD.OUTLOOK.COM (2603:10a6:10:54d::24)\n by PAWPR07MB9853.eurprd07.prod.outlook.com (2603:10a6:102:38d::9) with\n Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7544.39; Sun, 5 May\n 2024 08:47:59 +0000", "from DB3PEPF0000885C.eurprd02.prod.outlook.com\n (2603:10a6:10:54d:cafe::ac) by DU7P195CA0005.outlook.office365.com\n (2603:10a6:10:54d::24) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7544.39 via Frontend\n Transport; Sun, 5 May 2024 08:47:59 +0000", "from oa.msg.ericsson.com (192.176.1.74) by\n DB3PEPF0000885C.mail.protection.outlook.com (10.167.242.7) with Microsoft\n SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.20.7544.18 via Frontend Transport; Sun, 5 May 2024 08:47:58 +0000", "from seliicinfr00049.seli.gic.ericsson.se (153.88.142.248) by\n smtp-central.internal.ericsson.com (100.87.178.67) with Microsoft SMTP Server\n id 15.2.1544.9; Sun, 5 May 2024 10:47:58 +0200", "from breslau.. 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"X-Forefront-Antispam-Report": "CIP:192.176.1.74; CTRY:SE; LANG:en; SCL:1; SRV:;\n IPV:NLI; SFV:NSPM; H:oa.msg.ericsson.com; PTR:office365.se.ericsson.net;\n CAT:NONE; SFS:(13230031)(82310400017)(36860700004)(1800799015)(376005);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "ericsson.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "05 May 2024 08:47:58.9762 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 779eae21-991b-4122-f90a-08dc6ce010d5", "X-MS-Exchange-CrossTenant-Id": "92e84ceb-fbfd-47ab-be52-080c6b87953f", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=92e84ceb-fbfd-47ab-be52-080c6b87953f; Ip=[192.176.1.74];\n Helo=[oa.msg.ericsson.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DB3PEPF0000885C.eurprd02.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "PAWPR07MB9853", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Add atomic bit test/set/clear/assign/flip and\ntest-and-set/clear/assign/flip functions.\n\nAll atomic bit functions allow (and indeed, require) the caller to\nspecify a memory order.\n\nRFC v7:\n * Replace compare-exchange-based rte_bitset_atomic_test_and_*() and\n flip() with implementations that use the previous value as returned\n by the atomic fetch function.\n * Reword documentation to match the non-atomic macro variants.\n * Remove pointer to <rte_stdatomic.h> for memory model documentation,\n since there is no documentation for that API.\n\nRFC v6:\n * Have rte_bit_atomic_test() accept const-marked bitsets.\n\nRFC v4:\n * Add atomic bit flip.\n * Mark macro-generated private functions experimental.\n\nRFC v3:\n * Work around lack of C++ support for _Generic (Tyler Retzlaff).\n\nRFC v2:\n o Add rte_bit_atomic_test_and_assign() (for consistency).\n o Fix bugs in rte_bit_atomic_test_and_[set|clear]().\n o Use <rte_stdatomics.h> to support MSVC.\n\nSigned-off-by: Mattias Rönnblom <mattias.ronnblom@ericsson.com>\nAcked-by: Morten Brørup <mb@smartsharesystems.com>\nAcked-by: Tyler Retzlaff <roretzla@linux.microsoft.com>\n---\n lib/eal/include/rte_bitops.h | 413 +++++++++++++++++++++++++++++++++++\n 1 file changed, 413 insertions(+)", "diff": "diff --git a/lib/eal/include/rte_bitops.h b/lib/eal/include/rte_bitops.h\nindex 3644aa115c..673b888c1a 100644\n--- a/lib/eal/include/rte_bitops.h\n+++ b/lib/eal/include/rte_bitops.h\n@@ -21,6 +21,7 @@\n \n #include <rte_compat.h>\n #include <rte_debug.h>\n+#include <rte_stdatomic.h>\n \n #ifdef __cplusplus\n extern \"C\" {\n@@ -403,6 +404,204 @@ extern \"C\" {\n \t\t uint32_t *: __rte_bit_once_flip32,\t\t\\\n \t\t uint64_t *: __rte_bit_once_flip64)(addr, nr)\n \n+/**\n+ * @warning\n+ * @b EXPERIMENTAL: this API may change without prior notice.\n+ *\n+ * Test if a particular bit in a word is set with a particular memory\n+ * order.\n+ *\n+ * Test a bit with the resulting memory load ordered as per the\n+ * specified memory order.\n+ *\n+ * @param addr\n+ * A pointer to the word to query.\n+ * @param nr\n+ * The index of the bit.\n+ * @param memory_order\n+ * The memory order to use.\n+ * @return\n+ * Returns true if the bit is set, and false otherwise.\n+ */\n+#define rte_bit_atomic_test(addr, nr, memory_order)\t\t\t\\\n+\t_Generic((addr),\t\t\t\t\t\t\\\n+\t\t uint32_t *: __rte_bit_atomic_test32,\t\t\t\\\n+\t\t const uint32_t *: __rte_bit_atomic_test32,\t\t\\\n+\t\t uint64_t *: __rte_bit_atomic_test64,\t\t\t\\\n+\t\t const uint64_t *: __rte_bit_atomic_test64)(addr, nr,\t\\\n+\t\t\t\t\t\t\t memory_order)\n+\n+/**\n+ * @warning\n+ * @b EXPERIMENTAL: this API may change without prior notice.\n+ *\n+ * Atomically set bit in word.\n+ *\n+ * Generic selection macro to atomically set bit specified by @c nr in\n+ * the word pointed to by @c addr to '1', with the memory ordering as\n+ * specified by @c memory_order.\n+ *\n+ * @param addr\n+ * A pointer to the word to modify.\n+ * @param nr\n+ * The index of the bit.\n+ * @param memory_order\n+ * The memory order to use.\n+ */\n+#define rte_bit_atomic_set(addr, nr, memory_order)\t\t\t\\\n+\t_Generic((addr),\t\t\t\t\t\t\\\n+\t\t uint32_t *: __rte_bit_atomic_set32,\t\t\t\\\n+\t\t uint64_t *: __rte_bit_atomic_set64)(addr, nr, memory_order)\n+\n+/**\n+ * @warning\n+ * @b EXPERIMENTAL: this API may change without prior notice.\n+ *\n+ * Atomically clear bit in word.\n+ *\n+ * Generic selection macro to atomically set bit specified by @c nr in\n+ * the word pointed to by @c addr to '0', with the memory ordering as\n+ * specified by @c memory_order.\n+ *\n+ * @param addr\n+ * A pointer to the word to modify.\n+ * @param nr\n+ * The index of the bit.\n+ * @param memory_order\n+ * The memory order to use.\n+ */\n+#define rte_bit_atomic_clear(addr, nr, memory_order)\t\t\t\\\n+\t_Generic((addr),\t\t\t\t\t\t\\\n+\t\t uint32_t *: __rte_bit_atomic_clear32,\t\t\t\\\n+\t\t uint64_t *: __rte_bit_atomic_clear64)(addr, nr, memory_order)\n+\n+/**\n+ * @warning\n+ * @b EXPERIMENTAL: this API may change without prior notice.\n+ *\n+ * Atomically assign a value to bit in word.\n+ *\n+ * Generic selection macro to atomically set bit specified by @c nr in the\n+ * word pointed to by @c addr to the value indicated by @c value, with\n+ * the memory ordering as specified with @c memory_order.\n+ *\n+ * @param addr\n+ * A pointer to the word to modify.\n+ * @param nr\n+ * The index of the bit.\n+ * @param value\n+ * The new value of the bit - true for '1', or false for '0'.\n+ * @param memory_order\n+ * The memory order to use.\n+ */\n+#define rte_bit_atomic_assign(addr, nr, value, memory_order)\t\t\\\n+\t_Generic((addr),\t\t\t\t\t\t\\\n+\t\t uint32_t *: __rte_bit_atomic_assign32,\t\t\t\\\n+\t\t uint64_t *: __rte_bit_atomic_assign64)(addr, nr, value, \\\n+\t\t\t\t\t\t\tmemory_order)\n+\n+/**\n+ * @warning\n+ * @b EXPERIMENTAL: this API may change without prior notice.\n+ *\n+ * Atomically flip bit in word.\n+ *\n+ * Generic selection macro to atomically negate the value of the bit\n+ * specified by @c nr in the word pointed to by @c addr to the value\n+ * indicated by @c value, with the memory ordering as specified with\n+ * @c memory_order.\n+ *\n+ * @param addr\n+ * A pointer to the word to modify.\n+ * @param nr\n+ * The index of the bit.\n+ * @param memory_order\n+ * The memory order to use.\n+ */\n+#define rte_bit_atomic_flip(addr, nr, memory_order)\t\t\t\\\n+\t_Generic((addr),\t\t\t\t\t\t\\\n+\t\t uint32_t *: __rte_bit_atomic_flip32,\t\t\t\\\n+\t\t uint64_t *: __rte_bit_atomic_flip64)(addr, nr, memory_order)\n+\n+/**\n+ * @warning\n+ * @b EXPERIMENTAL: this API may change without prior notice.\n+ *\n+ * Atomically test and set a bit in word.\n+ *\n+ * Generic selection macro to atomically test and set bit specified by\n+ * @c nr in the word pointed to by @c addr to '1', with the memory\n+ * ordering as specified with @c memory_order.\n+ *\n+ * @param addr\n+ * A pointer to the word to modify.\n+ * @param nr\n+ * The index of the bit.\n+ * @param memory_order\n+ * The memory order to use.\n+ * @return\n+ * Returns true if the bit was set, and false otherwise.\n+ */\n+#define rte_bit_atomic_test_and_set(addr, nr, memory_order)\t\t\\\n+\t_Generic((addr),\t\t\t\t\t\t\\\n+\t\t uint32_t *: __rte_bit_atomic_test_and_set32,\t\t\\\n+\t\t uint64_t *: __rte_bit_atomic_test_and_set64)(addr, nr,\t\\\n+\t\t\t\t\t\t\t memory_order)\n+\n+/**\n+ * @warning\n+ * @b EXPERIMENTAL: this API may change without prior notice.\n+ *\n+ * Atomically test and clear a bit in word.\n+ *\n+ * Generic selection macro to atomically test and clear bit specified\n+ * by @c nr in the word pointed to by @c addr to '0', with the memory\n+ * ordering as specified with @c memory_order.\n+ *\n+ * @param addr\n+ * A pointer to the word to modify.\n+ * @param nr\n+ * The index of the bit.\n+ * @param memory_order\n+ * The memory order to use.\n+ * @return\n+ * Returns true if the bit was set, and false otherwise.\n+ */\n+#define rte_bit_atomic_test_and_clear(addr, nr, memory_order)\t\t\\\n+\t_Generic((addr),\t\t\t\t\t\t\\\n+\t\t uint32_t *: __rte_bit_atomic_test_and_clear32,\t\t\\\n+\t\t uint64_t *: __rte_bit_atomic_test_and_clear64)(addr, nr, \\\n+\t\t\t\t\t\t\t\tmemory_order)\n+\n+/**\n+ * @warning\n+ * @b EXPERIMENTAL: this API may change without prior notice.\n+ *\n+ * Atomically test and assign a bit in word.\n+ *\n+ * Generic selection macro to atomically test and assign bit specified\n+ * by @c nr in the word pointed to by @c addr the value specified by\n+ * @c value, with the memory ordering as specified with @c\n+ * memory_order.\n+ *\n+ * @param addr\n+ * A pointer to the word to modify.\n+ * @param nr\n+ * The index of the bit.\n+ * @param value\n+ * The new value of the bit - true for '1', or false for '0'.\n+ * @param memory_order\n+ * The memory order to use.\n+ * @return\n+ * Returns true if the bit was set, and false otherwise.\n+ */\n+#define rte_bit_atomic_test_and_assign(addr, nr, value, memory_order)\t\\\n+\t_Generic((addr),\t\t\t\t\t\t\\\n+\t\t uint32_t *: __rte_bit_atomic_test_and_assign32,\t\\\n+\t\t uint64_t *: __rte_bit_atomic_test_and_assign64)(addr, nr, \\\n+\t\t\t\t\t\t\t\t value, \\\n+\t\t\t\t\t\t\t\t memory_order)\n+\n #define __RTE_GEN_BIT_TEST(family, fun, qualifier, size)\t\t\\\n \t__rte_experimental\t\t\t\t\t\t\\\n \tstatic inline bool\t\t\t\t\t\t\\\n@@ -487,6 +686,145 @@ __RTE_GEN_BIT_CLEAR(once_, clear, volatile, 64)\n __RTE_GEN_BIT_ASSIGN(once_, assign, volatile, 64)\n __RTE_GEN_BIT_FLIP(once_, flip, volatile, 64)\n \n+#define __RTE_GEN_BIT_ATOMIC_TEST(size)\t\t\t\t\t\\\n+\t__rte_experimental\t\t\t\t\t\t\\\n+\tstatic inline bool\t\t\t\t\t\t\\\n+\t__rte_bit_atomic_test ## size(const uint ## size ## _t *addr,\t\\\n+\t\t\t\t unsigned int nr, int memory_order) \\\n+\t{\t\t\t\t\t\t\t\t\\\n+\t\tRTE_ASSERT(nr < size);\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tconst RTE_ATOMIC(uint ## size ## _t) *a_addr =\t\t\\\n+\t\t\t(const RTE_ATOMIC(uint ## size ## _t) *)addr;\t\\\n+\t\tuint ## size ## _t mask = (uint ## size ## _t)1 << nr;\t\\\n+\t\treturn rte_atomic_load_explicit(a_addr, memory_order) & mask; \\\n+\t}\n+\n+#define __RTE_GEN_BIT_ATOMIC_SET(size)\t\t\t\t\t\\\n+\t__rte_experimental\t\t\t\t\t\t\\\n+\tstatic inline void\t\t\t\t\t\t\\\n+\t__rte_bit_atomic_set ## size(uint ## size ## _t *addr,\t\t\\\n+\t\t\t\t unsigned int nr, int memory_order)\t\\\n+\t{\t\t\t\t\t\t\t\t\\\n+\t\tRTE_ASSERT(nr < size);\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tRTE_ATOMIC(uint ## size ## _t) *a_addr =\t\t\\\n+\t\t\t(RTE_ATOMIC(uint ## size ## _t) *)addr;\t\t\\\n+\t\tuint ## size ## _t mask = (uint ## size ## _t)1 << nr;\t\\\n+\t\trte_atomic_fetch_or_explicit(a_addr, mask, memory_order); \\\n+\t}\n+\n+#define __RTE_GEN_BIT_ATOMIC_CLEAR(size)\t\t\t\t\\\n+\t__rte_experimental\t\t\t\t\t\t\\\n+\tstatic inline void\t\t\t\t\t\t\\\n+\t__rte_bit_atomic_clear ## size(uint ## size ## _t *addr,\t\\\n+\t\t\t\t unsigned int nr, int memory_order) \\\n+\t{\t\t\t\t\t\t\t\t\\\n+\t\tRTE_ASSERT(nr < size);\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tRTE_ATOMIC(uint ## size ## _t) *a_addr =\t\t\\\n+\t\t\t(RTE_ATOMIC(uint ## size ## _t) *)addr;\t\t\\\n+\t\tuint ## size ## _t mask = (uint ## size ## _t)1 << nr;\t\\\n+\t\trte_atomic_fetch_and_explicit(a_addr, ~mask, memory_order); \\\n+\t}\n+\n+#define __RTE_GEN_BIT_ATOMIC_FLIP(size)\t\t\t\t\t\\\n+\t__rte_experimental\t\t\t\t\t\t\\\n+\tstatic inline void\t\t\t\t\t\t\\\n+\t__rte_bit_atomic_flip ## size(uint ## size ## _t *addr,\t\t\\\n+\t\t\t\t unsigned int nr, int memory_order) \\\n+\t{\t\t\t\t\t\t\t\t\\\n+\t\tRTE_ASSERT(nr < size);\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tRTE_ATOMIC(uint ## size ## _t) *a_addr =\t\t\\\n+\t\t\t(RTE_ATOMIC(uint ## size ## _t) *)addr;\t\t\\\n+\t\tuint ## size ## _t mask = (uint ## size ## _t)1 << nr;\t\\\n+\t\trte_atomic_fetch_xor_explicit(a_addr, mask, memory_order); \\\n+\t}\n+\n+#define __RTE_GEN_BIT_ATOMIC_ASSIGN(size)\t\t\t\t\\\n+\t__rte_experimental\t\t\t\t\t\t\\\n+\tstatic inline void\t\t\t\t\t\t\\\n+\t__rte_bit_atomic_assign ## size(uint ## size ## _t *addr,\t\\\n+\t\t\t\t\tunsigned int nr, bool value,\t\\\n+\t\t\t\t\tint memory_order)\t\t\\\n+\t{\t\t\t\t\t\t\t\t\\\n+\t\tif (value)\t\t\t\t\t\t\\\n+\t\t\t__rte_bit_atomic_set ## size(addr, nr, memory_order); \\\n+\t\telse\t\t\t\t\t\t\t\\\n+\t\t\t__rte_bit_atomic_clear ## size(addr, nr,\t\\\n+\t\t\t\t\t\t memory_order);\t\\\n+\t}\n+\n+#define __RTE_GEN_BIT_ATOMIC_TEST_AND_SET(size)\t\t\t\t\t\\\n+\t__rte_experimental\t\t\t\t\t\t\\\n+\tstatic inline bool\t\t\t\t\t\t\\\n+\t__rte_bit_atomic_test_and_set ## size(uint ## size ## _t *addr,\t\\\n+\t\t\t\t\t unsigned int nr,\t\t\\\n+\t\t\t\t\t int memory_order)\t\t\\\n+\t{\t\t\t\t\t\t\t\t\\\n+\t\tRTE_ASSERT(nr < size);\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tRTE_ATOMIC(uint ## size ## _t) *a_addr =\t\t\\\n+\t\t\t(RTE_ATOMIC(uint ## size ## _t) *)addr;\t\t\\\n+\t\tuint ## size ## _t mask = (uint ## size ## _t)1 << nr;\t\\\n+\t\tuint ## size ## _t prev;\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tprev = rte_atomic_fetch_or_explicit(a_addr, mask,\t\\\n+\t\t\t\t\t\t memory_order);\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\treturn prev & mask;\t\t\t\t\t\\\n+\t}\n+\n+#define __RTE_GEN_BIT_ATOMIC_TEST_AND_CLEAR(size)\t\t\t\\\n+\t__rte_experimental\t\t\t\t\t\t\\\n+\tstatic inline bool\t\t\t\t\t\t\\\n+\t__rte_bit_atomic_test_and_clear ## size(uint ## size ## _t *addr,\t\\\n+\t\t\t\t\t\tunsigned int nr,\t\\\n+\t\t\t\t\t\tint memory_order)\t\\\n+\t{\t\t\t\t\t\t\t\t\\\n+\t\tRTE_ASSERT(nr < size);\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tRTE_ATOMIC(uint ## size ## _t) *a_addr =\t\t\\\n+\t\t\t(RTE_ATOMIC(uint ## size ## _t) *)addr;\t\t\\\n+\t\tuint ## size ## _t mask = (uint ## size ## _t)1 << nr;\t\\\n+\t\tuint ## size ## _t prev;\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t prev = rte_atomic_fetch_and_explicit(a_addr, ~mask,\t\\\n+\t\t\t\t\t\t memory_order);\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\treturn prev & mask;\t\t\t\t\t\\\n+\t}\n+\n+#define __RTE_GEN_BIT_ATOMIC_TEST_AND_ASSIGN(size)\t\t\t\\\n+\t__rte_experimental\t\t\t\t\t\t\\\n+\tstatic inline bool\t\t\t\t\t\t\\\n+\t__rte_bit_atomic_test_and_assign ## size(uint ## size ## _t *addr, \\\n+\t\t\t\t\t\t unsigned int nr,\t\\\n+\t\t\t\t\t\t bool value,\t\t\\\n+\t\t\t\t\t\t int memory_order)\t\\\n+\t{\t\t\t\t\t\t\t\t\\\n+\t\tif (value)\t\t\t\t\t\t\\\n+\t\t\treturn __rte_bit_atomic_test_and_set ## size(addr, nr, \\\n+\t\t\t\t\t\t\t\t memory_order); \\\n+\t\telse\t\t\t\t\t\t\t\\\n+\t\t\treturn __rte_bit_atomic_test_and_clear ## size(addr, nr, \\\n+\t\t\t\t\t\t\t\t memory_order); \\\n+\t}\n+\n+#define __RTE_GEN_BIT_ATOMIC_OPS(size)\t\t\t\\\n+\t__RTE_GEN_BIT_ATOMIC_TEST(size)\t\t\t\\\n+\t__RTE_GEN_BIT_ATOMIC_SET(size)\t\t\t\\\n+\t__RTE_GEN_BIT_ATOMIC_CLEAR(size)\t\t\\\n+\t__RTE_GEN_BIT_ATOMIC_ASSIGN(size)\t\t\\\n+\t__RTE_GEN_BIT_ATOMIC_TEST_AND_SET(size)\t\t\\\n+\t__RTE_GEN_BIT_ATOMIC_TEST_AND_CLEAR(size)\t\\\n+\t__RTE_GEN_BIT_ATOMIC_TEST_AND_ASSIGN(size)\t\\\n+\t__RTE_GEN_BIT_ATOMIC_FLIP(size)\n+\n+__RTE_GEN_BIT_ATOMIC_OPS(32)\n+__RTE_GEN_BIT_ATOMIC_OPS(64)\n+\n /*------------------------ 32-bit relaxed operations ------------------------*/\n \n /**\n@@ -1188,6 +1526,14 @@ rte_log2_u64(uint64_t v)\n #undef rte_bit_once_assign\n #undef rte_bit_once_flip\n \n+#undef rte_bit_atomic_test\n+#undef rte_bit_atomic_set\n+#undef rte_bit_atomic_clear\n+#undef rte_bit_atomic_assign\n+#undef rte_bit_atomic_test_and_set\n+#undef rte_bit_atomic_test_and_clear\n+#undef rte_bit_atomic_test_and_assign\n+\n #define __RTE_BIT_OVERLOAD_SZ_2(fun, qualifier, size, arg1_type, arg1_name) \\\n \tstatic inline void\t\t\t\t\t\t\\\n \trte_bit_ ## fun(qualifier uint ## size ## _t *addr,\t\t\\\n@@ -1231,6 +1577,59 @@ rte_log2_u64(uint64_t v)\n \t__RTE_BIT_OVERLOAD_SZ_3(fun, qualifier, 64, arg1_type, arg1_name, \\\n \t\t\t\targ2_type, arg2_name)\n \n+#define __RTE_BIT_OVERLOAD_SZ_3R(fun, qualifier, size, ret_type, arg1_type, \\\n+\t\t\t\t arg1_name, arg2_type, arg2_name)\t\\\n+\tstatic inline ret_type\t\t\t\t\t\t\\\n+\trte_bit_ ## fun(uint ## size ## _t *addr, arg1_type arg1_name,\t\\\n+\t\t\targ2_type arg2_name)\t\t\t\t\\\n+\t{\t\t\t\t\t\t\t\t\\\n+\t\treturn __rte_bit_ ## fun ## size(addr, arg1_name, arg2_name); \\\n+\t}\n+\n+#define __RTE_BIT_OVERLOAD_3R(fun, qualifier, ret_type, arg1_type, arg1_name, \\\n+\t\t\t arg2_type, arg2_name)\t\t\t\\\n+\t__RTE_BIT_OVERLOAD_SZ_3R(fun, qualifier, 32, ret_type, arg1_type, \\\n+\t\t\t\t arg1_name, arg2_type, arg2_name)\t\\\n+\t__RTE_BIT_OVERLOAD_SZ_3R(fun, qualifier, 64, ret_type, arg1_type, \\\n+\t\t\t\t arg1_name, arg2_type, arg2_name)\n+\n+#define __RTE_BIT_OVERLOAD_SZ_4(fun, qualifier, size, arg1_type, arg1_name, \\\n+\t\t\t\targ2_type, arg2_name, arg3_type, arg3_name) \\\n+\tstatic inline void\t\t\t\t\t\t\\\n+\trte_bit_ ## fun(uint ## size ## _t *addr, arg1_type arg1_name,\t\\\n+\t\t\targ2_type arg2_name, arg3_type arg3_name)\t\\\n+\t{\t\t\t\t\t\t\t\t\\\n+\t\t__rte_bit_ ## fun ## size(addr, arg1_name, arg2_name,\t\\\n+\t\t\t\t\t arg3_name);\t\t \\\n+\t}\n+\n+#define __RTE_BIT_OVERLOAD_4(fun, qualifier, arg1_type, arg1_name, arg2_type, \\\n+\t\t\t arg2_name, arg3_type, arg3_name)\t\t\\\n+\t__RTE_BIT_OVERLOAD_SZ_4(fun, qualifier, 32, arg1_type, arg1_name, \\\n+\t\t\t\targ2_type, arg2_name, arg3_type, arg3_name) \\\n+\t__RTE_BIT_OVERLOAD_SZ_4(fun, qualifier, 64, arg1_type, arg1_name, \\\n+\t\t\t\targ2_type, arg2_name, arg3_type, arg3_name)\n+\n+#define __RTE_BIT_OVERLOAD_SZ_4R(fun, qualifier, size, ret_type, arg1_type, \\\n+\t\t\t\t arg1_name, arg2_type, arg2_name, arg3_type, \\\n+\t\t\t\t arg3_name)\t\t\t\t\\\n+\tstatic inline ret_type\t\t\t\t\t\t\\\n+\trte_bit_ ## fun(uint ## size ## _t *addr, arg1_type arg1_name,\t\\\n+\t\t\targ2_type arg2_name, arg3_type arg3_name)\t\\\n+\t{\t\t\t\t\t\t\t\t\\\n+\t\treturn __rte_bit_ ## fun ## size(addr, arg1_name, arg2_name, \\\n+\t\t\t\t\t\t arg3_name);\t\t\\\n+\t}\n+\n+#define __RTE_BIT_OVERLOAD_4R(fun, qualifier, ret_type, arg1_type, arg1_name, \\\n+\t\t\t arg2_type, arg2_name, arg3_type, arg3_name) \\\n+\t__RTE_BIT_OVERLOAD_SZ_4R(fun, qualifier, 32, ret_type, arg1_type, \\\n+\t\t\t\t arg1_name, arg2_type, arg2_name, arg3_type, \\\n+\t\t\t\t arg3_name)\t\t\t\t\\\n+\t__RTE_BIT_OVERLOAD_SZ_4R(fun, qualifier, 64, ret_type, arg1_type, \\\n+\t\t\t\t arg1_name, arg2_type, arg2_name, arg3_type, \\\n+\t\t\t\t arg3_name)\n+\n __RTE_BIT_OVERLOAD_2R(test, const, bool, unsigned int, nr)\n __RTE_BIT_OVERLOAD_2(set,, unsigned int, nr)\n __RTE_BIT_OVERLOAD_2(clear,, unsigned int, nr)\n@@ -1243,6 +1642,20 @@ __RTE_BIT_OVERLOAD_2(once_clear, volatile, unsigned int, nr)\n __RTE_BIT_OVERLOAD_3(once_assign, volatile, unsigned int, nr, bool, value)\n __RTE_BIT_OVERLOAD_2(once_flip, volatile, unsigned int, nr)\n \n+__RTE_BIT_OVERLOAD_3R(atomic_test, const, bool, unsigned int, nr,\n+\t\t int, memory_order)\n+__RTE_BIT_OVERLOAD_3(atomic_set,, unsigned int, nr, int, memory_order)\n+__RTE_BIT_OVERLOAD_3(atomic_clear,, unsigned int, nr, int, memory_order)\n+__RTE_BIT_OVERLOAD_4(atomic_assign,, unsigned int, nr, bool, value,\n+\t\t int, memory_order)\n+__RTE_BIT_OVERLOAD_3(atomic_flip,, unsigned int, nr, int, memory_order)\n+__RTE_BIT_OVERLOAD_3R(atomic_test_and_set,, bool, unsigned int, nr,\n+\t\t int, memory_order)\n+__RTE_BIT_OVERLOAD_3R(atomic_test_and_clear,, bool, unsigned int, nr,\n+\t\t int, memory_order)\n+__RTE_BIT_OVERLOAD_4R(atomic_test_and_assign,, bool, unsigned int, nr,\n+\t\t bool, value, int, memory_order)\n+\n #endif\n \n #endif /* _RTE_BITOPS_H_ */\n", "prefixes": [ "RFC", "v7", "5/6" ] }