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GET /api/patches/139881/?format=api
{ "id": 139881, "url": "http://patchwork.dpdk.org/api/patches/139881/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20240506114419.966498-2-igozlan@nvidia.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240506114419.966498-2-igozlan@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240506114419.966498-2-igozlan@nvidia.com", "date": "2024-05-06T11:44:05", "name": "[v2,02/16] common/mlx5: fix error in mlx5 prm structs", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "ad0450ca5ed8304282d39e341695f335d38b2626", "submitter": { "id": 3118, "url": "http://patchwork.dpdk.org/api/people/3118/?format=api", "name": "Itamar Gozlan", "email": "igozlan@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patchwork.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20240506114419.966498-2-igozlan@nvidia.com/mbox/", "series": [ { "id": 31885, "url": "http://patchwork.dpdk.org/api/series/31885/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=31885", "date": "2024-05-06T11:44:04", "name": "[v2,01/16] net/mlx5/hws: move warn into debug level when needed", "version": 2, "mbox": "http://patchwork.dpdk.org/series/31885/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/139881/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/139881/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id CDE0A43FB4;\n\tMon, 6 May 2024 13:44:49 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id EA564402E3;\n\tMon, 6 May 2024 13:44:47 +0200 (CEST)", "from NAM02-BN1-obe.outbound.protection.outlook.com\n (mail-bn1nam02on2069.outbound.protection.outlook.com [40.107.212.69])\n by mails.dpdk.org (Postfix) with ESMTP id 1D5C0402E1;\n Mon, 6 May 2024 13:44:46 +0200 (CEST)", "from PH0PR07CA0023.namprd07.prod.outlook.com (2603:10b6:510:5::28)\n by IA1PR12MB8538.namprd12.prod.outlook.com (2603:10b6:208:455::13) with\n Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7544.41; 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helo=mail.nvidia.com; pr=C", "From": "Itamar Gozlan <igozlan@nvidia.com>", "To": "<igozlan@nvidia.com>, <erezsh@nvidia.com>, <hamdani@nvidia.com>,\n <kliteyn@nvidia.com>, <viacheslavo@nvidia.com>, <thomas@monjalon.net>,\n <suanmingm@nvidia.com>, Dariusz Sosnowski <dsosnowski@nvidia.com>, Ori Kam\n <orika@nvidia.com>, Matan Azrad <matan@nvidia.com>, Alex Vesker\n <valex@nvidia.com>", "CC": "<dev@dpdk.org>, <stable@dpdk.org>", "Subject": "[v2 02/16] common/mlx5: fix error in mlx5 prm structs", "Date": "Mon, 6 May 2024 14:44:05 +0300", "Message-ID": "<20240506114419.966498-2-igozlan@nvidia.com>", "X-Mailer": "git-send-email 2.39.3", "In-Reply-To": "<20240506114419.966498-1-igozlan@nvidia.com>", "References": "<20240314114220.203241-1-igozlan@nvidia.com>\n <20240506114419.966498-1-igozlan@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-NV-OnPremToCloud": "ExternallySecured", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "CY4PEPF0000E9D5:EE_|IA1PR12MB8538:EE_", "X-MS-Office365-Filtering-Correlation-Id": "aaa1b9b4-8275-4eaa-ff8a-08dc6dc1ea9e", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;\n ARA:13230031|1800799015|82310400017|376005|36860700004|921011;", "X-Microsoft-Antispam-Message-Info": "\n DpbsBOcwZoXlna56U7cL1AgR/9njX5R+eLKc2Y5FhILPTnI+tctZcYPnIPp71LwVtURIWRWBp+jtw5bvXOmmK5/PMjF07rx36gW8lF+/bM8A3YUHF9IulxlQ9PYLQ/XeK50gIAwQNXBYclzXgOGU7wMNbb4pc+AMymMGm72tcBdWvcBurDGRWNxj6+JaY3WwX++NXijCCZ4G8y38PAyrJCnNm00/mlVFBtEDp5XMds3UlG/+CB6FOl53PJt/Fyj1/tvBYlC9gPrOO8PDop4W3h7UkEGkgeN2Tk8pi7eGixM+RUCebUd89/nd4H6n+lthiHKKIzV8wXbClr0UJLYj5qXU1RptH73tp6g/C11OWHFxmvWyppKkZ/PjcfI7muFbph6V507LQLytq4IvySTwbpU5A6E+gdYQQTWSCHE4lGCx2+HWRv+nQYpLKZa/J41xOtHUYuZ7pXczWCpS9Wxp/M2vylC+osIs4DYsT51Bz4TO4aHsqXExIrHMwUCryHkAamrpPf6vWj9ZRCK69QPfhEcUwKYCYw9yjdQqjXdYPJTx1B1WrP/HxGip8JtkZtnz4LGaGwP8zXJXdqnVwh3a1MQNXr5YUR+z7apEbV5Gu9JdBNgjvs4B0sggPr1xuNdJHcXtus4izMcTdUxSvFazZjFCqwo6hd75z2+jBG/+h36TRqVhSMqAXSl6Kq+uamCD/DRpy08Sz7fhatAEMv2LB9U/2PORLa2Ta0c9jDVWvQk3YPCYQdYA2rgXdSVAMQKt3o3//ZILPAd9VetA2l81+ANxs0Htx/l29aYaC/YT2dHSlpeF/rY+jpJDPaC9r1QxQkjAk+7AMu9mIc7xJJFNTt3mtc9ZD5WgPORqigl2nKJYlAAFmIVq0yaT13I9I2HipmNN5VfYrCCv9wSS4++WEStXmfFgN9AKZabRbbj+20lDzoQ1jwdIbv55eKsj21DX+Y4AuD227Q6FNn3v8GOgB7jXdMpj+p/s/yCK5zZcmc27Vy5f+OB/wQsyUhbRvRvsRgb674QVQuJWt+c4cb8+8WGKdndRIgNgRE4pX59jz/ji9XhiZ7ay71hUWOr+M5rEWxEB0fNSbQbP7Ki2NoTZFc7RHM730kjw+jRKm4xEQyZmYkkwq7jaZo2X9hVWEjcCuEo6z/kE27UhTCVvOQaYHuhQSFOVvD7HWhzuRab+JC96KaRuMN2FYY8QQbp2xGJiCco2Ww9t6KhhqUnZzTTTn9++n2+P90+QSMyUjXVYUaFKgiUq0+6is19RJx1/NhVwiWse7pL8h3U+dL1uzixtsnaittdspMYoqU1Ti9/zdY53guJKrOoRfRXtGU3p1NGnUKIWnEYZLMxRYc6gJm5Hk1tILjDzCGtFIPzQqFgIkp59q1FMtoNSFGZu0C2Dp6c5", "X-Forefront-Antispam-Report": "CIP:216.228.118.233; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc7edge2.nvidia.com; CAT:NONE;\n SFS:(13230031)(1800799015)(82310400017)(376005)(36860700004)(921011);\n DIR:OUT;\n SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "06 May 2024 11:44:41.1547 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n aaa1b9b4-8275-4eaa-ff8a-08dc6dc1ea9e", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.118.233];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CY4PEPF0000E9D5.namprd05.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "IA1PR12MB8538", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Yevgeny Kliteynik <kliteyn@nvidia.com>\n\nFix wrong reserved size and add helpful comment\n\nFixes: 365cdf5f8ce7 (\"net/mlx5/hws: add command layer\")\nCc: stable@dpdk.org\n\nSigned-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/common/mlx5/mlx5_prm.h | 6 +++---\n 1 file changed, 3 insertions(+), 3 deletions(-)", "diff": "diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h\nindex c671c75bfd..c6846cdb7e 100644\n--- a/drivers/common/mlx5/mlx5_prm.h\n+++ b/drivers/common/mlx5/mlx5_prm.h\n@@ -2360,8 +2360,8 @@ struct mlx5_ifc_cmd_hca_cap_2_bits {\n \tu8 reserved_at_d0[0x3];\n \tu8 log_conn_track_max_alloc[0x5];\n \tu8 reserved_at_d8[0x3];\n-\tu8 log_max_conn_track_offload[0x5];\n-\tu8 cross_vhca_object_to_object_supported[0x20]; /* End of DW7. */\n+\tu8 log_max_conn_track_offload[0x5]; /* End of DW7. */\n+\tu8 cross_vhca_object_to_object_supported[0x20];\n \tu8 allowed_object_for_other_vhca_access_high[0x20];\n \tu8 allowed_object_for_other_vhca_access[0x20];\n \tu8 reserved_at_140[0x20];\n@@ -3655,7 +3655,7 @@ struct mlx5_ifc_stc_ste_param_vport_bits {\n \tu8 eswitch_owner_vhca_id[0x10];\n \tu8 vport_number[0x10];\n \tu8 eswitch_owner_vhca_id_valid[0x1];\n-\tu8 reserved_at_21[0x59];\n+\tu8 reserved_at_21[0x5f];\n };\n \n union mlx5_ifc_stc_param_bits {\n", "prefixes": [ "v2", "02/16" ] }