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GET /api/patches/139985/?format=api
{ "id": 139985, "url": "http://patchwork.dpdk.org/api/patches/139985/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20240507124305.2318-22-venkatkumar.ande@amd.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240507124305.2318-22-venkatkumar.ande@amd.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240507124305.2318-22-venkatkumar.ande@amd.com", "date": "2024-05-07T12:43:02", "name": "[v2,22/25] net/axgbe: add support for Rx adaptation", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": false, "hash": "728b53bf44c7a0a9a078674bbb2190f2efd6b446", "submitter": { "id": 3256, "url": "http://patchwork.dpdk.org/api/people/3256/?format=api", "name": "Venkat Kumar Ande", "email": "venkatkumar.ande@amd.com" }, "delegate": { "id": 319, "url": "http://patchwork.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20240507124305.2318-22-venkatkumar.ande@amd.com/mbox/", "series": [ { "id": 31890, "url": "http://patchwork.dpdk.org/api/series/31890/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=31890", "date": "2024-05-07T12:42:41", "name": "[v2,01/25] net/axgbe: fix mdio access for non-zero ports and CL45 PHYs", "version": 2, "mbox": "http://patchwork.dpdk.org/series/31890/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/139985/comments/", "check": "warning", "checks": "http://patchwork.dpdk.org/api/patches/139985/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 6DF2343FC9;\n\tTue, 7 May 2024 14:46:15 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id F31DF433C7;\n\tTue, 7 May 2024 14:44:40 +0200 (CEST)", "from NAM10-BN7-obe.outbound.protection.outlook.com\n (mail-bn7nam10on2086.outbound.protection.outlook.com [40.107.92.86])\n by mails.dpdk.org (Postfix) with ESMTP id E646D433D9\n for <dev@dpdk.org>; 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helo=SATLEXMB04.amd.com; pr=C", "From": "Venkat Kumar Ande <venkatkumar.ande@amd.com>", "To": "<dev@dpdk.org>", "CC": "<Selwin.Sebastian@amd.com>, Venkat Kumar Ande <venkatkumar.ande@amd.com>", "Subject": "[PATCH v2 22/25] net/axgbe: add support for Rx adaptation", "Date": "Tue, 7 May 2024 18:13:02 +0530", "Message-ID": "<20240507124305.2318-22-venkatkumar.ande@amd.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20240507124305.2318-1-venkatkumar.ande@amd.com>", "References": "<20240412125013.10498-1-VenkatKumar.Ande@amd.com>\n <20240507124305.2318-1-venkatkumar.ande@amd.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.180.168.240]", "X-ClientProxiedBy": "SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com\n (10.181.40.145)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "SN1PEPF00036F42:EE_|PH7PR12MB7188:EE_", "X-MS-Office365-Filtering-Correlation-Id": "ffd7d962-36d9-43a4-12a6-08dc6e937264", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;\n ARA:13230031|82310400017|36860700004|376005|1800799015;", "X-Microsoft-Antispam-Message-Info": "\n iir8RGVoopHmK/xNS3mwuu0meRgEGk8ON04bBVHeh0zM6ZzyNcXzHTeO6+N3DLbWKvPTUtTx7Aor5X5tR3zPWUX9Bb4ZZSo6bPpcqyRm/4tBTODAv0w5WShFHj7uF0q+5fzSa5k1GhEwWHTey5anOVvhF6GKwxQoJlnZNRsmtEHgj0WDEHuEIUwdxjbndX7YVjXExemr1ioRnArk35RlhyJXwYJ8X8BwrbASJPgPSfL6APw8rj3gNhi9tvH80hydGpYELPl8e5n2HJO3aqfDsWpqX2BZlp40T0CgjP2CwQrsONXdyuHOPCDIlVaLXlTTuuDCg3iM5ZIXLTO/HG5Fgd83gpjceuxzsriksWz/7KrDWFv2xN9X8YA2gYNxjOzSAdOgJxdx3+JlyHAnhEijbaCba85kcyI/R5xvZ8/rSK+69v5Br69+YS754NcdIxdMhQu+rbYvwrQe3nTvukxePLoDYDMgt5VJlHP3pg3oWG4QoMu2cZruWJC2v8bhBeY+28aystbSnoQxjKtHsozFGdk9xGhB7VZDKsSg3m1B9Z86a+WJ96jWJgTRljtil89MfJSEBTPTDijqyNAv2DgUHgtjsT+gjZRc4zG5RxHqGeEBiSLMKLXQcoRlSJ0XhlKtOaIIZiy3AFmnKNRJN0yEwJD4X8Umr6CvZyIAfInYHe+eZaxnL4060AGA0p+xtQHyCFjSDW3Z2/4N/50n3GxBbI4UxC3lREYGCEU+g7gZf2jR2nsXjs+POoDFyExn0T5Ms9r5FxcELtuAFKcPVodqIdJqaMjGgfImCs7vUMruzPuhQUOEj+D2ABfTckN2kdR6huhjKSITctxSXZ3Y/qPQ0wMFLTabcYlacSpvJUVFoQjxDjaf62qQ/Sxy8lBh7WKpa7spEGE1/rTDHdi9WXCPze6wUIp9G+bGxflyK0EqBVAdgrxAuPLeUqOAO0qpPb3BEcZyroaQIHS6wTRE/qBR+XLmxs3o+GbxPAQNNp3N0hpD9jIgqvTYFDpr6mvVBk8Y+ag85MAoA7bYMCfvViCSCQsj30G2hrEie1FZXig8Gprk8R/pUQqLZO/wLfkb9ihzarkMnV/c7hKkLkNL3c0ug7KgW/r7ilSJd5b6kuriIRmRV23Rxdlx4/4MVIX2aUKczKgTXxJT7LbR0E29jxeUnlSzYr62Yro+vtTg5oXqTiQvsPRumhBNj7NuHT9CWrQCI8qp1SalbWVgOxW7JVhR/UwQUITPuTJiLV8nphuJlYoqzCKKCXVtrMeoMkbAHF91Bl3c0cH1IsjzMVzCve0GFIRTi22sADYJ6Y18C8uz/F0sDahfUmoEMqllIoqSNaVcCDj1RDRGRJjdgSDBzCu1enMS+VY7wx2LctpR/vyIHNl8xRkWQSxvmjMUb4bzLhV/", "X-Forefront-Antispam-Report": "CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:;\n IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE;\n SFS:(13230031)(82310400017)(36860700004)(376005)(1800799015); DIR:OUT;\n SFP:1101;", "X-OriginatorOrg": "amd.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "07 May 2024 12:44:33.7551 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n ffd7d962-36d9-43a4-12a6-08dc6e937264", "X-MS-Exchange-CrossTenant-Id": "3dd8961f-e488-4e60-8e11-a82d994e183d", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17];\n Helo=[SATLEXMB04.amd.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n SN1PEPF00036F42.namprd05.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "PH7PR12MB7188", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "The existing implementation for non-Autonegotiation 10G speed modes does\nnot enable RX adaptation in the Driver and FW. The RX Equalization\nsettings (AFE settings alone) are manually configured and the existing\nlink-up sequence in the driver does not perform rx adaptation process as\nmentioned in the Synopsys databook. There's a customer request for 10G\nbackplane mode without Auto-negotiation and for the DAC cables of more\nsignificant length that follow the non-Autonegotiation mode. These modes\nrequire PHY to perform RX Adaptation.\n\nThe proposed logic adds the necessary changes to Yellow Carp devices to\nensure seamless RX Adaptation for 10G-SFI (LONG DAC) and 10G-KR without\nAN (CL72 not present). The RX adaptation core algorithm is executed by\nfirmware, however, to achieve that a new mailbox sub-command is required\nto be sent by the driver.\n\nSigned-off-by: Venkat Kumar Ande <venkatkumar.ande@amd.com>\n---\n drivers/net/axgbe/axgbe_common.h | 38 +++++++\n drivers/net/axgbe/axgbe_ethdev.h | 5 +\n drivers/net/axgbe/axgbe_phy_impl.c | 170 ++++++++++++++++++++++++++++-\n 3 files changed, 210 insertions(+), 3 deletions(-)", "diff": "diff --git a/drivers/net/axgbe/axgbe_common.h b/drivers/net/axgbe/axgbe_common.h\nindex 1a43192630..0e1b2c1500 100644\n--- a/drivers/net/axgbe/axgbe_common.h\n+++ b/drivers/net/axgbe/axgbe_common.h\n@@ -1274,6 +1274,22 @@\n #define MDIO_PMA_RX_CTRL1\t\t0x8051\n #endif\n \n+#ifndef MDIO_PMA_RX_LSTS\n+#define MDIO_PMA_RX_LSTS\t\t0x018020\n+#endif\n+\n+#ifndef MDIO_PMA_RX_EQ_CTRL4\n+#define MDIO_PMA_RX_EQ_CTRL4\t\t0x0001805C\n+#endif\n+\n+#ifndef MDIO_PMA_MP_MISC_STS\n+#define MDIO_PMA_MP_MISC_STS\t\t0x0078\n+#endif\n+\n+#ifndef MDIO_PMA_PHY_RX_EQ_CEU\n+#define MDIO_PMA_PHY_RX_EQ_CEU\t\t0x1800E\n+#endif\n+\n #ifndef MDIO_PCS_DIG_CTRL\n #define MDIO_PCS_DIG_CTRL\t\t0x8000\n #endif\n@@ -1415,6 +1431,28 @@ static inline uint32_t high32_value(uint64_t addr)\n #define XGBE_PMA_RX_RST_0_RESET_ON 0x10\n #define XGBE_PMA_RX_RST_0_RESET_OFF 0x00\n \n+#define XGBE_PMA_RX_SIG_DET_0_MASK\tBIT(4)\n+#define XGBE_PMA_RX_SIG_DET_0_ENABLE\tBIT(4)\n+#define XGBE_PMA_RX_SIG_DET_0_DISABLE\t0x0000\n+\n+#define XGBE_PMA_RX_VALID_0_MASK\tBIT(12)\n+#define XGBE_PMA_RX_VALID_0_ENABLE\tBIT(12)\n+#define XGBE_PMA_RX_VALID_0_DISABLE\t0x0000\n+\n+#define XGBE_PMA_RX_AD_REQ_MASK\t\tBIT(12)\n+#define XGBE_PMA_RX_AD_REQ_ENABLE\tBIT(12)\n+#define XGBE_PMA_RX_AD_REQ_DISABLE\t0x0000\n+\n+#define XGBE_PMA_RX_ADPT_ACK_MASK\tBIT(12)\n+#define XGBE_PMA_RX_ADPT_ACK\t\tBIT(12)\n+\n+#define XGBE_PMA_CFF_UPDTM1_VLD\t\tBIT(8)\n+#define XGBE_PMA_CFF_UPDT0_VLD\t\tBIT(9)\n+#define XGBE_PMA_CFF_UPDT1_VLD\t\tBIT(10)\n+#define XGBE_PMA_CFF_UPDT_MASK\t\t(XGBE_PMA_CFF_UPDTM1_VLD |\\\n+\t\t\t\t\t XGBE_PMA_CFF_UPDT0_VLD | \\\n+\t\t\t\t\t XGBE_PMA_CFF_UPDT1_VLD)\n+\n /*END*/\n \n /* Bit setting and getting macros\ndiff --git a/drivers/net/axgbe/axgbe_ethdev.h b/drivers/net/axgbe/axgbe_ethdev.h\nindex cb3df47a63..dd00ae8af5 100644\n--- a/drivers/net/axgbe/axgbe_ethdev.h\n+++ b/drivers/net/axgbe/axgbe_ethdev.h\n@@ -244,6 +244,7 @@ enum axgbe_mb_cmd {\n \n enum axgbe_mb_subcmd {\n \tAXGBE_MB_SUBCMD_NONE = 0,\n+\tAXGBE_MB_SUBCMD_RX_ADAP,\n \n \t/* 10GbE SFP subcommands */\n \tAXGBE_MB_SUBCMD_ACTIVE = 0,\n@@ -722,6 +723,10 @@ struct axgbe_port {\n \tstruct rte_timecounter tx_tstamp;\n \tunsigned int tstamp_addend;\n \n+\tbool en_rx_adap;\n+\tint rx_adapt_retries;\n+\tbool rx_adapt_done;\n+\tbool mode_set;\n };\n \n void axgbe_init_function_ptrs_dev(struct axgbe_hw_if *hw_if);\ndiff --git a/drivers/net/axgbe/axgbe_phy_impl.c b/drivers/net/axgbe/axgbe_phy_impl.c\nindex 13b37e9b8b..a1c42b7dd4 100644\n--- a/drivers/net/axgbe/axgbe_phy_impl.c\n+++ b/drivers/net/axgbe/axgbe_phy_impl.c\n@@ -247,6 +247,10 @@ struct axgbe_phy_data {\n };\n \n static enum axgbe_an_mode axgbe_phy_an_mode(struct axgbe_port *pdata);\n+static void axgbe_phy_perform_ratechange(struct axgbe_port *pdata,\n+\t\tenum axgbe_mb_cmd cmd, enum axgbe_mb_subcmd sub_cmd);\n+static void axgbe_phy_rrc(struct axgbe_port *pdata);\n+\n \n static int axgbe_phy_i2c_xfer(struct axgbe_port *pdata,\n \t\t\t struct axgbe_i2c_op *i2c_op)\n@@ -1194,6 +1198,92 @@ static void axgbe_phy_set_redrv_mode(struct axgbe_port *pdata)\n \taxgbe_phy_put_comm_ownership(pdata);\n }\n \n+#define MAX_RX_ADAPT_RETRIES\t\t1\n+#define XGBE_PMA_RX_VAL_SIG_MASK\t(XGBE_PMA_RX_SIG_DET_0_MASK | \\\n+\t\t\t\t\t XGBE_PMA_RX_VALID_0_MASK)\n+\n+static void axgbe_set_rx_adap_mode(struct axgbe_port *pdata,\n+\t\t\t\t enum axgbe_mode mode)\n+{\n+\tif (pdata->rx_adapt_retries++ >= MAX_RX_ADAPT_RETRIES) {\n+\t\tpdata->rx_adapt_retries = 0;\n+\t\treturn;\n+\t}\n+\n+\taxgbe_phy_perform_ratechange(pdata,\n+\t\t\t\t mode == AXGBE_MODE_KR ?\n+\t\t\t\t AXGBE_MB_CMD_SET_10G_KR :\n+\t\t\t\t AXGBE_MB_CMD_SET_10G_SFI,\n+\t\t\t\t AXGBE_MB_SUBCMD_RX_ADAP);\n+}\n+\n+static void axgbe_rx_adaptation(struct axgbe_port *pdata)\n+{\n+\tstruct axgbe_phy_data *phy_data = pdata->phy_data;\n+\tunsigned int reg;\n+\n+\t/* step 2: force PCS to send RX_ADAPT Req to PHY */\n+\tXMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_RX_EQ_CTRL4,\n+\t\t\t XGBE_PMA_RX_AD_REQ_MASK, XGBE_PMA_RX_AD_REQ_ENABLE);\n+\n+\t/* Step 3: Wait for RX_ADAPT ACK from the PHY */\n+\trte_delay_ms(200);\n+\n+\t/* Software polls for coefficient update command (given by local PHY) */\n+\treg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_PHY_RX_EQ_CEU);\n+\n+\t/* Clear the RX_AD_REQ bit */\n+\tXMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_RX_EQ_CTRL4,\n+\t\t\t XGBE_PMA_RX_AD_REQ_MASK, XGBE_PMA_RX_AD_REQ_DISABLE);\n+\n+\t/* Check if coefficient update command is set */\n+\tif ((reg & XGBE_PMA_CFF_UPDT_MASK) != XGBE_PMA_CFF_UPDT_MASK)\n+\t\tgoto set_mode;\n+\n+\t/* Step 4: Check for Block lock */\n+\n+\t/* Link status is latched low, so read once to clear\n+\t * and then read again to get current state\n+\t */\n+\treg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);\n+\treg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);\n+\tif (reg & MDIO_STAT1_LSTATUS) {\n+\t\t/* If the block lock is found, update the helpers\n+\t\t * and declare the link up\n+\t\t */\n+\t\tPMD_DRV_LOG(NOTICE, \"Rx adaptation - Block_lock done\\n\");\n+\t\tpdata->rx_adapt_done = true;\n+\t\tpdata->mode_set = false;\n+\t\treturn;\n+\t}\n+\n+set_mode:\n+\taxgbe_set_rx_adap_mode(pdata, phy_data->cur_mode);\n+}\n+\n+static void axgbe_phy_rx_adaptation(struct axgbe_port *pdata)\n+{\n+\tunsigned int reg;\n+\n+rx_adapt_reinit:\n+\treg = XMDIO_READ_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_RX_LSTS,\n+\t\t\t XGBE_PMA_RX_VAL_SIG_MASK);\n+\n+\t/* step 1: Check for RX_VALID && LF_SIGDET */\n+\tif ((reg & XGBE_PMA_RX_VAL_SIG_MASK) != XGBE_PMA_RX_VAL_SIG_MASK) {\n+\t\tPMD_DRV_LOG(NOTICE, \"RX_VALID or LF_SIGDET is unset, issue rrc\\n\");\n+\t\taxgbe_phy_rrc(pdata);\n+\t\tif (pdata->rx_adapt_retries++ >= MAX_RX_ADAPT_RETRIES) {\n+\t\t\tpdata->rx_adapt_retries = 0;\n+\t\t\treturn;\n+\t\t}\n+\t\tgoto rx_adapt_reinit;\n+\t}\n+\n+\t/* perform rx adaptation */\n+\taxgbe_rx_adaptation(pdata);\n+}\n+\n static void axgbe_phy_rx_reset(struct axgbe_port *pdata)\n {\n \tint reg;\n@@ -1258,12 +1348,27 @@ static void axgbe_phy_perform_ratechange(struct axgbe_port *pdata,\n \twait = AXGBE_RATECHANGE_COUNT;\n \twhile (wait--) {\n \t\tif (!XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS))\n-\t\t\tgoto reenable_pll;\n+\t\t\tgoto do_rx_adaptation;\n \t\trte_delay_us(1500);\n \t}\n \tPMD_DRV_LOG(NOTICE, \"firmware mailbox command did not complete\\n\");\n \t/* Reset on error */\n \taxgbe_phy_rx_reset(pdata);\n+\tgoto reenable_pll;\n+\n+\n+do_rx_adaptation:\n+\tif (pdata->en_rx_adap && sub_cmd == AXGBE_MB_SUBCMD_RX_ADAP &&\n+\t (cmd == AXGBE_MB_CMD_SET_10G_KR || cmd == AXGBE_MB_CMD_SET_10G_SFI)) {\n+\t\tPMD_DRV_LOG(NOTICE, \"Enabling RX adaptation\\n\");\n+\t\tpdata->mode_set = true;\n+\t\taxgbe_phy_rx_adaptation(pdata);\n+\t\t/* return from here to avoid enabling PLL ctrl\n+\t\t * during adaptation phase\n+\t\t */\n+\t\treturn;\n+\t}\n+\n \n reenable_pll:\n \t/* Enable PLL re-initialization, not needed for PHY Power Off and RRC cmds */\n@@ -1296,6 +1401,31 @@ static void axgbe_phy_power_off(struct axgbe_port *pdata)\n \tPMD_DRV_LOG(DEBUG, \"phy powered off\\n\");\n }\n \n+static bool enable_rx_adap(struct axgbe_port *pdata, enum axgbe_mode mode)\n+{\n+\tstruct axgbe_phy_data *phy_data = pdata->phy_data;\n+\tunsigned int ver;\n+\n+\t/* Rx-Adaptation is not supported on older platforms(< 0x30H) */\n+\tver = AXGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER);\n+\tif (ver < 0x30)\n+\t\treturn false;\n+\n+\t/* Re-driver models 4223 && 4227 do not support Rx-Adaptation */\n+\tif (phy_data->redrv &&\n+\t (phy_data->redrv_model == AXGBE_PHY_REDRV_MODEL_4223 ||\n+\t phy_data->redrv_model == AXGBE_PHY_REDRV_MODEL_4227))\n+\t\treturn false;\n+\n+\t/* 10G KR mode with AN does not support Rx-Adaptation */\n+\tif (mode == AXGBE_MODE_KR &&\n+\t phy_data->port_mode != AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG)\n+\t\treturn false;\n+\n+\tpdata->en_rx_adap = 1;\n+\treturn true;\n+}\n+\n static void axgbe_phy_sfi_mode(struct axgbe_port *pdata)\n {\n \tstruct axgbe_phy_data *phy_data = pdata->phy_data;\n@@ -1304,8 +1434,13 @@ static void axgbe_phy_sfi_mode(struct axgbe_port *pdata)\n \n \t/* 10G/SFI */\n \tif (phy_data->sfp_cable != AXGBE_SFP_CABLE_PASSIVE) {\n+\t\tpdata->en_rx_adap = 0;\n \t\taxgbe_phy_perform_ratechange(pdata, AXGBE_MB_CMD_SET_10G_SFI,\n \t\t\t\t\t\t\tAXGBE_MB_SUBCMD_ACTIVE);\n+\t} else if ((phy_data->sfp_cable == AXGBE_SFP_CABLE_PASSIVE) &&\n+\t\t\t\t(enable_rx_adap(pdata, AXGBE_MODE_SFI))) {\n+\t\taxgbe_phy_perform_ratechange(pdata, AXGBE_MB_CMD_SET_10G_SFI,\n+\t\t\t\t\t\tAXGBE_MB_SUBCMD_RX_ADAP);\n \t} else {\n \t\tif (phy_data->sfp_cable_len <= 1)\n \t\t\taxgbe_phy_perform_ratechange(pdata, AXGBE_MB_CMD_SET_10G_SFI,\n@@ -1330,6 +1465,10 @@ static void axgbe_phy_kr_mode(struct axgbe_port *pdata)\n \taxgbe_phy_set_redrv_mode(pdata);\n \n \t/* 10G/KR */\n+\tif (enable_rx_adap(pdata, AXGBE_MODE_KR))\n+\t\taxgbe_phy_perform_ratechange(pdata, AXGBE_MB_CMD_SET_10G_KR,\n+\t\t\t\t\t\tAXGBE_MB_SUBCMD_RX_ADAP);\n+\telse\n \t\taxgbe_phy_perform_ratechange(pdata, AXGBE_MB_CMD_SET_10G_KR,\n \t\t\t\t\t\tAXGBE_MB_SUBCMD_NONE);\n \tphy_data->cur_mode = AXGBE_MODE_KR;\n@@ -1719,8 +1858,11 @@ static int axgbe_phy_link_status(struct axgbe_port *pdata, int *an_restart)\n \t\t\treturn 0;\n \t\t}\n \n-\t\tif (phy_data->sfp_mod_absent || phy_data->sfp_rx_los)\n+\t\tif (phy_data->sfp_mod_absent || phy_data->sfp_rx_los) {\n+\t\t\tif (pdata->en_rx_adap)\n+\t\t\t\tpdata->rx_adapt_done = false;\n \t\t\treturn 0;\n+\t\t}\n \t}\n \n \t/* Link status is latched low, so read once to clear\n@@ -1728,7 +1870,29 @@ static int axgbe_phy_link_status(struct axgbe_port *pdata, int *an_restart)\n \t */\n \treg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);\n \treg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);\n-\tif (reg & MDIO_STAT1_LSTATUS)\n+\n+\tif (pdata->en_rx_adap) {\n+\t\t/* if the link is available and adaptation is done,\n+\t\t * declare link up\n+\t\t */\n+\t\tif ((reg & MDIO_STAT1_LSTATUS) && pdata->rx_adapt_done)\n+\t\t\treturn 1;\n+\t\t/* If either link is not available or adaptation is not done,\n+\t\t * retrigger the adaptation logic. (if the mode is not set,\n+\t\t * then issue mailbox command first)\n+\t\t */\n+\t\tif (pdata->mode_set) {\n+\t\t\taxgbe_phy_rx_adaptation(pdata);\n+\t\t} else {\n+\t\t\tpdata->rx_adapt_done = false;\n+\t\t\taxgbe_phy_set_mode(pdata, phy_data->cur_mode);\n+\t\t}\n+\n+\t\t/* check again for the link and adaptation status */\n+\t\treg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);\n+\t\tif ((reg & MDIO_STAT1_LSTATUS) && pdata->rx_adapt_done)\n+\t\t\treturn 1;\n+\t} else if (reg & MDIO_STAT1_LSTATUS)\n \t\treturn 1;\n \n \tif (pdata->phy.autoneg == AUTONEG_ENABLE &&\n", "prefixes": [ "v2", "22/25" ] }