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GET /api/patches/16220/?format=api
{ "id": 16220, "url": "http://patchwork.dpdk.org/api/patches/16220/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/1475144449-22176-10-git-send-email-3chas3@gmail.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1475144449-22176-10-git-send-email-3chas3@gmail.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1475144449-22176-10-git-send-email-3chas3@gmail.com", "date": "2016-09-29T10:20:49", "name": "[dpdk-dev,v2,10/10] bnx2x: Merge debug register operations into headers", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "1cdd11977ee997897b38afedd5ada5d0a77340a9", "submitter": { "id": 341, "url": "http://patchwork.dpdk.org/api/people/341/?format=api", "name": "Chas Williams", "email": "3chas3@gmail.com" }, "delegate": { "id": 10, "url": "http://patchwork.dpdk.org/api/users/10/?format=api", "username": "bruce", "first_name": "Bruce", "last_name": "Richardson", "email": "bruce.richardson@intel.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/1475144449-22176-10-git-send-email-3chas3@gmail.com/mbox/", "series": [], "comments": "http://patchwork.dpdk.org/api/patches/16220/comments/", "check": "pending", "checks": "http://patchwork.dpdk.org/api/patches/16220/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 592E46A95;\n\tThu, 29 Sep 2016 12:21:18 +0200 (CEST)", "from mail-yb0-f193.google.com (mail-yb0-f193.google.com\n\t[209.85.213.193]) by dpdk.org (Postfix) with ESMTP id EE57D591F\n\tfor <dev@dpdk.org>; Thu, 29 Sep 2016 12:21:06 +0200 (CEST)", "by mail-yb0-f193.google.com with SMTP id t5so792651yba.3\n\tfor <dev@dpdk.org>; Thu, 29 Sep 2016 03:21:06 -0700 (PDT)", "from monolith.home (pool-96-231-205-104.washdc.fios.verizon.net.\n\t[96.231.205.104]) by smtp.gmail.com with ESMTPSA id\n\tz133sm5302430ywb.51.2016.09.29.03.21.05\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tThu, 29 Sep 2016 03:21:06 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references;\n\tbh=fPtiMVWvk4D4t70q2f/epsHWCs+PzN8CDRSe4WGID1Y=;\n\tb=fvbtpxXcAZ/wgiQXEg5RgPUal+HUT3dS4l/7mqZ+gyMsRiSsZobR0kB18YOoAABq1s\n\tfc36u+M2puXKWsYFCNK18K1fxmpao2Irijn9WHC2B4nbqAc9fxJwEf7aBQ/WvkjfYjVt\n\ta0pkuU0jSBPS1D7gnfdE1oN5jyjSCOor3E+PkOU8jM4ieixy49KadCxkmq0CJbQMBRUs\n\tZ2w2mv6KNP9sA7WzCwubXr0ekWAPsSgcBekJk7W7FvQOnK2ZTr63/v1ELXRxv2RfZii3\n\tAEUTxy8g7PmTVfiwX4avtsUb9znRnY+2+7/Wvg8Spm8JR7iM0Kp9aeeMh+pJqvf6EIyN\n\tBrEg==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20130820;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=fPtiMVWvk4D4t70q2f/epsHWCs+PzN8CDRSe4WGID1Y=;\n\tb=klKn9UJaTa6t4vFs4f2NsYgAmfuRq1Qft3xTR346bU/cnvoeX+Aa5UTdvZmsTTk1tr\n\taPdhsoLxTe7Dvy01s16eRZcuorxB4y2EQuLhYGyqBBv1iiCl/w2xpHt47jT8OMjG8iQB\n\tr9HNR54rdzH56xVnneppDooHv7o6Pyxgn3FsMI9Gmx62TEs5UQJ2FBs8BE/N9D7xE/tG\n\tKJEFXdqN5GIp4jbaImA7gqngzeP8gVGk9YnGMyZ6+q6B2M+hAjyxdv6FyGdQBPpyCSjp\n\tuetVuudRyPWXAA3RvHB9pF/aT4X/zOAEJsvyvY0qpC38SSPG/BLpBlXIc5ouSFtYL37w\n\tksoQ==", "X-Gm-Message-State": "AA6/9Rm3r/SLqhGVr7bw85BMmIrqar3b1idSq3MpwjYClfDiTuAeUEC/UN9U91Y0om9PZA==", "X-Received": "by 10.37.112.213 with SMTP id l204mr367053ybc.124.1475144466443; \n\tThu, 29 Sep 2016 03:21:06 -0700 (PDT)", "From": "Chas Williams <3chas3@gmail.com>", "To": "dev@dpdk.org", "Cc": "harish.patil@qlogic.com,\n\tChas Williams <3chas3@gmail.com>", "Date": "Thu, 29 Sep 2016 06:20:49 -0400", "Message-Id": "<1475144449-22176-10-git-send-email-3chas3@gmail.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1475144449-22176-1-git-send-email-3chas3@gmail.com>", "References": "<1475144449-22176-1-git-send-email-3chas3@gmail.com>", "Subject": "[dpdk-dev] [PATCH v2 10/10] bnx2x: Merge debug register operations\n\tinto headers", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "patches and discussions about DPDK <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "The register read/writes should just be static inline instead of\nalternately defined as routines or macros depending on the status of\ndebugging.\n\nFix bnx2x_reg_read32() returning 0 during debug unaligned reads.\n\nFixes: b5bf7719221d (\"bnx2x: driver support routines\")\n\nSigned-off-by: Chas Williams <3chas3@gmail.com>\n---\n drivers/net/bnx2x/Makefile | 1 -\n drivers/net/bnx2x/bnx2x.h | 99 +++++++++++++++++++++++++++++++++++++---------\n drivers/net/bnx2x/debug.c | 96 --------------------------------------------\n 3 files changed, 80 insertions(+), 116 deletions(-)\n delete mode 100644 drivers/net/bnx2x/debug.c", "diff": "diff --git a/drivers/net/bnx2x/Makefile b/drivers/net/bnx2x/Makefile\nindex ab69680..e971fb6 100644\n--- a/drivers/net/bnx2x/Makefile\n+++ b/drivers/net/bnx2x/Makefile\n@@ -28,7 +28,6 @@ SRCS-$(CONFIG_RTE_LIBRTE_BNX2X_PMD) += bnx2x_ethdev.c\n SRCS-$(CONFIG_RTE_LIBRTE_BNX2X_PMD) += ecore_sp.c\n SRCS-$(CONFIG_RTE_LIBRTE_BNX2X_PMD) += elink.c\n SRCS-$(CONFIG_RTE_LIBRTE_BNX2X_PMD) += bnx2x_vfpf.c\n-SRCS-$(CONFIG_RTE_LIBRTE_BNX2X_DEBUG_PERIODIC) += debug.c\n \n # this lib depends upon:\n DEPDIRS-$(CONFIG_RTE_LIBRTE_BNX2X_PMD) += lib/librte_eal lib/librte_ether\ndiff --git a/drivers/net/bnx2x/bnx2x.h b/drivers/net/bnx2x/bnx2x.h\nindex e4979ac..d1dd6aa 100644\n--- a/drivers/net/bnx2x/bnx2x.h\n+++ b/drivers/net/bnx2x/bnx2x.h\n@@ -1414,34 +1414,95 @@ struct bnx2x_func_init_params {\n #define BAR1 2\n #define BAR2 4\n \n+static inline void\n+bnx2x_reg_write8(struct bnx2x_softc *sc, size_t offset, uint8_t val)\n+{\n+\tPMD_DEBUG_PERIODIC_LOG(DEBUG, \"offset=0x%08lx val=0x%02x\",\n+\t\t\t (unsigned long)offset, val);\n+\t*((volatile uint8_t*)\n+\t ((uintptr_t)sc->bar[BAR0].base_addr + offset)) = val;\n+}\n+\n+static inline void\n+bnx2x_reg_write16(struct bnx2x_softc *sc, size_t offset, uint16_t val)\n+{\n+#ifdef RTE_LIBRTE_BNX2X_DEBUG_PERIODIC\n+\tif ((offset % 2) != 0)\n+\t\tPMD_DRV_LOG(NOTICE, \"Unaligned 16-bit write to 0x%08lx\",\n+\t\t\t (unsigned long)offset);\n+#endif\n+\tPMD_DEBUG_PERIODIC_LOG(DEBUG, \"offset=0x%08lx val=0x%04x\",\n+\t\t\t (unsigned long)offset, val);\n+\t*((volatile uint16_t*)\n+\t ((uintptr_t)sc->bar[BAR0].base_addr + offset)) = val;\n+}\n+\n+static inline void\n+bnx2x_reg_write32(struct bnx2x_softc *sc, size_t offset, uint32_t val)\n+{\n #ifdef RTE_LIBRTE_BNX2X_DEBUG_PERIODIC\n-uint8_t bnx2x_reg_read8(struct bnx2x_softc *sc, size_t offset);\n-uint16_t bnx2x_reg_read16(struct bnx2x_softc *sc, size_t offset);\n-uint32_t bnx2x_reg_read32(struct bnx2x_softc *sc, size_t offset);\n+\tif ((offset % 4) != 0)\n+\t\tPMD_DRV_LOG(NOTICE, \"Unaligned 32-bit write to 0x%08lx\",\n+\t\t\t (unsigned long)offset);\n+#endif\n \n-void bnx2x_reg_write8(struct bnx2x_softc *sc, size_t offset, uint8_t val);\n-void bnx2x_reg_write16(struct bnx2x_softc *sc, size_t offset, uint16_t val);\n-void bnx2x_reg_write32(struct bnx2x_softc *sc, size_t offset, uint32_t val);\n-#else\n-#define bnx2x_reg_write8(sc, offset, val)\\\n-\t*((volatile uint8_t*)((uintptr_t)sc->bar[BAR0].base_addr + offset)) = val\n+\tPMD_DEBUG_PERIODIC_LOG(DEBUG, \"offset=0x%08lx val=0x%08x\",\n+\t\t\t (unsigned long)offset, val);\n+\t*((volatile uint32_t*)\n+\t ((uintptr_t)sc->bar[BAR0].base_addr + offset)) = val;\n+}\n+\n+static inline uint8_t\n+bnx2x_reg_read8(struct bnx2x_softc *sc, size_t offset)\n+{\n+\tuint8_t val;\n+\n+\tval = (uint8_t)(*((volatile uint8_t*)\n+\t\t\t ((uintptr_t) sc->bar[BAR0].base_addr + offset)));\n+\tPMD_DEBUG_PERIODIC_LOG(DEBUG, \"offset=0x%08lx val=0x%02x\",\n+\t\t\t (unsigned long)offset, val);\n+\n+\treturn val;\n+}\n+\n+static inline uint16_t\n+bnx2x_reg_read16(struct bnx2x_softc *sc, size_t offset)\n+{\n+\tuint16_t val;\n \n-#define bnx2x_reg_write16(sc, offset, val)\\\n-\t*((volatile uint16_t*)((uintptr_t)sc->bar[BAR0].base_addr + offset)) = val\n+#ifdef RTE_LIBRTE_BNX2X_DEBUG_PERIODIC\n+\tif ((offset % 2) != 0)\n+\t\tPMD_DRV_LOG(NOTICE, \"Unaligned 16-bit read from 0x%08lx\",\n+\t\t\t (unsigned long)offset);\n+#endif\n \n-#define bnx2x_reg_write32(sc, offset, val)\\\n-\t*((volatile uint32_t*)((uintptr_t)sc->bar[BAR0].base_addr + offset)) = val\n+\tval = (uint16_t)(*((volatile uint16_t*)\n+\t\t\t ((uintptr_t) sc->bar[BAR0].base_addr + offset)));\n+\tPMD_DEBUG_PERIODIC_LOG(DEBUG, \"offset=0x%08lx val=0x%08x\",\n+\t\t\t (unsigned long)offset, val);\n \n-#define bnx2x_reg_read8(sc, offset)\\\n-\t(*((volatile uint8_t*)((uintptr_t)sc->bar[BAR0].base_addr + offset)))\n+\treturn val;\n+}\n \n-#define bnx2x_reg_read16(sc, offset)\\\n-\t(*((volatile uint16_t*)((uintptr_t)sc->bar[BAR0].base_addr + offset)))\n+static inline uint32_t\n+bnx2x_reg_read32(struct bnx2x_softc *sc, size_t offset)\n+{\n+\tuint32_t val;\n \n-#define bnx2x_reg_read32(sc, offset)\\\n-\t(*((volatile uint32_t*)((uintptr_t)sc->bar[BAR0].base_addr + offset)))\n+#ifdef RTE_LIBRTE_BNX2X_DEBUG_PERIODIC\n+\tif ((offset % 4) != 0)\n+\t\tPMD_DRV_LOG(NOTICE, \"Unaligned 32-bit read from 0x%08lx\",\n+\t\t\t (unsigned long)offset);\n #endif\n \n+\tval = (uint32_t)(*((volatile uint32_t*)\n+\t\t\t ((uintptr_t) sc->bar[BAR0].base_addr + offset)));\n+\tPMD_DEBUG_PERIODIC_LOG(DEBUG, \"offset=0x%08lx val=0x%08x\",\n+\t\t\t (unsigned long)offset, val);\n+\n+\treturn val;\n+}\n+\n #define REG_ADDR(sc, offset) (((uint64_t)sc->bar[BAR0].base_addr) + (offset))\n \n #define REG_RD8(sc, offset) bnx2x_reg_read8(sc, (offset))\ndiff --git a/drivers/net/bnx2x/debug.c b/drivers/net/bnx2x/debug.c\ndeleted file mode 100644\nindex cc50845..0000000\n--- a/drivers/net/bnx2x/debug.c\n+++ /dev/null\n@@ -1,96 +0,0 @@\n-/*-\n- * Copyright (c) 2007-2013 QLogic Corporation. All rights reserved.\n- *\n- * Eric Davis <edavis@broadcom.com>\n- * David Christensen <davidch@broadcom.com>\n- * Gary Zambrano <zambrano@broadcom.com>\n- *\n- * Copyright (c) 2013-2015 Brocade Communications Systems, Inc.\n- * Copyright (c) 2015 QLogic Corporation.\n- * All rights reserved.\n- * www.qlogic.com\n- *\n- * See LICENSE.bnx2x_pmd for copyright and licensing details.\n- */\n-\n-#include \"bnx2x.h\"\n-\n-\n-/*\n- * Debug versions of the 8/16/32 bit OS register read/write functions to\n- * capture/display values read/written from/to the controller.\n- */\n-void\n-bnx2x_reg_write8(struct bnx2x_softc *sc, size_t offset, uint8_t val)\n-{\n-\tPMD_DEBUG_PERIODIC_LOG(DEBUG, \"offset=0x%08lx val=0x%02x\", (unsigned long)offset, val);\n-\t*((volatile uint8_t*)((uintptr_t)sc->bar[BAR0].base_addr + offset)) = val;\n-}\n-\n-void\n-bnx2x_reg_write16(struct bnx2x_softc *sc, size_t offset, uint16_t val)\n-{\n-\tif ((offset % 2) != 0) {\n-\t\tPMD_DRV_LOG(NOTICE, \"Unaligned 16-bit write to 0x%08lx\",\n-\t\t\t (unsigned long)offset);\n-\t}\n-\n-\tPMD_DEBUG_PERIODIC_LOG(DEBUG, \"offset=0x%08lx val=0x%04x\", (unsigned long)offset, val);\n-\t*((volatile uint16_t*)((uintptr_t)sc->bar[BAR0].base_addr + offset)) = val;\n-}\n-\n-void\n-bnx2x_reg_write32(struct bnx2x_softc *sc, size_t offset, uint32_t val)\n-{\n-\tif ((offset % 4) != 0) {\n-\t\tPMD_DRV_LOG(NOTICE, \"Unaligned 32-bit write to 0x%08lx\",\n-\t\t\t (unsigned long)offset);\n-\t}\n-\n-\tPMD_DEBUG_PERIODIC_LOG(DEBUG, \"offset=0x%08lx val=0x%08x\", (unsigned long)offset, val);\n-\t*((volatile uint32_t*)((uintptr_t)sc->bar[BAR0].base_addr + offset)) = val;\n-}\n-\n-uint8_t\n-bnx2x_reg_read8(struct bnx2x_softc *sc, size_t offset)\n-{\n-\tuint8_t val;\n-\n-\tval = (uint8_t)(*((volatile uint8_t*)((uintptr_t)sc->bar[BAR0].base_addr + offset)));\n-\tPMD_DEBUG_PERIODIC_LOG(DEBUG, \"offset=0x%08lx val=0x%02x\", (unsigned long)offset, val);\n-\n-\treturn val;\n-}\n-\n-uint16_t\n-bnx2x_reg_read16(struct bnx2x_softc *sc, size_t offset)\n-{\n-\tuint16_t val;\n-\n-\tif ((offset % 2) != 0) {\n-\t\tPMD_DRV_LOG(NOTICE, \"Unaligned 16-bit read from 0x%08lx\",\n-\t\t\t (unsigned long)offset);\n-\t}\n-\n-\tval = (uint16_t)(*((volatile uint16_t*)((uintptr_t)sc->bar[BAR0].base_addr + offset)));\n-\tPMD_DEBUG_PERIODIC_LOG(DEBUG, \"offset=0x%08lx val=0x%08x\", (unsigned long)offset, val);\n-\n-\treturn val;\n-}\n-\n-uint32_t\n-bnx2x_reg_read32(struct bnx2x_softc *sc, size_t offset)\n-{\n-\tuint32_t val;\n-\n-\tif ((offset % 4) != 0) {\n-\t\tPMD_DRV_LOG(NOTICE, \"Unaligned 32-bit read from 0x%08lx\",\n-\t\t\t (unsigned long)offset);\n-\t\treturn 0;\n-\t}\n-\n-\tval = (uint32_t)(*((volatile uint32_t*)((uintptr_t)sc->bar[BAR0].base_addr + offset)));\n-\tPMD_DEBUG_PERIODIC_LOG(DEBUG, \"offset=0x%08lx val=0x%08x\", (unsigned long)offset, val);\n-\n-\treturn val;\n-}\n", "prefixes": [ "dpdk-dev", "v2", "10/10" ] }