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{
    "id": 17210,
    "url": "http://patchwork.dpdk.org/api/patches/17210/?format=api",
    "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/1479921780-9813-3-git-send-email-wenzhuo.lu@intel.com/",
    "project": {
        "id": 1,
        "url": "http://patchwork.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1479921780-9813-3-git-send-email-wenzhuo.lu@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1479921780-9813-3-git-send-email-wenzhuo.lu@intel.com",
    "date": "2016-11-23T17:22:46",
    "name": "[dpdk-dev,02/16] e1000/base: increase PHY PLL clock gate timing",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": true,
    "hash": "fad24506f4f3639892638e03c589387edb3dc428",
    "submitter": {
        "id": 258,
        "url": "http://patchwork.dpdk.org/api/people/258/?format=api",
        "name": "Wenzhuo Lu",
        "email": "wenzhuo.lu@intel.com"
    },
    "delegate": {
        "id": 319,
        "url": "http://patchwork.dpdk.org/api/users/319/?format=api",
        "username": "fyigit",
        "first_name": "Ferruh",
        "last_name": "Yigit",
        "email": "ferruh.yigit@amd.com"
    },
    "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/1479921780-9813-3-git-send-email-wenzhuo.lu@intel.com/mbox/",
    "series": [],
    "comments": "http://patchwork.dpdk.org/api/patches/17210/comments/",
    "check": "warning",
    "checks": "http://patchwork.dpdk.org/api/patches/17210/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 4AD565599;\n\tThu, 24 Nov 2016 02:32:54 +0100 (CET)",
            "from mga07.intel.com (mga07.intel.com [134.134.136.100])\n\tby dpdk.org (Postfix) with ESMTP id A5C8E2BA3\n\tfor <dev@dpdk.org>; Thu, 24 Nov 2016 02:32:07 +0100 (CET)",
            "from fmsmga006.fm.intel.com ([10.253.24.20])\n\tby orsmga105.jf.intel.com with ESMTP; 23 Nov 2016 17:32:07 -0800",
            "from dpdk26.sh.intel.com ([10.239.128.228])\n\tby fmsmga006.fm.intel.com with ESMTP; 23 Nov 2016 17:32:06 -0800"
        ],
        "X-ExtLoop1": "1",
        "X-IronPort-AV": "E=Sophos;i=\"5.31,689,1473145200\"; d=\"scan'208\";a=\"35041852\"",
        "From": "Wenzhuo Lu <wenzhuo.lu@intel.com>",
        "To": "dev@dpdk.org",
        "Cc": "Wenzhuo Lu <wenzhuo.lu@intel.com>",
        "Date": "Wed, 23 Nov 2016 12:22:46 -0500",
        "Message-Id": "<1479921780-9813-3-git-send-email-wenzhuo.lu@intel.com>",
        "X-Mailer": "git-send-email 1.9.3",
        "In-Reply-To": "<1479921780-9813-1-git-send-email-wenzhuo.lu@intel.com>",
        "References": "<1479921780-9813-1-git-send-email-wenzhuo.lu@intel.com>",
        "Subject": "[dpdk-dev] [PATCH 02/16] e1000/base: increase PHY PLL clock gate\n\ttiming",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "patches and discussions about DPDK <dev.dpdk.org>",
        "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://dpdk.org/ml/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "To avoid packet loss, HW team concluded that Phase Lock\nLoop (PLL) clock gate time need to be increased for\nnon 1 gig speeds.\n\nSigned-off-by: Wenzhuo Lu <wenzhuo.lu@intel.com>\n---\n drivers/net/e1000/base/e1000_ich8lan.c | 15 +++++++++++++++\n drivers/net/e1000/base/e1000_ich8lan.h |  3 +++\n 2 files changed, 18 insertions(+)",
    "diff": "diff --git a/drivers/net/e1000/base/e1000_ich8lan.c b/drivers/net/e1000/base/e1000_ich8lan.c\nindex 4a5cef0..7aea8dd 100644\n--- a/drivers/net/e1000/base/e1000_ich8lan.c\n+++ b/drivers/net/e1000/base/e1000_ich8lan.c\n@@ -1486,6 +1486,21 @@ STATIC s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)\n \t\t\temi_addr = I217_RX_CONFIG;\n \t\tret_val = e1000_write_emi_reg_locked(hw, emi_addr, emi_val);\n \n+\n+\t\tif (hw->mac.type >= e1000_pch_lpt) {\n+\t\t\tu16 phy_reg;\n+\n+\t\t\thw->phy.ops.read_reg_locked(hw, I217_PLL_CLOCK_GATE_REG,\n+\t\t\t\t\t\t    &phy_reg);\n+\t\t\tphy_reg &= ~I217_PLL_CLOCK_GATE_MASK;\n+\t\t\tif (speed == SPEED_100 || speed == SPEED_10)\n+\t\t\t\tphy_reg |= 0x3E8;\n+\t\t\telse\n+\t\t\t\tphy_reg |= 0xFA;\n+\t\t\thw->phy.ops.write_reg_locked(hw,\n+\t\t\t\t\t\t     I217_PLL_CLOCK_GATE_REG,\n+\t\t\t\t\t\t     phy_reg);\n+\t\t }\n \t\thw->phy.ops.release(hw);\n \n \t\tif (ret_val)\ndiff --git a/drivers/net/e1000/base/e1000_ich8lan.h b/drivers/net/e1000/base/e1000_ich8lan.h\nindex 33e77fb..6aa9288 100644\n--- a/drivers/net/e1000/base/e1000_ich8lan.h\n+++ b/drivers/net/e1000/base/e1000_ich8lan.h\n@@ -237,6 +237,9 @@ POSSIBILITY OF SUCH DAMAGE.\n #define HV_PM_CTRL_PLL_STOP_IN_K1_GIGA\t0x100\n #define HV_PM_CTRL_K1_ENABLE\t\t0x4000\n \n+#define I217_PLL_CLOCK_GATE_REG\tPHY_REG(772, 28)\n+#define I217_PLL_CLOCK_GATE_MASK\t0x07FF\n+\n #define SW_FLAG_TIMEOUT\t\t1000 /* SW Semaphore flag timeout in ms */\n \n /* Inband Control */\n",
    "prefixes": [
        "dpdk-dev",
        "02/16"
    ]
}