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GET /api/patches/40688/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 40688,
    "url": "http://patchwork.dpdk.org/api/patches/40688/?format=api",
    "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/1528282041-20380-2-git-send-email-radu.nicolau@intel.com/",
    "project": {
        "id": 1,
        "url": "http://patchwork.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1528282041-20380-2-git-send-email-radu.nicolau@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1528282041-20380-2-git-send-email-radu.nicolau@intel.com",
    "date": "2018-06-06T10:47:21",
    "name": "[dpdk-dev,2/2] examples/l3fw-power: add high/regular performance cores option",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "115feae1fec640d1db799f2a53431fb3b0508b9a",
    "submitter": {
        "id": 743,
        "url": "http://patchwork.dpdk.org/api/people/743/?format=api",
        "name": "Radu Nicolau",
        "email": "radu.nicolau@intel.com"
    },
    "delegate": {
        "id": 1,
        "url": "http://patchwork.dpdk.org/api/users/1/?format=api",
        "username": "tmonjalo",
        "first_name": "Thomas",
        "last_name": "Monjalon",
        "email": "thomas@monjalon.net"
    },
    "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/1528282041-20380-2-git-send-email-radu.nicolau@intel.com/mbox/",
    "series": [
        {
            "id": 17,
            "url": "http://patchwork.dpdk.org/api/series/17/?format=api",
            "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=17",
            "date": "2018-06-06T10:47:20",
            "name": "[dpdk-dev,1/2] power: add get capabilities API",
            "version": 1,
            "mbox": "http://patchwork.dpdk.org/series/17/mbox/"
        }
    ],
    "comments": "http://patchwork.dpdk.org/api/patches/40688/comments/",
    "check": "warning",
    "checks": "http://patchwork.dpdk.org/api/patches/40688/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<radu.nicolau@intel.com>",
        "Received": [
            "from mga17.intel.com (mga17.intel.com [192.55.52.151])\n\tby dpdk.org (Postfix) with ESMTP id 3795A1B67C\n\tfor <dev@dpdk.org>; Wed,  6 Jun 2018 12:53:58 +0200 (CEST)",
            "from orsmga001.jf.intel.com ([10.7.209.18])\n\tby fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t06 Jun 2018 03:53:55 -0700",
            "from silpixa00383879.ir.intel.com (HELO\n\tsilpixa00383879.ger.corp.intel.com) ([10.237.223.127])\n\tby orsmga001.jf.intel.com with ESMTP; 06 Jun 2018 03:53:54 -0700"
        ],
        "X-Amp-Result": "SKIPPED(no attachment in message)",
        "X-Amp-File-Uploaded": "False",
        "X-ExtLoop1": "1",
        "X-IronPort-AV": "E=Sophos;i=\"5.49,483,1520924400\"; d=\"scan'208\";a=\"62245981\"",
        "From": "Radu Nicolau <radu.nicolau@intel.com>",
        "To": "dev@dpdk.org",
        "Cc": "david.hunt@intel.com, chris.macnamara@intel.com,\n\tmichael.j.glynn@intel.com, Radu Nicolau <radu.nicolau@intel.com>",
        "Date": "Wed,  6 Jun 2018 11:47:21 +0100",
        "Message-Id": "<1528282041-20380-2-git-send-email-radu.nicolau@intel.com>",
        "X-Mailer": "git-send-email 2.7.5",
        "In-Reply-To": "<1528282041-20380-1-git-send-email-radu.nicolau@intel.com>",
        "References": "<1528282041-20380-1-git-send-email-radu.nicolau@intel.com>",
        "Subject": "[dpdk-dev] [PATCH 2/2] examples/l3fw-power: add high/regular\n\tperformance cores option",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://dpdk.org/ml/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "X-List-Received-Date": "Wed, 06 Jun 2018 10:53:59 -0000"
    },
    "content": "Added high/regular performance core pinning configuration options\nthat can be used in place of the existing 'config' option.\n\n'--high-perf-cores CORELIST' option allow the user to specify a high performance\ncores list; if this option is not used and the 'perf-config' option is used, the\napplication will query the system using the rte_power library in order to get a list\nof available high performance cores. The cores that are considered high performance\nare the cores that have turbo enabled.\n\n'--perf-config (port,queue,hi_perf,lcore_index)[(port,queue,hi_perf,lcore_index)]'\noption is similar to the existing config option, the cores are specified\nas indices for bins containing high or regular performance cores.\n\nExample:\n\nl3fwd-power -l 6,7 -- -p 0xff --high-perf-cores 6 --perf-config=\"(0,0,0,0),(1,0,1,0)\"\n\ncores 6 and 7 are used, core 6 is specified as a high performance core.\nport 0 queue 0 will use a regular performance core, index 0 (core 7)\nport 1 queue 0 will use a high performance core, index 0 (core 6)\n\nSigned-off-by: Radu Nicolau <radu.nicolau@intel.com>\n---\n examples/l3fwd-power/Makefile    |   4 +-\n examples/l3fwd-power/main.c      |  74 ++++++++++---\n examples/l3fwd-power/main.h      |  20 ++++\n examples/l3fwd-power/meson.build |   4 +-\n examples/l3fwd-power/perf_core.c | 229 +++++++++++++++++++++++++++++++++++++++\n examples/l3fwd-power/perf_core.h |  12 ++\n 6 files changed, 322 insertions(+), 21 deletions(-)\n create mode 100644 examples/l3fwd-power/main.h\n create mode 100644 examples/l3fwd-power/perf_core.c\n create mode 100644 examples/l3fwd-power/perf_core.h",
    "diff": "diff --git a/examples/l3fwd-power/Makefile b/examples/l3fwd-power/Makefile\nindex 390b7d6..1a46033 100644\n--- a/examples/l3fwd-power/Makefile\n+++ b/examples/l3fwd-power/Makefile\n@@ -1,11 +1,11 @@\n # SPDX-License-Identifier: BSD-3-Clause\n-# Copyright(c) 2010-2014 Intel Corporation\n+# Copyright(c) 2010-2018 Intel Corporation\n \n # binary name\n APP = l3fwd-power\n \n # all source are stored in SRCS-y\n-SRCS-y := main.c\n+SRCS-y := main.c perf_core.c\n \n # Build using pkg-config variables if possible\n $(shell pkg-config --exists libdpdk)\ndiff --git a/examples/l3fwd-power/main.c b/examples/l3fwd-power/main.c\nindex 596d645..36f31de 100644\n--- a/examples/l3fwd-power/main.c\n+++ b/examples/l3fwd-power/main.c\n@@ -1,5 +1,5 @@\n /* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(c) 2010-2016 Intel Corporation\n+ * Copyright(c) 2010-2018 Intel Corporation\n  */\n \n #include <stdio.h>\n@@ -44,6 +44,9 @@\n #include <rte_power.h>\n #include <rte_spinlock.h>\n \n+#include \"perf_core.h\"\n+#include \"main.h\"\n+\n #define RTE_LOGTYPE_L3FWD_POWER RTE_LOGTYPE_USER1\n \n #define MAX_PKT_BURST 32\n@@ -155,14 +158,7 @@ struct lcore_rx_queue {\n #define MAX_RX_QUEUE_INTERRUPT_PER_PORT 16\n \n \n-#define MAX_LCORE_PARAMS 1024\n-struct lcore_params {\n-\tuint16_t port_id;\n-\tuint8_t queue_id;\n-\tuint8_t lcore_id;\n-} __rte_cache_aligned;\n-\n-static struct lcore_params lcore_params_array[MAX_LCORE_PARAMS];\n+struct lcore_params lcore_params_array[MAX_LCORE_PARAMS];\n static struct lcore_params lcore_params_array_default[] = {\n \t{0, 0, 2},\n \t{0, 1, 2},\n@@ -175,8 +171,8 @@ static struct lcore_params lcore_params_array_default[] = {\n \t{3, 1, 3},\n };\n \n-static struct lcore_params * lcore_params = lcore_params_array_default;\n-static uint16_t nb_lcore_params = sizeof(lcore_params_array_default) /\n+struct lcore_params * lcore_params = lcore_params_array_default;\n+uint16_t nb_lcore_params = sizeof(lcore_params_array_default) /\n \t\t\t\tsizeof(lcore_params_array_default[0]);\n \n static struct rte_eth_conf port_conf = {\n@@ -1121,10 +1117,15 @@ print_usage(const char *prgname)\n {\n \tprintf (\"%s [EAL options] -- -p PORTMASK -P\"\n \t\t\"  [--config (port,queue,lcore)[,(port,queue,lcore]]\"\n+\t\t\"  [--high-perf-cores CORELIST\"\n+\t\t\"  [--perf-config (port,queue,hi_perf,lcore_index)[,(port,queue,hi_perf,lcore_index]]\"\n \t\t\"  [--enable-jumbo [--max-pkt-len PKTLEN]]\\n\"\n \t\t\"  -p PORTMASK: hexadecimal bitmask of ports to configure\\n\"\n \t\t\"  -P : enable promiscuous mode\\n\"\n \t\t\"  --config (port,queue,lcore): rx queues configuration\\n\"\n+\t\t\"  --high-perf-cores CORELIST: list of high performance cores\\n\"\n+\t\t\"  --perf-config: similar as config, cores specified as indices\"\n+\t\t\" for bins containing high or regular performance cores\\n\"\n \t\t\"  --no-numa: optional, disable numa awareness\\n\"\n \t\t\"  --enable-jumbo: enable jumbo frame\"\n \t\t\" which max packet len is PKTLEN in decimal (64-9600)\\n\"\n@@ -1234,6 +1235,8 @@ parse_args(int argc, char **argv)\n \tchar *prgname = argv[0];\n \tstatic struct option lgopts[] = {\n \t\t{\"config\", 1, 0, 0},\n+\t\t{\"perf-config\", 1, 0, 0},\n+\t\t{\"high-perf-cores\", 1, 0, 0},\n \t\t{\"no-numa\", 0, 0, 0},\n \t\t{\"enable-jumbo\", 0, 0, 0},\n \t\t{CMD_LINE_OPT_PARSE_PTYPE, 0, 0, 0},\n@@ -1272,6 +1275,26 @@ parse_args(int argc, char **argv)\n \t\t\t}\n \n \t\t\tif (!strncmp(lgopts[option_index].name,\n+\t\t\t\t\t\"perf-config\", 11)) {\n+\t\t\t\tret = parse_perf_config(optarg);\n+\t\t\t\tif (ret) {\n+\t\t\t\t\tprintf(\"invalid perf-config\\n\");\n+\t\t\t\t\tprint_usage(prgname);\n+\t\t\t\t\treturn -1;\n+\t\t\t\t}\n+\t\t\t}\n+\n+\t\t\tif (!strncmp(lgopts[option_index].name,\n+\t\t\t\t\t\"high-perf-cores\", 15)) {\n+\t\t\t\tret = parse_perf_core_list(optarg);\n+\t\t\t\tif (ret) {\n+\t\t\t\t\tprintf(\"invalid high-perf-cores\\n\");\n+\t\t\t\t\tprint_usage(prgname);\n+\t\t\t\t\treturn -1;\n+\t\t\t\t}\n+\t\t\t}\n+\n+\t\t\tif (!strncmp(lgopts[option_index].name,\n \t\t\t\t\t\t\"no-numa\", 7)) {\n \t\t\t\tprintf(\"numa is disabled \\n\");\n \t\t\t\tnuma_on = 0;\n@@ -1609,6 +1632,23 @@ static int check_ptype(uint16_t portid)\n \n }\n \n+static int\n+init_power_library(void)\n+{\n+\tint ret = 0, lcore_id;\n+\tfor (lcore_id = 0; lcore_id < RTE_MAX_LCORE; lcore_id++) {\n+\t\tif (rte_lcore_is_enabled(lcore_id)) {\n+\t\t\t/* init power management library */\n+\t\t\tret = rte_power_init(lcore_id);\n+\t\t\tif (ret)\n+\t\t\t\tRTE_LOG(ERR, POWER,\n+\t\t\t\t\"Library initialization failed on core %u\\n\",\n+\t\t\t\tlcore_id);\n+\t\t}\n+\t}\n+\treturn ret;\n+}\n+\n int\n main(int argc, char **argv)\n {\n@@ -1643,6 +1683,12 @@ main(int argc, char **argv)\n \tif (ret < 0)\n \t\trte_exit(EXIT_FAILURE, \"Invalid L3FWD parameters\\n\");\n \n+\tif (init_power_library())\n+\t\trte_exit(EXIT_FAILURE, \"init_power_library failed\\n\");\n+\n+\tif (update_lcore_params() < 0)\n+\t\trte_exit(EXIT_FAILURE, \"update_lcore_params failed\\n\");\n+\n \tif (check_lcore_params() < 0)\n \t\trte_exit(EXIT_FAILURE, \"check_lcore_params failed\\n\");\n \n@@ -1773,12 +1819,6 @@ main(int argc, char **argv)\n \t\tif (rte_lcore_is_enabled(lcore_id) == 0)\n \t\t\tcontinue;\n \n-\t\t/* init power management library */\n-\t\tret = rte_power_init(lcore_id);\n-\t\tif (ret)\n-\t\t\tRTE_LOG(ERR, POWER,\n-\t\t\t\t\"Library initialization failed on core %u\\n\", lcore_id);\n-\n \t\t/* init timer structures for each enabled lcore */\n \t\trte_timer_init(&power_timers[lcore_id]);\n \t\thz = rte_get_timer_hz();\ndiff --git a/examples/l3fwd-power/main.h b/examples/l3fwd-power/main.h\nnew file mode 100644\nindex 0000000..258de98\n--- /dev/null\n+++ b/examples/l3fwd-power/main.h\n@@ -0,0 +1,20 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2010-2018 Intel Corporation\n+ */\n+\n+#ifndef _MAIN_H_\n+#define _MAIN_H_\n+\n+\n+#define MAX_LCORE_PARAMS 1024\n+struct lcore_params {\n+\tuint16_t port_id;\n+\tuint8_t queue_id;\n+\tuint8_t lcore_id;\n+} __rte_cache_aligned;\n+\n+extern struct lcore_params *lcore_params;\n+extern uint16_t nb_lcore_params;\n+extern struct lcore_params lcore_params_array[];\n+\n+#endif /* _MAIN_H_ */\ndiff --git a/examples/l3fwd-power/meson.build b/examples/l3fwd-power/meson.build\nindex f633a0f..20c8054 100644\n--- a/examples/l3fwd-power/meson.build\n+++ b/examples/l3fwd-power/meson.build\n@@ -1,5 +1,5 @@\n # SPDX-License-Identifier: BSD-3-Clause\n-# Copyright(c) 2017 Intel Corporation\n+# Copyright(c) 2018 Intel Corporation\n \n # meson file, for building this example as part of a main DPDK build.\n #\n@@ -11,5 +11,5 @@ if host_machine.system() != 'linux'\n endif\n deps += ['power', 'timer', 'lpm', 'hash']\n sources = files(\n-\t'main.c'\n+\t'main.c', 'perf_core.c'\n )\ndiff --git a/examples/l3fwd-power/perf_core.c b/examples/l3fwd-power/perf_core.c\nnew file mode 100644\nindex 0000000..d11b46f\n--- /dev/null\n+++ b/examples/l3fwd-power/perf_core.c\n@@ -0,0 +1,229 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2010-2018 Intel Corporation\n+ */\n+\n+#include <stdio.h>\n+#include <string.h>\n+\n+#include <rte_common.h>\n+#include <rte_memory.h>\n+#include <rte_lcore.h>\n+#include <rte_power.h>\n+#include <rte_string_fns.h>\n+\n+#include \"perf_core.h\"\n+#include \"main.h\"\n+\n+\n+static uint16_t high_perf_lcores[RTE_MAX_LCORE];\n+static uint16_t nb_high_perf_lcores;\n+\n+struct perf_lcore_params {\n+\tuint16_t port_id;\n+\tuint8_t queue_id;\n+\tuint8_t high_perf;\n+\tuint8_t lcore_idx;\n+} __rte_cache_aligned;\n+\n+static struct perf_lcore_params perf_lcore_params[MAX_LCORE_PARAMS];\n+static uint16_t nb_perf_lcore_params;\n+\n+int\n+update_lcore_params(void)\n+{\n+\tuint8_t non_perf_lcores[RTE_MAX_LCORE];\n+\tuint16_t nb_non_perf_lcores = 0;\n+\tint i, j, ret;\n+\n+\t/* if perf-config option was not used do nothing */\n+\tif (nb_perf_lcore_params == 0)\n+\t\treturn 0;\n+\n+\t/* if  high-perf-cores option was not used query every available core */\n+\tif (nb_high_perf_lcores == 0) {\n+\t\tfor (i = 0; i < RTE_MAX_LCORE; i++) {\n+\t\t\tif (rte_lcore_is_enabled(i)) {\n+\t\t\t\tstruct rte_power_core_capabilities caps;\n+\t\t\t\tret = rte_power_get_capabilities(i, &caps);\n+\t\t\t\tif (ret == 0 && caps.turbo) {\n+\t\t\t\t\thigh_perf_lcores[nb_high_perf_lcores] = i;\n+\t\t\t\t\tnb_high_perf_lcores++;\n+\t\t\t\t}\n+\t\t\t}\n+\t\t}\n+\t}\n+\n+\t/* create a list on non high performance cores*/\n+\tfor (i = 0; i < RTE_MAX_LCORE; i++) {\n+\t\tif (rte_lcore_is_enabled(i)) {\n+\t\t\tint hp = 0;\n+\t\t\tfor (j = 0; j < nb_high_perf_lcores; j++) {\n+\t\t\t\tif (high_perf_lcores[j] == i) {\n+\t\t\t\t\thp = 1;\n+\t\t\t\t\tbreak;\n+\t\t\t\t}\n+\t\t\t}\n+\t\t\tif (!hp)\n+\t\t\t\tnon_perf_lcores[nb_non_perf_lcores++] = i;\n+\t\t}\n+\t}\n+\n+\t/* update the lcore config */\n+\tfor (i = 0; i < nb_perf_lcore_params; i++) {\n+\t\tint lcore = -1;\n+\t\tif (perf_lcore_params[i].high_perf) {\n+\t\t\tif (perf_lcore_params[i].lcore_idx < nb_high_perf_lcores)\n+\t\t\t\tlcore = high_perf_lcores[perf_lcore_params[i].lcore_idx];\n+\t\t} else {\n+\t\t\tif (perf_lcore_params[i].lcore_idx < nb_non_perf_lcores)\n+\t\t\t\tlcore = non_perf_lcores[perf_lcore_params[i].lcore_idx];\n+\t\t}\n+\n+\t\tif (lcore < 0) {\n+\t\t\tprintf(\"Performance cores configuration error\\n\");\n+\t\t\treturn -1;\n+\t\t}\n+\n+\t\tlcore_params_array[i].lcore_id = lcore;\n+\t\tlcore_params_array[i].queue_id = perf_lcore_params[i].queue_id;\n+\t\tlcore_params_array[i].port_id = perf_lcore_params[i].port_id;\n+\t}\n+\n+\tlcore_params = lcore_params_array;\n+\tnb_lcore_params = nb_perf_lcore_params;\n+\n+\tprintf(\"Updated performance core configuration\\n\");\n+\tfor (i = 0; i < nb_perf_lcore_params; i++)\n+\t\tprintf(\"\\t(%d,%d,%d)\\n\", lcore_params[i].port_id,\n+\t\t\t\tlcore_params[i].queue_id,\n+\t\t\t\tlcore_params[i].lcore_id);\n+\n+\treturn 0;\n+}\n+\n+int\n+parse_perf_config(const char *q_arg)\n+{\n+\tchar s[256];\n+\tconst char *p, *p0 = q_arg;\n+\tchar *end;\n+\tenum fieldnames {\n+\t\tFLD_PORT = 0,\n+\t\tFLD_QUEUE,\n+\t\tFLD_LCORE_HP,\n+\t\tFLD_LCORE_IDX,\n+\t\t_NUM_FLD\n+\t};\n+\tunsigned long int_fld[_NUM_FLD];\n+\tchar *str_fld[_NUM_FLD];\n+\tint i;\n+\tunsigned int size;\n+\n+\tnb_perf_lcore_params = 0;\n+\n+\twhile ((p = strchr(p0, '(')) != NULL) {\n+\t\t++p;\n+\t\tif ((p0 = strchr(p, ')')) == NULL)\n+\t\t\treturn -1;\n+\n+\t\tsize = p0 - p;\n+\t\tif (size >= sizeof(s))\n+\t\t\treturn -1;\n+\n+\t\tsnprintf(s, sizeof(s), \"%.*s\", size, p);\n+\t\tif (rte_strsplit(s, sizeof(s), str_fld, _NUM_FLD, ',') !=\n+\t\t\t\t\t\t\t\t_NUM_FLD)\n+\t\t\treturn -1;\n+\t\tfor (i = 0; i < _NUM_FLD; i++) {\n+\t\t\terrno = 0;\n+\t\t\tint_fld[i] = strtoul(str_fld[i], &end, 0);\n+\t\t\tif (errno != 0 || end == str_fld[i] || int_fld[i] >\n+\t\t\t\t\t\t\t\t\t255)\n+\t\t\t\treturn -1;\n+\t\t}\n+\t\tif (nb_perf_lcore_params >= MAX_LCORE_PARAMS) {\n+\t\t\tprintf(\"exceeded max number of lcore params: %hu\\n\",\n+\t\t\t\t\tnb_perf_lcore_params);\n+\t\t\treturn -1;\n+\t\t}\n+\t\tperf_lcore_params[nb_perf_lcore_params].port_id =\n+\t\t\t\t(uint8_t)int_fld[FLD_PORT];\n+\t\tperf_lcore_params[nb_perf_lcore_params].queue_id =\n+\t\t\t\t(uint8_t)int_fld[FLD_QUEUE];\n+\t\tperf_lcore_params[nb_perf_lcore_params].high_perf =\n+\t\t\t\t!!(uint8_t)int_fld[FLD_LCORE_HP];\n+\t\tperf_lcore_params[nb_perf_lcore_params].lcore_idx =\n+\t\t\t\t(uint8_t)int_fld[FLD_LCORE_IDX];\n+\t\t++nb_perf_lcore_params;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+int\n+parse_perf_core_list(const char *corelist)\n+{\n+\tint i, idx = 0;\n+\tunsigned int count = 0;\n+\tchar *end = NULL;\n+\tint min, max;\n+\n+\tif (corelist == NULL) {\n+\t\tprintf(\"invalid core list\\n\");\n+\t\treturn -1;\n+\t}\n+\n+\n+\t/* Remove all blank characters ahead and after */\n+\twhile (isblank(*corelist))\n+\t\tcorelist++;\n+\ti = strlen(corelist);\n+\twhile ((i > 0) && isblank(corelist[i - 1]))\n+\t\ti--;\n+\n+\t/* Get list of cores */\n+\tmin = RTE_MAX_LCORE;\n+\tdo {\n+\t\twhile (isblank(*corelist))\n+\t\t\tcorelist++;\n+\t\tif (*corelist == '\\0')\n+\t\t\treturn -1;\n+\t\terrno = 0;\n+\t\tidx = strtoul(corelist, &end, 10);\n+\t\tif (errno || end == NULL)\n+\t\t\treturn -1;\n+\t\twhile (isblank(*end))\n+\t\t\tend++;\n+\t\tif (*end == '-') {\n+\t\t\tmin = idx;\n+\t\t} else if ((*end == ',') || (*end == '\\0')) {\n+\t\t\tmax = idx;\n+\t\t\tif (min == RTE_MAX_LCORE)\n+\t\t\t\tmin = idx;\n+\t\t\tfor (idx = min; idx <= max; idx++) {\n+\t\t\t\thigh_perf_lcores[count] = idx;\n+\t\t\t\tcount++;\n+\t\t\t}\n+\t\t\tmin = RTE_MAX_LCORE;\n+\t\t} else {\n+\t\t\tprintf(\"invalid core list\\n\");\n+\t\t\treturn -1;\n+\t\t}\n+\t\tcorelist = end + 1;\n+\t} while (*end != '\\0');\n+\n+\tif (count == 0) {\n+\t\tprintf(\"invalid core list\\n\");\n+\t\treturn -1;\n+\t}\n+\n+\tnb_high_perf_lcores = count;\n+\n+\tprintf(\"Configured %d high performance cores\\n\", nb_high_perf_lcores);\n+\tfor (i = 0; i < nb_high_perf_lcores; i++)\n+\t\tprintf(\"\\tHigh performance core %d %d\\n\",\n+\t\t\t\ti, high_perf_lcores[i]);\n+\n+\treturn 0;\n+}\n+\ndiff --git a/examples/l3fwd-power/perf_core.h b/examples/l3fwd-power/perf_core.h\nnew file mode 100644\nindex 0000000..7b7b747\n--- /dev/null\n+++ b/examples/l3fwd-power/perf_core.h\n@@ -0,0 +1,12 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2010-2018 Intel Corporation\n+ */\n+\n+#ifndef _PERF_CORE_H_\n+#define _PERF_CORE_H_\n+\n+int parse_perf_config(const char *q_arg);\n+int parse_perf_core_list(const char *corelist);\n+int update_lcore_params(void);\n+\n+#endif /* _PERF_CORE_H_ */\n",
    "prefixes": [
        "dpdk-dev",
        "2/2"
    ]
}