Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/40863/?format=api
{ "id": 40863, "url": "http://patchwork.dpdk.org/api/patches/40863/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/1528476325-15585-3-git-send-email-anoob.joseph@caviumnetworks.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1528476325-15585-3-git-send-email-anoob.joseph@caviumnetworks.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1528476325-15585-3-git-send-email-anoob.joseph@caviumnetworks.com", "date": "2018-06-08T16:45:11", "name": "[dpdk-dev,02/16] crypto/cpt/base: add hardware definitions Cavium CPT", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "de3d10f23c32ecc33dbe7f82c5bad606dde05213", "submitter": { "id": 893, "url": "http://patchwork.dpdk.org/api/people/893/?format=api", "name": "Anoob Joseph", "email": "anoob.joseph@caviumnetworks.com" }, "delegate": { "id": 6690, "url": "http://patchwork.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/1528476325-15585-3-git-send-email-anoob.joseph@caviumnetworks.com/mbox/", "series": [ { "id": 58, "url": "http://patchwork.dpdk.org/api/series/58/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=58", "date": "2018-06-08T16:45:09", "name": "Adding Cavium's crypto device(CPT) driver", "version": 1, "mbox": "http://patchwork.dpdk.org/series/58/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/40863/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/40863/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 54DFE7ED7;\n\tFri, 8 Jun 2018 18:48:52 +0200 (CEST)", "from NAM04-SN1-obe.outbound.protection.outlook.com\n\t(mail-eopbgr700056.outbound.protection.outlook.com [40.107.70.56])\n\tby dpdk.org (Postfix) with ESMTP id 2871D7ED7\n\tfor <dev@dpdk.org>; Fri, 8 Jun 2018 18:48:50 +0200 (CEST)", "from ajoseph83.caveonetworks.com.caveonetworks.com (115.113.156.2)\n\tby SN6PR07MB4911.namprd07.prod.outlook.com (2603:10b6:805:3c::29)\n\twith Microsoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.820.15;\n\tFri, 8 Jun 2018 16:48:44 +0000" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=CAVIUMNETWORKS.onmicrosoft.com; s=selector1-cavium-com;\n\th=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n\tbh=AKv1kGrgOg2WJQ1WCjfdb6xwSUL7YYQwAlH0JviJ0BA=;\n\tb=F4Lqbp97Ke+VVI3NXy+NDe8mxc6YI6e3Lt6fWlBIEuRqXST5tGfQVPqKfSgVH91Sj9Rv+fZVIIzxOeKJYKMBqpX8qrhFJ1sBGv5fbno5HPlOwuD+uEN/PM8VwHAm4Bo0Xadeuv8HoC5TxS9epor7unurg02B7NP/PTBzbDrHGro=", "Authentication-Results": "spf=none (sender IP is )\n\tsmtp.mailfrom=Anoob.Joseph@cavium.com; ", "From": "Anoob Joseph <anoob.joseph@caviumnetworks.com>", "To": "Akhil Goyal <akhil.goyal@nxp.com>,\n\tPablo de Lara <pablo.de.lara.guarch@intel.com>,\n\tThomas Monjalon <thomas@monjalon.net>", "Cc": "Nithin Dabilpuram <nithin.dabilpuram@cavium.com>,\n\tAnkur Dwivedi <ankur.dwivedi@cavium.com>,\n\tJerin Jacob <jerin.jacob@caviumnetworks.com>,\n\tMurthy NSSR <Nidadavolu.Murthy@cavium.com>,\n\tNarayana Prasad <narayanaprasad.athreya@caviumnetworks.com>,\n\tRagothaman Jayaraman <Ragothaman.Jayaraman@cavium.com>,\n\tSrisivasubramanian Srinivasan\n\t<Srisivasubramanian.Srinivasan@cavium.com>, dev@dpdk.org", "Date": "Fri, 8 Jun 2018 22:15:11 +0530", "Message-Id": "<1528476325-15585-3-git-send-email-anoob.joseph@caviumnetworks.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1528476325-15585-1-git-send-email-anoob.joseph@caviumnetworks.com>", "References": "<1528476325-15585-1-git-send-email-anoob.joseph@caviumnetworks.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[115.113.156.2]", "X-ClientProxiedBy": "BM1PR01CA0071.INDPRD01.PROD.OUTLOOK.COM\n\t(2603:1096:b00:1::11) To SN6PR07MB4911.namprd07.prod.outlook.com\n\t(2603:10b6:805:3c::29)", "X-MS-PublicTrafficType": "Email", "X-Microsoft-Antispam": "UriScan:; BCL:0; PCL:0;\n\tRULEID:(7020095)(4652020)(5600026)(4534165)(7168020)(4627221)(201703031133081)(201702281549075)(2017052603328)(7153060)(7193020);\n\tSRVR:SN6PR07MB4911; ", "X-Microsoft-Exchange-Diagnostics": [ "1; SN6PR07MB4911;\n\t3:R0LiZ2yF3P2KfM8QQu+rSvjlEP4sjpLtJy0Ov9ioq+cDCDiVAZmD0JZOg6NaJ+oH8ddymh++uBXNTgeBi/48GSmLG/SpY+CI6Bqc6xS4yZJRnfZbvQOIVRechI/Xi780LTreDEUjJtvPok+Irgp+KbHEObaa0xqbdXLf0M2k5+L3gyJi62GfqbiGZwmR7jLnHnBzn+EJs9GHePu0VgdCm3Tu8LFQjB210i7m82kE7wxHXj0LJ52aDgxJ6DjTNSJf;\n\t25:RPe2F0tZchqCJZiJ00s9LdQX5CYhqr+as4azmbq+VdCRVG+oScSvyzoF9/Jdn2MrCpyq88QvQO8PuQ238YZrsCJW0eoP2SE3w4SU44210GiMq2Cx+6UidNeamaBUZd4Lcx0FErP8HhmKKxIR1ZeZO7xIGJXV2XrZ9PLE/O1SV5sFg/YYTX4Qd6zBAAH1zVCTyl3FfQhkfAvFFUi22g5Locqo7gbBn6Sy0uTDkNSTFgdC7eCdstJysFzrkOqPH1YwFSNr2b+0UGZr20q6QYnvO4l+4W2FAUYFNyNj4QQqQJ3Qr0Elg2u+0GN0qWUcH/peP7/86EYDPXWTwLDN/aZUGA==;\n\t31:6jh+/aYwpLnVNVinqAm3CcstSFJhhqlKasuDOhvp4ewmifAPbRloaeWiI/dMdyQErSxigl/En43hAIO1f9qu/aDBHvWoMGYOvempRSDsphicaRbW5mTc0NvP7paoXGgP83ZLaUi4cMKs60Vv+9p0EQeGv8o2JuiEzJKKWBSJ2vsrfqnLbksohFHECUzwN/QtdBdktr6NQeHpcGNt9YpNNa0XR4j1wb1ntgO2GXXfnSk=", "1; SN6PR07MB4911;\n\t20:v7xM5ra64YBclbSRVoue3mkp20ATtl/iW0L2dgha8rGsh6ZKN6+SPlfdCJewxVRKUkhgdmld3HRI4k9//7y8iDdSlu5sepxLtaHsFhPnHip3Kt00hjUcZQsdtItjAXGFHjdP0tbcS8YqrohkJZYtyF4vt1JYLTFCf3QIt/7unaZoiOsbU31VcpfsVmSrWV9800lCCKoc6D6yAVaEuCiU+RaY0RdpwO2eSsiZvZtD2PxWAdi9wrHeFqLzIim5+VY1w/BAxgIrcAvYas4sWiCKgFXxhg5IVJYNZqAItkNVkfnGDDaMp1yqsG/AECABL0PQf0PiFVxgPE6tchujacwAp5U2i5fPBTJ34NsiFE6CVt7d+dhXqClQp6D/nds00ifdBIlRK0UWMxizs2FhyT4PZPztTue8/jnmAXiVV3HuKUvBN1w18qCMCTXZRa8Ct3LRWnaiV81QF8KABhbjZJj2tTJC94MPj/BBw2+H4rClIz3MEfxDWE5jN3UUuO/Ew/CAnmYtzEOWRv72s9vVixKa9aYjvKR3MfG58O1/P+3tFpe3Eh7+gr9Vir1GN+bDXEH1jlcLZxupuMkfppzuyzXerAXv9964DJsFBwJOaqwsbZY=;\n\t4:IafRr+pQLWZT9yd7v8XohPP/L/ogrSjDiTICLOm47WutDGMCK346G9BxU6Cxob/Y9p/+VlEkZ7E5TKuU4eF1WRSYUhWXP7s5ZS6C5lc0IPZwCizJp8azmYyI0hI2xpXbCop69EEvIf7ZUl1Tpul7iecDmM188epPv7q/B+GKvKrhuo+EFzk/2l0LlNybkZ5TmVspDjB3e2BDu2+p/dsmt0xBn0wDeGXbYWiORKqeoZaPCMncXrwWLV7zQF2KUUPRG2fGX9wzYhim6EMnKKp52A==", "=?us-ascii?Q?1; SN6PR07MB4911;\n\t23:j9w0U1ILnZAlHtW+SA9/SHp7vPGcgEqPzvkjL6v8f?=\n\tIyf/TeelRu++hY+UyBDBkyjhjbuYOEcCtfkKSCM131AP+/HKi+E8Nj+agq7GKJBXng7QFHM8Xv5/ocZ8nmjq/ffs9HXoZ0ctuz7fNzZQ34LSVKZgypCMe0QXONGa9EVtKAhlgf0YC3P2lly9zGmhWBCKS5th7kieqyNVH2lnfEHFm50Ui/IADZ2xz0JjQBG06ihRedo/dROaFIyouznEW+M+UZaYFYmqTeAHR+Qa/QoRKzrvguipbeg/wHA3GJCU+A9TLWZRX+3aeyalX4SpvAy0mLkHE0y4IZpUPr34QCrN5uQraaucrXObFhr2LVm/m+x9IKiZ63KxcNFiGB4LEJitUOCxltGHSg1SSP4xhuXHzlC2/MVgHa2hrKe/7jT2FTwcdP8qd5kTT7jOWQW7WRaKZ9hZmxJUYqMnt5MwOEiyZFLHNpJVieVpuvP4nQfD3Ku+o5WwFXGUGdyJZEBeayMiMppqDyl3kH+wJ5J+nG0An/NTUUKROjjKiQ/LyHv6SenUwZWeucfm+7HyQJieB7/O6QnJd605N6X78yxEuFJZHLqmlFyk+UQBh4G89SsbijhnQy1dbSCVs91pzhH74ud0RQRFJAOMYuC3qGoTBNsafDqUNivmCtq2X+1ihDd6AXVvdh+RoAisbvRPp3OwQmKaXbBhc/BCGUmoifNwnw6noDgAj870OeD9VVfG8aio7Q3060QK20xs8b4SDlptsieoL17P2K8y4LvZRhU2So8zgVafFLkWeVgVS+9tHAr1HW7dMYELarPilOHFIG01YOQgEwAQfEfqRkffqJfb7XcoF+yEvBWLrlQiMz+deMbu/NVqFN0a49AA1+Ojv0CjoyQE5LKn+glOH29d+5UDrTbw8pFsxU/reeJj2rWlzHEfAuJgsnctmQlHtsgMDNg66sZcIYg2XC9RtGmsELVLFrXOCuWEZZBdb69soslgX1yQjBYOthITbb6CUj1qksTyifMUN4lqTjgwmnig0uy4pB9fPounXN6G457BCEfBCgLsz6PxZ0/g1j3HScUiTkhdj/PttnAi3Ll996G5Xx6ihJD5V589xb8cPKfFUbNWT3UmhKU7zOn7HY74aGDqccxZLHi2w+gGLfY53gp2naIVDScExQnSUVyf9IZb5zj8gbV9OIeABCdwVHJzzAc4ySDH2ssBOkbO1C7zF7Tw6Sco3OBD9jf833KSLx0u1WXkbUCWZWmvc0ncKTheUc2hFYK/bbgrxXzTmyvIFvdYXqykQHK3IcKEWnMUWY8Hwv3MGg6aM2iWNQ8ZENNiM7yn6vvjO9x", "1; SN6PR07MB4911;\n\t6:D3cne+GU3smHNPq11AoN5VBJBW899yIg6vxA+/dYG6LGwzERojBpCtsdTIFRbAz4wlQwLxxSQVZXoyMXA/0DoCAO6ZcJUt3ZC3jELoJhFlXadC/GAkcA41t4XcMrAP+84vVN3Mrinb0jQbwFyA+OqczohiUBhE17UjBvmlam5NQ7NlLeGdl4TBUkjkA1JuogDflWDMcPjDClWs45yG9WPu+9gq0gH1O9SvsIoGzlfChe34xBDjMZIHtwJuciYN6jO5264xk2BPK8xb2T0itEz6cUx7GZJMO4JA38Sa1TD79JhyEQkVRw+pwcUY4hgIcAihYQFWBdRID3vs9d6sOT4HFmiKuSqHQ8a1GsaHwK/lVseW/4TiAYyWPIoBJbtsPwXQabb6J4SWIEBDZHjdqc2a+LYfAEVFxRz5iQhmFoXsU6PeQe+AXWpQzJcTKlGuGx/FIFBNkMce1P5g0teEH/1w==;\n\t5:unucM0uPs3jXEA7usVhOfDlGKb6yFe9gGS/CU47e2oPVNTVOgE7opsB8njzWSSuC2YqmS3Ge0HC4uACsriDenBgQ1Lhv2gwYilZe31HhrzOXqKoF0YrWpVS2ldL23gg0SgCrOG0tnqqIn4+Qg6oquhQ1r2leBTPF2RWHa6vctT8=;\n\t24:9UXeydiBE2rLhxx2VCu6cQP2UNiYcsI8R6lSOtP5GLfJEqvY6gJS8lC841sW93Pz8I71G0/uT9flMqx7mDSaAhqXwdahN4QagmRu1Or74UI=", "1; SN6PR07MB4911;\n\t7:zYAgu0saschp1CMHzdvCB3V6qi9yymw+kZlSUXnqfc686jRr7gYvUusMT++7XPx57saD9Rf2HpEuWU1K3y90fnubr7xKjXaXIWK7//sUvuA54Di4yOF5HCIQ1drrAMsUE+HFliL0D4fmisSgaWLrEBb/UfEYspeG18dbJxYm8JfYLySPrSdQwWPydXmjODA/X5rX+Qo8CZVXT4bn30b7PbHXVFoXMwuSGuI6MH5NKl8BdaYq8g2S5aXqqOJbn3mg" ], "X-MS-TrafficTypeDiagnostic": "SN6PR07MB4911:", "X-Microsoft-Antispam-PRVS": "<SN6PR07MB49118D886F7C32B30F8BD8FDF87B0@SN6PR07MB4911.namprd07.prod.outlook.com>", "X-Exchange-Antispam-Report-Test": "UriScan:;", "X-MS-Exchange-SenderADCheck": "1", "X-Exchange-Antispam-Report-CFA-Test": "BCL:0; PCL:0;\n\tRULEID:(8211001083)(6040522)(2401047)(8121501046)(5005006)(10201501046)(93006095)(3002001)(3231254)(944501410)(52105095)(149027)(150027)(6041310)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123560045)(20161123562045)(20161123558120)(20161123564045)(6072148)(201708071742011)(7699016);\n\tSRVR:SN6PR07MB4911; BCL:0; PCL:0; RULEID:; SRVR:SN6PR07MB4911; ", "X-Forefront-PRVS": "06973FFAD3", "X-Forefront-Antispam-Report": "SFV:NSPM;\n\tSFS:(10009020)(376002)(396003)(346002)(39380400002)(366004)(39860400002)(189003)(199004)(26005)(52116002)(956004)(305945005)(8676002)(81156014)(50226002)(8936002)(81166006)(7736002)(68736007)(105586002)(106356001)(3846002)(6116002)(72206003)(478600001)(6486002)(97736004)(6506007)(16586007)(6512007)(53946003)(53936002)(47776003)(486006)(25786009)(5660300001)(50466002)(48376002)(6666003)(4326008)(54906003)(76176011)(36756003)(110136005)(66066001)(8656006)(2906002)(316002)(55236004)(11346002)(16526019)(386003)(186003)(59450400001)(446003)(476003)(42882007)(44832011)(2616005)(51416003);\n\tDIR:OUT; SFP:1101; SCL:1; SRVR:SN6PR07MB4911;\n\tH:ajoseph83.caveonetworks.com.caveonetworks.com; FPR:; SPF:None;\n\tLANG:en; PTR:InfoNoRecords; MX:1; A:1; ", "Received-SPF": "None (protection.outlook.com: cavium.com does not designate\n\tpermitted sender hosts)", "X-Microsoft-Antispam-Message-Info": "H0gJuZmYhTzOQ3qyEyStLThV0oEiS83sXAPGN3HTPTe7qRTNx77yFL6lGO9aILMxBI0BvasHMrqth4rf/0htEetBiBdSTd0kOeTfhzwsomLCoxFjlFZpZKeiQpvJdtUffbjFsT0PTcOMj8ojziz9+1msJcyMnxeE4zoV2FpcykkM2zFWV7IY5PLVxtO3gadZ", "SpamDiagnosticOutput": "1:99", "SpamDiagnosticMetadata": "NSPM", "X-MS-Office365-Filtering-Correlation-Id": "31af13ac-c788-40de-9fa0-08d5cd5fb4c0", "X-OriginatorOrg": "caviumnetworks.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "08 Jun 2018 16:48:44.5568\n\t(UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "31af13ac-c788-40de-9fa0-08d5cd5fb4c0", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "711e4ccf-2e9b-4bcf-a551-4094005b6194", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "SN6PR07MB4911", "Subject": "[dpdk-dev] [PATCH 02/16] crypto/cpt/base: add hardware definitions\n\tCavium CPT", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Nithin Dabilpuram <nithin.dabilpuram@cavium.com>\n\nAdds hardware specific definitions for Cavium CPT device.\n\nSigned-off-by: Ankur Dwivedi <ankur.dwivedi@cavium.com>\nSigned-off-by: Murthy NSSR <Nidadavolu.Murthy@cavium.com>\nSigned-off-by: Nithin Dabilpuram <nithin.dabilpuram@cavium.com>\nSigned-off-by: Ragothaman Jayaraman <Ragothaman.Jayaraman@cavium.com>\nSigned-off-by: Srisivasubramanian Srinivasan <Srisivasubramanian.Srinivasan@cavium.com>\n---\n drivers/crypto/cpt/base/cpt_hw_types.h | 836 ++++++++++++++++++++++++++++++++\n drivers/crypto/cpt/base/mcode_defines.h | 215 ++++++++\n 2 files changed, 1051 insertions(+)\n create mode 100644 drivers/crypto/cpt/base/cpt_hw_types.h\n create mode 100644 drivers/crypto/cpt/base/mcode_defines.h", "diff": "diff --git a/drivers/crypto/cpt/base/cpt_hw_types.h b/drivers/crypto/cpt/base/cpt_hw_types.h\nnew file mode 100644\nindex 0000000..b4b2af1\n--- /dev/null\n+++ b/drivers/crypto/cpt/base/cpt_hw_types.h\n@@ -0,0 +1,836 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2017 Cavium, Inc\n+ */\n+\n+#ifndef __CPT_HW_TYPES_H\n+#define __CPT_HW_TYPES_H\n+\n+#include <stddef.h>\n+#include <stdint.h>\n+#include <stdbool.h>\n+#include <errno.h>\n+#include <string.h>\n+\n+#define CPT_INST_SIZE\t (64)\n+#define CPT_VQ_CHUNK_ALIGN\t (128) /**< 128 byte align */\n+#define CPT_NEXT_CHUNK_PTR_SIZE (8)\n+#define CPT_INST_CHUNK_MAX_SIZE (1023)\n+\n+#define CPT_PF_VF_MAILBOX_SIZE\t\t(2)\n+\n+#define CPT_VF_INTR_MBOX_MASK (1<<0)\n+#define CPT_VF_INTR_DOVF_MASK (1<<1)\n+#define CPT_VF_INTR_IRDE_MASK (1<<2)\n+#define CPT_VF_INTR_NWRP_MASK (1<<3)\n+#define CPT_VF_INTR_SWERR_MASK (1<<4)\n+#define CPT_VF_INTR_HWERR_MASK (1<<5)\n+#define CPT_VF_INTR_FAULT_MASK (1<<6)\n+\n+/*\n+ * CPT_INST_S software command definitions\n+ * Words EI (0-3)\n+ */\n+typedef union {\n+\tuint64_t u64;\n+\tstruct {\n+\t\tuint16_t opcode;\n+\t\tuint16_t param1;\n+\t\tuint16_t param2;\n+\t\tuint16_t dlen;\n+\t} s;\n+} vq_cmd_word0_t;\n+\n+typedef union {\n+\tuint64_t u64;\n+\tstruct {\n+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__\n+\t\tuint64_t grp\t: 3;\n+\t\tuint64_t cptr\t: 61;\n+#else\n+\t\tuint64_t cptr\t: 61;\n+\t\tuint64_t grp\t: 3;\n+#endif\n+\t} s;\n+} vq_cmd_word3_t;\n+\n+typedef struct cpt_vq_command {\n+\tvq_cmd_word0_t cmd;\n+\tuint64_t dptr;\n+\tuint64_t rptr;\n+\tvq_cmd_word3_t cptr;\n+} cpt_vq_cmd_t;\n+\n+/**\n+ * Structure cpt_inst_s\n+ *\n+ * CPT Instruction Structure\n+ * This structure specifies the instruction layout.\n+ * Instructions are stored in memory\n+ * as little-endian unless CPT()_PF_Q()_CTL[INST_BE] is set.\n+ */\n+typedef union cpt_inst_s {\n+\tuint64_t u[8];\n+\tstruct cpt_inst_s_s {\n+#if (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__) /* Word 0 - Big Endian */\n+\t\tuint64_t reserved_17_63 : 47;\n+\t\tuint64_t doneint : 1;\n+\t\t/*< [ 16: 16] Done interrupt.\n+\t\t * 0 = No interrupts related to this instruction.\n+\t\t * 1 = When the instruction completes,CPT()_VQ()_DONE[DONE]\n+\t\t * will be incremented, and based on the rules described\n+\t\t * there an interrupt may occur.\n+\t\t */\n+\t\tuint64_t reserved_0_15 : 16;\n+#else /* Word 0 - Little Endian */\n+\t\tuint64_t reserved_0_15 : 16;\n+\t\tuint64_t doneint : 1;\n+\t\t/*< [ 16: 16] Done interrupt.\n+\t\t * 0 = No interrupts related to this instruction.\n+\t\t * 1 = When the instruction completes,CPT()_VQ()_DONE[DONE]\n+\t\t * will be incremented, and based on the rules described\n+\t\t * there aninterrupt may occur.\n+\t\t */\n+\t\tuint64_t reserved_17_63 : 47;\n+#endif /* Word 0 - End */\n+#if (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__) /* Word 1 - Big Endian */\n+\t\tuint64_t res_addr : 64;\n+\t\t/*< [127: 64] Result IOVA.\n+\t\t * If nonzero, specifies where to write CPT_RES_S.\n+\t\t * If zero, no result structure will be written.\n+\t\t * Address must be 16-byte aligned.\n+\n+\t\t * Bits <63:49> are ignored by hardware; software should\n+\t\t *use a sign-extended bit <48> for forward compatibility.\n+\t\t */\n+#else /* Word 1 - Little Endian */\n+\t\tuint64_t res_addr : 64;\n+\t\t/*< [127: 64] Result IOVA.\n+\t\t * If nonzero, specifies where to write CPT_RES_S.\n+\t\t * If zero, no result structure will be written.\n+\t\t * Address must be 16-byte aligned.\n+\n+\t\t * Bits <63:49> are ignored by hardware; software should\n+\t\t *use a sign-extended bit <48> for forward compatibility.\n+\t\t */\n+#endif /* Word 1 - End */\n+#if (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__) /* Word 2 - Big Endian */\n+\t\tuint64_t reserved_172_191 : 20;\n+\t\tuint64_t grp : 10;\n+\t\t/*< [171:162] If [WQ_PTR] is nonzero, the SSO guest-group to\n+\t\t * use when CPT submits work to SSO.\n+\t\t * For the SSO to not discard the add-work request, FPA_PF_MAP()\n+\t\t * must map [GRP] and CPT()_PF_Q()_GMCTL[GMID] as valid.\n+\t\t */\n+\t\tuint64_t tt : 2;\n+\t\t/*< [161:160] If [WQ_PTR] is nonzero, the SSO tag type to use\n+\t\t * when CPT submits work to SSO.\n+\t\t */\n+\t\tuint64_t tag : 32;\n+\t\t/*< [159:128] If [WQ_PTR] is nonzero, the SSO tag to use when\n+\t\t * CPT submits work to SSO.\n+\t\t */\n+#else /* Word 2 - Little Endian */\n+\t\tuint64_t tag : 32;\n+\t\t/**< [159:128] If [WQ_PTR] is nonzero, the SSO tag to use when\n+\t\t * CPT submits work to SSO.\n+\t\t */\n+\t\tuint64_t tt : 2;\n+\t\t/**< [161:160] If [WQ_PTR] is nonzero, the SSO tag type to use\n+\t\t * when CPT submits work to SSO.\n+\t\t */\n+\t\tuint64_t grp : 10;\n+\t\t/**< [171:162] If [WQ_PTR] is nonzero, the SSO guest-group to\n+\t\t * use when CPT submits work to SSO.\n+\t\t * For the SSO to not discard the add-work request, FPA_PF_MAP()\n+\t\t * must map [GRP] and CPT()_PF_Q()_GMCTL[GMID] as valid.\n+\t\t **/\n+\t\tuint64_t reserved_172_191 : 20;\n+#endif /* Word 2 - End */\n+#if (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__) /* Word 3 - Big Endian */\n+\t\tuint64_t wq_ptr : 64;\n+\t\t/**< [255:192] If [WQ_PTR] is nonzero, it is a pointer to a\n+\t\t * work-queue entry that CPT submits work to SSO after all\n+\t\t * context, output data, and result write operations are\n+\t\t * visible to other CNXXXX units and the cores.\n+\t\t * Bits <2:0> must be zero.\n+\t\t * Bits <63:49> are ignored by hardware; software should use a\n+\t\t * sign-extended bit <48> for forward compatibility.\n+\t\t * Internal:Bits <63:49>, <2:0> are ignored by hardware,\n+\t\t * treated as always 0x0.\n+\t\t **/\n+#else /* Word 3 - Little Endian */\n+\t\tuint64_t wq_ptr : 64;\n+\t\t/**< [255:192] If [WQ_PTR] is nonzero, it is a pointer to a\n+\t\t * work-queue entry that CPT submits work to SSO after all\n+\t\t * context, output data, and result write operations are\n+\t\t * visible to other CNXXXX units and the cores.\n+\t\t * Bits <2:0> must be zero.\n+\t\t * Bits <63:49> are ignored by hardware; software should use a\n+\t\t * sign-extended bit <48> for forward compatibility.\n+\t\t * Internal: Bits <63:49>, <2:0> are ignored by hardware,\n+\t\t * treated as always 0x0.\n+\t\t **/\n+#endif /* Word 3 - End */\n+#if (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__) /* Word 4 - Big Endian */\n+\t\tunion {\n+\t\t\tuint64_t ei0 : 64;\n+\t\t\t/**< [319:256] Engine instruction word 0. Passed to the\n+\t\t\t * AE/SE.\n+\t\t\t **/\n+\t\t\tvq_cmd_word0_t vq_cmd_w0;\n+\t\t};\n+#else /* Word 4 - Little Endian */\n+\t\tunion {\n+\t\t\tuint64_t ei0 : 64;\n+\t\t\t/**< [319:256] Engine instruction word 0. Passed to the\n+\t\t\t * AE/SE.\n+\t\t\t **/\n+\t\t\tvq_cmd_word0_t vq_cmd_w0;\n+\t\t};\n+#endif /* Word 4 - End */\n+#if (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__) /* Word 5 - Big Endian */\n+\t\tunion {\n+\t\t\tuint64_t ei1 : 64;\n+\t\t\t/**< [383:320] Engine instruction word 1. Passed to the\n+\t\t\t * AE/SE.\n+\t\t\t **/\n+\t\t\tuint64_t dptr;\n+\t\t};\n+#else /* Word 5 - Little Endian */\n+\t\tunion {\n+\t\t\tuint64_t ei1 : 64;\n+\t\t\t/**< [383:320] Engine instruction word 1. Passed to the\n+\t\t\t * AE/SE.\n+\t\t\t **/\n+\t\t\tuint64_t dptr;\n+\t\t};\n+#endif /* Word 5 - End */\n+#if (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__) /* Word 6 - Big Endian */\n+\t\tunion {\n+\t\t\tuint64_t ei2 : 64;\n+\t\t\t/**< [447:384] Engine instruction word 2. Passed to the\n+\t\t\t * AE/SE.\n+\t\t\t **/\n+\t\t\tuint64_t rptr;\n+\t\t};\n+#else /* Word 6 - Little Endian */\n+\t\tunion {\n+\t\t\tuint64_t ei2 : 64;\n+\t\t\t/**< [447:384] Engine instruction word 2. Passed to the\n+\t\t\t * AE/SE.\n+\t\t\t **/\n+\t\t\tuint64_t rptr;\n+\t\t};\n+#endif /* Word 6 - End */\n+#if (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__) /* Word 7 - Big Endian */\n+\t\tunion {\n+\t\t\tuint64_t ei3 : 64;\n+\t\t\t/**< [511:448] Engine instruction word 3. Passed to the\n+\t\t\t * AE/SE.\n+\t\t\t **/\n+\t\t\tvq_cmd_word3_t vq_cmd_w3;\n+\t\t};\n+#else /* Word 7 - Little Endian */\n+\t\tunion {\n+\t\t\tuint64_t ei3 : 64;\n+\t\t\t/**< [511:448] Engine instruction word 3. Passed to the\n+\t\t\t * AE/SE.\n+\t\t\t **/\n+\t\t\tvq_cmd_word3_t vq_cmd_w3;\n+\t\t};\n+#endif /* Word 7 - End */\n+\t} s;\n+\tstruct cpt_inst_s_cn {\n+#if (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__) /* Word 0 - Big Endian */\n+\t\tuint64_t reserved_17_63 : 47;\n+\t\tuint64_t doneint : 1;\n+\t\t/**< [ 16: 16] Done interrupt.\n+\t\t * 0 = No interrupts related to this instruction.\n+\t\t * 1 = When the instruction completes, CPT()_VQ()_DONE[DONE]\n+\t\t * will be incremented,and based on the rules described there\n+\t\t * an interrupt may occur.\n+\t\t **/\n+\t\tuint64_t reserved_8_15 : 8;\n+\t\tuint64_t reserved_0_7 : 8;\n+#else /* Word 0 - Little Endian */\n+\t\tuint64_t reserved_0_7 : 8;\n+\t\tuint64_t reserved_8_15 : 8;\n+\t\tuint64_t doneint : 1;\n+\t\t/**< [ 16: 16] Done interrupt.\n+\t\t * 0 = No interrupts related to this instruction.\n+\t\t * 1 = When the instruction completes, CPT()_VQ()_DONE[DONE]\n+\t\t * will be incremented,and based on the rules described there\n+\t\t * an interrupt may occur.\n+\t\t **/\n+\t\tuint64_t reserved_17_63 : 47;\n+#endif /* Word 0 - End */\n+#if (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__) /* Word 1 - Big Endian */\n+\t\tuint64_t res_addr : 64;\n+\t\t/**< [127: 64] Result IOVA.\n+\t\t * If nonzero, specifies where to write CPT_RES_S.\n+\t\t * If zero, no result structure will be written.\n+\t\t * Address must be 16-byte aligned.\n+\t\t *\n+\t\t * Bits <63:49> are ignored by hardware; software should\n+\t\t * use a sign-extended bit <48> for forward compatibility.\n+\t\t **/\n+#else /* Word 1 - Little Endian */\n+\t\tuint64_t res_addr : 64;\n+\t\t/**< [127: 64] Result IOVA.\n+\t\t * If nonzero, specifies where to write CPT_RES_S.\n+\t\t * If zero, no result structure will be written.\n+\t\t * Address must be 16-byte aligned.\n+\t\t *\n+\t\t * Bits <63:49> are ignored by hardware; software should\n+\t\t * use a sign-extended bit <48> for forward compatibility.\n+\t\t **/\n+#endif /* Word 1 - End */\n+#if (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__) /* Word 2 - Big Endian */\n+\t\tuint64_t reserved_172_191 : 20;\n+\t\tuint64_t grp : 10;\n+\t\t/**< [171:162] If [WQ_PTR] is nonzero, the SSO guest-group to\n+\t\t * use when CPT submits work to SSO. For the SSO to not discard\n+\t\t * the add-work request, FPA_PF_MAP() must map [GRP] and\n+\t\t * CPT()_PF_Q()_GMCTL[GMID] as valid.\n+\t\t **/\n+\t\tuint64_t tt : 2;\n+\t\t/**< [161:160] If [WQ_PTR] is nonzero, the SSO tag type to use\n+\t\t * when CPT submits work to SSO.\n+\t\t **/\n+\t\tuint64_t tag : 32;\n+\t\t/**< [159:128] If [WQ_PTR] is nonzero, the SSO tag to use\n+\t\t * when CPT submits work to SSO.\n+\t\t **/\n+#else /* Word 2 - Little Endian */\n+\t\tuint64_t tag : 32;\n+\t\t/**< [159:128] If [WQ_PTR] is nonzero, the SSO tag to use\n+\t\t * when CPT submits work to SSO.\n+\t\t **/\n+\t\tuint64_t tt : 2;\n+\t\t/**< [161:160] If [WQ_PTR] is nonzero, the SSO tag type to use\n+\t\t * when CPT submits work to SSO.\n+\t\t **/\n+\t\tuint64_t grp : 10;\n+\t\t/**< [171:162] If [WQ_PTR] is nonzero, the SSO guest-group to\n+\t\t * use when CPT submits work to SSO. For the SSO to not discard\n+\t\t * the add-work request, FPA_PF_MAP() must map [GRP] and\n+\t\t * CPT()_PF_Q()_GMCTL[GMID] as valid.\n+\t\t **/\n+\t\tuint64_t reserved_172_191 : 20;\n+#endif /* Word 2 - End */\n+#if (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__) /* Word 3 - Big Endian */\n+\t\tuint64_t wq_ptr : 64;\n+\t\t/**< [255:192] If [WQ_PTR] is nonzero, it is a pointer to a work\n+\t\t * -queue entry that CPT submits work to SSO after all context,\n+\t\t * output data, and result write operations are visible to other\n+\t\t * CNXXXX units and the cores.\n+\n+\t\tBits <2:0> must be zero. Bits <63:49> are ignored by hardware;\n+\t\tsoftware should use a sign-extended bit <48> for forward\n+\t\tcompatibility.\n+\n+Internal:\n+Bits <63:49>, <2:0> are ignored by hardware, treated as always 0x0.\n+\t\t */\n+#else /* Word 3 - Little Endian */\n+\t\tuint64_t wq_ptr : 64;\n+\t\t/**< [255:192] If [WQ_PTR] is nonzero, it is a pointer to a work\n+\t\t * -queue entry that CPT submits work to SSO after all context,\n+\t\t * output data, and result write operations are visible to other\n+\t\t * CNXXXX units and the cores.\n+\n+\t\tBits <2:0> must be zero. Bits <63:49> are ignored by hardware;\n+\t\tsoftware should use a sign-extended bit <48> for forward\n+\t\tcompatibility.\n+\n+Internal:\n+Bits <63:49>, <2:0> are ignored by hardware, treated as always 0x0.\n+\t\t */\n+#endif /* Word 3 - End */\n+#if (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__) /* Word 4 - Big Endian */\n+\t\tuint64_t ei0 : 64;\n+\t\t/**< [319:256] Engine instruction word 0. Passed to the AE/SE.*/\n+#else /* Word 4 - Little Endian */\n+\t\tuint64_t ei0 : 64;\n+\t\t/**< [319:256] Engine instruction word 0. Passed to the AE/SE.*/\n+#endif /* Word 4 - End */\n+#if (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__) /* Word 5 - Big Endian */\n+\t\tuint64_t ei1 : 64;\n+\t\t/**< [383:320] Engine instruction word 1. Passed to the AE/SE.*/\n+#else /* Word 5 - Little Endian */\n+\t\tuint64_t ei1 : 64;\n+\t\t/**< [383:320] Engine instruction word 1. Passed to the AE/SE.*/\n+#endif /* Word 5 - End */\n+#if (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__) /* Word 6 - Big Endian */\n+\t\tuint64_t ei2 : 64;\n+\t\t/**< [447:384] Engine instruction word 2. Passed to the AE/SE.*/\n+#else /* Word 6 - Little Endian */\n+\t\tuint64_t ei2 : 64;\n+\t\t/**< [447:384] Engine instruction word 2. Passed to the AE/SE.*/\n+#endif /* Word 6 - End */\n+#if (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__) /* Word 7 - Big Endian */\n+\t\tuint64_t ei3 : 64;\n+\t\t/**< [511:448] Engine instruction word 3. Passed to the AE/SE.*/\n+#else /* Word 7 - Little Endian */\n+\t\tuint64_t ei3 : 64;\n+\t\t/**< [511:448] Engine instruction word 3. Passed to the AE/SE.*/\n+#endif /* Word 7 - End */\n+\t} cn;\n+} cpt_inst_s_t;\n+\n+/**\n+ * Structure cpt_res_s\n+ *\n+ * CPT Result Structure\n+ * The CPT coprocessor writes the result structure after it completes a\n+ * CPT_INST_S instruction. The result structure is exactly 16 bytes, and each\n+ * instruction completion produces exactly one result structure.\n+ *\n+ * This structure is stored in memory as little-endian unless\n+ * CPT()_PF_Q()_CTL[INST_BE] is set.\n+ */\n+typedef union cpt_res_s {\n+\tuint64_t u[2];\n+\tstruct cpt_res_s_s {\n+#if (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__) /* Word 0 - Big Endian */\n+\t\tuint64_t reserved_17_63 : 47;\n+\t\tuint64_t doneint : 1;\n+\t\t/**< [ 16: 16] Done interrupt. This bit is copied from the\n+\t\t * corresponding instruction's CPT_INST_S[DONEINT].\n+\t\t **/\n+\t\tuint64_t reserved_8_15 : 8;\n+\t\tuint64_t compcode : 8;\n+\t\t/**< [ 7: 0] Indicates completion/error status of the CPT\n+\t\t * coprocessor for the associated instruction, as enumerated by\n+\t\t * CPT_COMP_E. Core software may write the memory location\n+\t\t * containing [COMPCODE] to 0x0 before ringing the doorbell, and\n+\t\t * then poll for completion by checking for a nonzero value.\n+\n+\t\t Once the core observes a nonzero [COMPCODE] value in this case,\n+\t\t the CPT coprocessor will have also completed L2/DRAM write\n+\t\t operations.\n+\t\t */\n+#else /* Word 0 - Little Endian */\n+\t\tuint64_t compcode : 8;\n+\t\t/**< [ 7: 0] Indicates completion/error status of the CPT\n+\t\t * coprocessor for the associated instruction, as enumerated by\n+\t\t * CPT_COMP_E. Core software may write the memory location\n+\t\t * containing [COMPCODE] to 0x0 before ringing the doorbell, and\n+\t\t * then poll for completion by checking for a nonzero value.\n+\n+\t\tOnce the core observes a nonzero [COMPCODE] value in this case,\n+\t\tthe CPT coprocessor will have also completed L2/DRAM write\n+\t\toperations.\n+\t\t */\n+\t\tuint64_t reserved_8_15 : 8;\n+\t\tuint64_t doneint : 1;\n+\t\t/**< [ 16: 16] Done interrupt. This bit is copied from the\n+\t\t * corresponding instruction's CPT_INST_S[DONEINT].\n+\t\t **/\n+\t\tuint64_t reserved_17_63 : 47;\n+#endif /* Word 0 - End */\n+#if (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__) /* Word 1 - Big Endian */\n+\t\tuint64_t reserved_64_127 : 64;\n+#else /* Word 1 - Little Endian */\n+\t\tuint64_t reserved_64_127 : 64;\n+#endif /* Word 1 - End */\n+\t} s;\n+\t/* struct cpt_res_s_s cn; */\n+} cpt_res_s_t;\n+\n+/**\n+ * Register (NCB) cpt#_vq#_ctl\n+ *\n+ * CPT VF Queue Control Registers\n+ * This register configures queues. This register should be changed (other than\n+ * clearing [ENA]) only when quiescent (see CPT()_VQ()_INPROG[INFLIGHT]).\n+ */\n+typedef union {\n+\tuint64_t u;\n+\tstruct cptx_vqx_ctl_s {\n+#if (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__) /* Word 0 - Big Endian */\n+\t\tuint64_t reserved_1_63 : 63;\n+\t\tuint64_t ena : 1;\n+\t\t/**< [ 0: 0](R/W/H) Enables the logical instruction queue.\n+\t\t * See also CPT()_PF_Q()_CTL[CONT_ERR] and\n+\t\t * CPT()_VQ()_INPROG[INFLIGHT].\n+\t\t * 1 = Queue is enabled.\n+\t\t * 0 = Queue is disabled.\n+\t\t **/\n+#else /* Word 0 - Little Endian */\n+\t\tuint64_t ena : 1;\n+\t\t/**< [ 0: 0](R/W/H) Enables the logical instruction queue.\n+\t\t * See also CPT()_PF_Q()_CTL[CONT_ERR] and\n+\t\t * CPT()_VQ()_INPROG[INFLIGHT].\n+\t\t * 1 = Queue is enabled.\n+\t\t * 0 = Queue is disabled.\n+\t\t **/\n+\t\tuint64_t reserved_1_63 : 63;\n+#endif /* Word 0 - End */\n+\t} s;\n+\t/* struct cptx_vqx_ctl_s cn; */\n+} cptx_vqx_ctl_t;\n+\n+/**\n+ * Register (NCB) cpt#_vq#_done\n+ *\n+ * CPT Queue Done Count Registers\n+ * These registers contain the per-queue instruction done count.\n+ */\n+typedef union {\n+\tuint64_t u;\n+\tstruct cptx_vqx_done_s {\n+#if (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__) /* Word 0 - Big Endian */\n+\t\tuint64_t reserved_20_63 : 44;\n+\t\tuint64_t done : 20;\n+\t\t/**< [ 19: 0](R/W/H) Done count. When CPT_INST_S[DONEINT] set\n+\t\t * and that instruction completes,CPT()_VQ()_DONE[DONE] is\n+\t\t * incremented when the instruction finishes. Write to this\n+\t\t * field are for diagnostic use only; instead software writes\n+\t\t * CPT()_VQ()_DONE_ACK with the number of decrements for this\n+\t\t * field.\n+\n+\t\tInterrupts are sent as follows:\n+\n+\t\t * When CPT()_VQ()_DONE[DONE] = 0, then no results are pending,\n+\t\t * the interrupt coalescing timer is held to zero, and an\n+\t\t * interrupt is not sent.\n+\n+\t\t * When CPT()_VQ()_DONE[DONE] != 0, then the interrupt\n+\t\t * coalescing timer counts. If the counter is >= CPT()_VQ()_DONE\n+\t\t * _WAIT[TIME_WAIT]*1024, or CPT()_VQ()_DONE[DONE] >= CPT()_VQ()\n+\t\t * _DONE_WAIT[NUM_WAIT], i.e. enough time has passed or enough\n+\t\t * results have arrived, then the interrupt is sent. Otherwise,\n+\t\t * it is not sent due to coalescing.\n+\n+\t\t* When CPT()_VQ()_DONE_ACK is written (or CPT()_VQ()_DONE is\n+\t\t* written but this is not typical), the interrupt coalescing\n+\t\t* timer restarts. Note after decrementing this interrupt\n+\t\t* equation is recomputed, for example if CPT()_VQ()_DONE[DONE]\n+\t\t* >= CPT()_VQ()_DONE_WAIT[NUM_WAIT] and because the timer is\n+\t\t* zero, the interrupt will be resent immediately. (This covers\n+\t\t* the race case between software acknowledging an interrupt and\n+\t\t* a result returning.)\n+\n+\t\t* When CPT()_VQ()_DONE_ENA_W1S[DONE] = 0, interrupts are not\n+\t\t* sent, but the counting described above still occurs.\n+\n+\t\tSince CPT instructions complete out-of-order, if software is\n+\t\tusing completion interrupts the suggested scheme is to request a\n+\t\tDONEINT on each request, and when an interrupt arrives perform a\n+\t\t\"greedy\" scan for completions; even if a later command is\n+\t\tacknowledged first this will not result in missing a completion.\n+\n+\t\tSoftware is responsible for making sure [DONE] does not overflow\n+\t\t; for example by insuring there are not more than 2^20-1\n+\t\tinstructions in flight that may request interrupts.\n+\t\t */\n+#else /* Word 0 - Little Endian */\n+\t\tuint64_t done : 20;\n+\t\t/**< [ 19: 0](R/W/H) Done count. When CPT_INST_S[DONEINT] set\n+\t\t * and that instruction completes,CPT()_VQ()_DONE[DONE] is\n+\t\t * incremented when the instruction finishes. Write to this\n+\t\t * field are for diagnostic use only; instead software writes\n+\t\t * CPT()_VQ()_DONE_ACK with the number of decrements for this\n+\t\t * field.\n+\n+\t\tInterrupts are sent as follows:\n+\n+\t\t * When CPT()_VQ()_DONE[DONE] = 0, then no results are pending,\n+\t\t * the interrupt coalescing timer is held to zero, and an\n+\t\t * interrupt is not sent.\n+\n+\t\t * When CPT()_VQ()_DONE[DONE] != 0, then the interrupt\n+\t\t * coalescing timer counts. If the counter is >= CPT()_VQ()_DONE\n+\t\t * _WAIT[TIME_WAIT]*1024, or CPT()_VQ()_DONE[DONE] >= CPT()_VQ()\n+\t\t * _DONE_WAIT[NUM_WAIT], i.e. enough time has passed or enough\n+\t\t * results have arrived, then the interrupt is sent. Otherwise,\n+\t\t * it is not sent due to coalescing.\n+\n+\t\t* When CPT()_VQ()_DONE_ACK is written (or CPT()_VQ()_DONE is\n+\t\t* written but this is not typical), the interrupt coalescing\n+\t\t* timer restarts. Note after decrementing this interrupt\n+\t\t* equation is recomputed, for example if CPT()_VQ()_DONE[DONE]\n+\t\t* >= CPT()_VQ()_DONE_WAIT[NUM_WAIT] and because the timer is\n+\t\t* zero, the interrupt will be resent immediately. (This covers\n+\t\t* the race case between software acknowledging an interrupt and\n+\t\t* a result returning.)\n+\n+\t\t* When CPT()_VQ()_DONE_ENA_W1S[DONE] = 0, interrupts are not\n+\t\t* sent, but the counting described above still occurs.\n+\n+\t\tSince CPT instructions complete out-of-order, if software is\n+\t\tusing completion interrupts the suggested scheme is to request a\n+\t\tDONEINT on each request, and when an interrupt arrives perform a\n+\t\t\"greedy\" scan for completions; even if a later command is\n+\t\tacknowledged first this will not result in missing a completion.\n+\n+\t\tSoftware is responsible for making sure [DONE] does not overflow\n+\t\t; for example by insuring there are not more than 2^20-1\n+\t\tinstructions in flight that may request interrupts.\n+\t\t */\n+\t\tuint64_t reserved_20_63 : 44;\n+#endif /* Word 0 - End */\n+\t} s;\n+\t/* struct cptx_vqx_done_s cn; */\n+} cptx_vqx_done_t;\n+\n+/**\n+ * Register (NCB) cpt#_vq#_done_ack\n+ *\n+ * CPT Queue Done Count Ack Registers\n+ * This register is written by software to acknowledge interrupts.\n+ */\n+typedef union {\n+\tuint64_t u;\n+\tstruct cptx_vqx_done_ack_s {\n+#if (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__) /* Word 0 - Big Endian */\n+\t\tuint64_t reserved_20_63 : 44;\n+\t\tuint64_t done_ack : 20;\n+\t\t/**< [ 19: 0](R/W/H) Number of decrements to CPT()_VQ()_DONE\n+\t\t * [DONE]. Reads CPT()_VQ()_DONE[DONE].\n+\n+\t\tWritten by software to acknowledge interrupts. If CPT()_VQ()_\n+\t\tDONE[DONE] is still nonzero the interrupt will be re-sent if the\n+\t\tconditions described in CPT()_VQ()_DONE[DONE] are satisfied.\n+\t\t */\n+#else /* Word 0 - Little Endian */\n+\t\tuint64_t done_ack : 20;\n+\t\t/**< [ 19: 0](R/W/H) Number of decrements to CPT()_VQ()_DONE\n+\t\t * [DONE]. Reads CPT()_VQ()_DONE[DONE].\n+\n+\t\tWritten by software to acknowledge interrupts. If CPT()_VQ()_\n+\t\tDONE[DONE] is still nonzero the interrupt will be re-sent if the\n+\t\tconditions described in CPT()_VQ()_DONE[DONE] are satisfied.\n+\t\t */\n+\t\tuint64_t reserved_20_63 : 44;\n+#endif /* Word 0 - End */\n+\t} s;\n+\t/* struct cptx_vqx_done_ack_s cn; */\n+} cptx_vqx_done_ack_t;\n+\n+/**\n+ * Register (NCB) cpt#_vq#_done_wait\n+ *\n+ * CPT Queue Done Interrupt Coalescing Wait Registers\n+ * Specifies the per queue interrupt coalescing settings.\n+ */\n+typedef union {\n+\tuint64_t u;\n+\tstruct cptx_vqx_done_wait_s {\n+#if (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__) /* Word 0 - Big Endian */\n+\t\tuint64_t reserved_48_63 : 16;\n+\t\tuint64_t time_wait : 16;\n+\t\t/**< [ 47: 32](R/W) Time hold-off. When CPT()_VQ()_DONE[DONE] =\n+\t\t * 0, or CPT()_VQ()_DONE_ACK is written a timer is cleared. When\n+\t\t * the timer reaches [TIME_WAIT]*1024 then interrupt coalescing\n+\t\t * ends; see CPT()_VQ()_DONE[DONE]. If 0x0, time coalescing is\n+\t\t * disabled.\n+\t\t **/\n+\t\tuint64_t reserved_20_31 : 12;\n+\t\tuint64_t num_wait : 20;\n+\t\t/**< [ 19: 0](R/W) Number of messages hold-off. When\n+\t\t * CPT()_VQ()_DONE[DONE] >= [NUM_WAIT] then interrupt coalescing\n+\t\t * ends; see CPT()_VQ()_DONE[DONE]. If 0x0, same behavior as\n+\t\t * 0x1.\n+\t\t **/\n+#else /* Word 0 - Little Endian */\n+\t\tuint64_t num_wait : 20;\n+\t\t/**< [ 19: 0](R/W) Number of messages hold-off. When\n+\t\t * CPT()_VQ()_DONE[DONE] >= [NUM_WAIT] then interrupt coalescing\n+\t\t * ends; see CPT()_VQ()_DONE[DONE]. If 0x0, same behavior as\n+\t\t * 0x1.\n+\t\t **/\n+\t\tuint64_t reserved_20_31 : 12;\n+\t\tuint64_t time_wait : 16;\n+\t\t/**< [ 47: 32](R/W) Time hold-off. When CPT()_VQ()_DONE[DONE] =\n+\t\t * 0, or CPT()_VQ()_DONE_ACK is written a timer is cleared. When\n+\t\t * the timer reaches [TIME_WAIT]*1024 then interrupt coalescing\n+\t\t * ends; see CPT()_VQ()_DONE[DONE]. If 0x0, time coalescing is\n+\t\t * disabled.\n+\t\t **/\n+\t\tuint64_t reserved_48_63 : 16;\n+#endif /* Word 0 - End */\n+\t} s;\n+\t/* struct cptx_vqx_done_wait_s cn; */\n+} cptx_vqx_done_wait_t;\n+\n+/**\n+ * Register (NCB) cpt#_vq#_doorbell\n+ *\n+ * CPT Queue Doorbell Registers\n+ * Doorbells for the CPT instruction queues.\n+ */\n+typedef union {\n+\tuint64_t u;\n+\tstruct cptx_vqx_doorbell_s {\n+#if (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__) /* Word 0 - Big Endian */\n+\t\tuint64_t reserved_20_63 : 44;\n+\t\tuint64_t dbell_cnt : 20;\n+\t\t/**< [ 19: 0](R/W/H) Number of instruction queue 64-bit words\n+\t\t * to add to the CPT instruction doorbell count. Readback value\n+\t\t * is the the current number of pending doorbell requests.\n+\n+\t\tIf counter overflows CPT()_VQ()_MISC_INT[DBELL_DOVF] is set.\n+\n+\t\tTo reset the count back to zero, write one to clear\n+\t\tCPT()_VQ()_MISC_INT_ENA_W1C[DBELL_DOVF], then write a value of\n+\t\t2^20 minus the read [DBELL_CNT], then write one to\n+\t\tCPT()_VQ()_MISC_INT_W1C[DBELL_DOVF] and\n+\t\tCPT()_VQ()_MISC_INT_ENA_W1S[DBELL_DOVF].\n+\n+\t\tMust be a multiple of 8. All CPT instructions are 8 words and\n+\t\trequire a doorbell count of multiple of 8.\n+\t\t */\n+#else /* Word 0 - Little Endian */\n+\t\tuint64_t dbell_cnt : 20;\n+\t\t/**< [ 19: 0](R/W/H) Number of instruction queue 64-bit words\n+\t\t * to add to the CPT instruction doorbell count. Readback value\n+\t\t * is the the current number of pending doorbell requests.\n+\n+\t\tIf counter overflows CPT()_VQ()_MISC_INT[DBELL_DOVF] is set.\n+\n+\t\tTo reset the count back to zero, write one to clear\n+\t\tCPT()_VQ()_MISC_INT_ENA_W1C[DBELL_DOVF], then write a value of\n+\t\t2^20 minus the read [DBELL_CNT], then write one to\n+\t\tCPT()_VQ()_MISC_INT_W1C[DBELL_DOVF] and\n+\t\tCPT()_VQ()_MISC_INT_ENA_W1S[DBELL_DOVF].\n+\n+\t\tMust be a multiple of 8. All CPT instructions are 8 words and\n+\t\trequire a doorbell count of multiple of 8.\n+\t\t */\n+\t\tuint64_t reserved_20_63 : 44;\n+#endif /* Word 0 - End */\n+\t} s;\n+\t/* struct cptx_vqx_doorbell_s cn; */\n+} cptx_vqx_doorbell_t;\n+\n+/**\n+ * Register (NCB) cpt#_vq#_inprog\n+ *\n+ * CPT Queue In Progress Count Registers\n+ * These registers contain the per-queue instruction in flight registers.\n+ */\n+typedef union {\n+\tuint64_t u;\n+\tstruct cptx_vqx_inprog_s {\n+#if (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__) /* Word 0 - Big Endian */\n+\t\tuint64_t reserved_8_63 : 56;\n+\t\tuint64_t inflight : 8;\n+\t\t/**< [ 7: 0](RO/H) Inflight count. Counts the number of\n+\t\t * instructions for the VF for which CPT is fetching, executing\n+\t\t * or responding to instructions. However this does not include\n+\t\t * any interrupts that are awaiting software handling\n+\t\t * (CPT()_VQ()_DONE[DONE] != 0x0).\n+\n+\t\tA queue may not be reconfigured until:\n+\t\t1. CPT()_VQ()_CTL[ENA] is cleared by software.\n+\t\t2. [INFLIGHT] is polled until equals to zero.\n+\t\t */\n+#else /* Word 0 - Little Endian */\n+\t\tuint64_t inflight : 8;\n+\t\t/**< [ 7: 0](RO/H) Inflight count. Counts the number of\n+\t\t * instructions for the VF for which CPT is fetching, executing\n+\t\t * or responding to instructions. However this does not include\n+\t\t * any interrupts that are awaiting software handling\n+\t\t * (CPT()_VQ()_DONE[DONE] != 0x0).\n+\n+\t\tA queue may not be reconfigured until:\n+\t\t1. CPT()_VQ()_CTL[ENA] is cleared by software.\n+\t\t2. [INFLIGHT] is polled until equals to zero.\n+\t\t */\n+\t\tuint64_t reserved_8_63 : 56;\n+#endif /* Word 0 - End */\n+\t} s;\n+\t/* struct cptx_vqx_inprog_s cn; */\n+} cptx_vqx_inprog_t;\n+\n+/**\n+ * Register (NCB) cpt#_vq#_misc_int\n+ *\n+ * CPT Queue Misc Interrupt Register\n+ * These registers contain the per-queue miscellaneous interrupts.\n+ */\n+typedef union {\n+\tuint64_t u;\n+\tstruct cptx_vqx_misc_int_s {\n+#if (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__) /* Word 0 - Big Endian */\n+\t\tuint64_t reserved_7_63 : 57;\n+\t\tuint64_t fault\t\t : 1;\n+\t\t/**< [ 6: 6](R/W1C/H) Translation fault detected. */\n+\t\tuint64_t hwerr\t\t : 1;\n+\t\t/**< [ 5: 5](R/W1C/H) Hardware error from engines. */\n+\t\tuint64_t swerr : 1;\n+\t\t/**< [ 4: 4](R/W1C/H) Software error from engines. */\n+\t\tuint64_t nwrp : 1;\n+\t\t/**< [ 3: 3](R/W1C/H) NCB result write response error. */\n+\t\tuint64_t irde : 1;\n+\t\t/**< [ 2: 2](R/W1C/H) Instruction NCB read response error. */\n+\t\tuint64_t dovf : 1;\n+\t\t/**< [ 1: 1](R/W1C/H) Doorbell overflow. */\n+\t\tuint64_t mbox : 1;\n+\t\t/**< [ 0: 0](R/W1C/H) PF to VF mailbox interrupt. Set when\n+\t\t * CPT()_VF()_PF_MBOX(0) is written.\n+\t\t **/\n+#else /* Word 0 - Little Endian */\n+\t\tuint64_t mbox : 1;\n+\t\t/**< [ 0: 0](R/W1C/H) PF to VF mailbox interrupt. Set when\n+\t\t * CPT()_VF()_PF_MBOX(0) is written.\n+\t\t **/\n+\t\tuint64_t dovf : 1;\n+\t\t/**< [ 1: 1](R/W1C/H) Doorbell overflow. */\n+\t\tuint64_t irde : 1;\n+\t\t/**< [ 2: 2](R/W1C/H) Instruction NCB read response error. */\n+\t\tuint64_t nwrp : 1;\n+\t\t/**< [ 3: 3](R/W1C/H) NCB result write response error. */\n+\t\tuint64_t swerr : 1;\n+\t\t/**< [ 4: 4](R/W1C/H) Software error from engines. */\n+\t\tuint64_t hwerr\t\t : 1;\n+\t\t/**< [ 5: 5](R/W1C/H) Hardware error from engines. */\n+\t\tuint64_t fault\t\t : 1;\n+\t\t/**< [ 6: 6](R/W1C/H) Translation fault detected. */\n+\t\tuint64_t reserved_5_63 : 59;\n+#endif /* Word 0 - End */\n+\t} s;\n+\t/* struct cptx_vqx_misc_int_s cn; */\n+} cptx_vqx_misc_int_t;\n+\n+/**\n+ * Register (NCB) cpt#_vq#_saddr\n+ *\n+ * CPT Queue Starting Buffer Address Registers\n+ * These registers set the instruction buffer starting address.\n+ */\n+typedef union {\n+\tuint64_t u;\n+\tstruct cptx_vqx_saddr_s\t{\n+#if (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__) /* Word 0 - Big Endian */\n+\t\tuint64_t reserved_49_63 : 15;\n+\t\tuint64_t ptr : 43;\n+\t\t/**< [ 48: 6](R/W/H) Instruction buffer IOVA <48:6>\n+\t\t * (64-byte aligned). When written, it is the initial buffer\n+\t\t * starting address; when read, it is the next read pointer to\n+\t\t * be requested from L2C. The PTR field is overwritten with the\n+\t\t * next pointer each time that the command buffer segment is\n+\t\t * exhausted. New commands will then be read from the newly\n+\t\t * specified command buffer pointer.\n+\t\t **/\n+\t\tuint64_t reserved_0_5 : 6;\n+#else /* Word 0 - Little Endian */\n+\t\tuint64_t reserved_0_5 : 6;\n+\t\tuint64_t ptr : 43;\n+\t\t/**< [ 48: 6](R/W/H) Instruction buffer IOVA <48:6>\n+\t\t * (64-byte aligned). When written, it is the initial buffer\n+\t\t * starting address; when read, it is the next read pointer to\n+\t\t * be requested from L2C. The PTR field is overwritten with the\n+\t\t * next pointer each time that the command buffer segment is\n+\t\t * exhausted. New commands will then be read from the newly\n+\t\t * specified command buffer pointer.\n+\t\t **/\n+\t\tuint64_t reserved_49_63 : 15;\n+#endif /* Word 0 - End */\n+\t} s;\n+\t/* struct cptx_vqx_saddr_s cn; */\n+} cptx_vqx_saddr_t;\n+\n+#endif /*__CPT_HW_TYPES_H*/\ndiff --git a/drivers/crypto/cpt/base/mcode_defines.h b/drivers/crypto/cpt/base/mcode_defines.h\nnew file mode 100644\nindex 0000000..15e7e60\n--- /dev/null\n+++ b/drivers/crypto/cpt/base/mcode_defines.h\n@@ -0,0 +1,215 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2017 Cavium, Inc\n+ */\n+\n+#ifndef _MCODE_DEFINES_H_\n+#define _MCODE_DEFINES_H_\n+\n+#include <stddef.h>\n+#include <stdint.h>\n+\n+/*SE opcodes*/\n+#define MAJOR_OP_FC 0x33\n+#define MAJOR_OP_HASH 0x34\n+#define MAJOR_OP_HMAC 0x35\n+#define MAJOR_OP_ZUC_SNOW3G 0x37\n+#define MAJOR_OP_KASUMI 0x38\n+\n+#define BYTE_16 16\n+#define BYTE_24 24\n+#define BYTE_32 32\n+#define MAX_BUF_CNT 1024\n+#define MAX_SG_IN_OUT_CNT 16\n+#define MAX_SG_CNT (MAX_SG_IN_OUT_CNT/2)\n+\n+#define ENCRYPT 1\n+#define DECRYPT 0\n+#define OFFSET_CONTROL_BYTES 8\n+\n+#define DMA_MODE (1 << 7) /* Default support is with SG */\n+\n+#define FROM_CTX 0\n+#define FROM_DPTR 1\n+\n+typedef enum {\n+\tMD5_TYPE = 1,\n+\tSHA1_TYPE = 2,\n+\tSHA2_SHA224 = 3,\n+\tSHA2_SHA256 = 4,\n+\tSHA2_SHA384 = 5,\n+\tSHA2_SHA512 = 6,\n+\tGMAC_TYPE = 7,\n+\tXCBC_TYPE = 8,\n+\tSHA3_SHA224 = 10,\n+\tSHA3_SHA256 = 11,\n+\tSHA3_SHA384 = 12,\n+\tSHA3_SHA512 = 13,\n+\tSHA3_SHAKE256 = 14,\n+\tSHA3_SHAKE512 = 15,\n+\n+\t/* These are only for software use */\n+\tZUC_EIA3 = 0x90,\n+\tSNOW3G_UIA2 = 0x91,\n+\tKASUMI_F9_CBC = 0x92,\n+\tKASUMI_F9_ECB = 0x93,\n+} mc_hash_type_t;\n+\n+typedef enum {\n+\t/*\n+\t * These are defined by MC for Flexi crypto\n+\t * for field of 4 bits\n+\t */\n+\tDES3_CBC = 0x1,\n+\tDES3_ECB = 0x2,\n+\tAES_CBC = 0x3,\n+\tAES_ECB = 0x4,\n+\tAES_CFB = 0x5,\n+\tAES_CTR = 0x6,\n+\tAES_GCM = 0x7,\n+\tAES_XTS = 0x8,\n+\n+\t/* These are only for software use */\n+\tZUC_EEA3 = 0x90,\n+\tSNOW3G_UEA2 = 0x91,\n+\tKASUMI_F8_CBC = 0x92,\n+\tKASUMI_F8_ECB = 0x93,\n+} mc_cipher_type_t;\n+\n+typedef enum {\n+\tAES_128_BIT = 0x1,\n+\tAES_192_BIT = 0x2,\n+\tAES_256_BIT = 0x3\n+} mc_aes_type_t;\n+\n+typedef enum {\n+\t/*Microcode errors*/\n+\tNO_ERR = 0x00,\n+\tERR_OPCODE_UNSUPPORTED = 0x01,\n+\n+\t/*SCATTER GATHER*/\n+\tERR_SCATTER_GATHER_WRITE_LENGTH = 0x02,\n+\tERR_SCATTER_GATHER_LIST = 0x03,\n+\tERR_SCATTER_GATHER_NOT_SUPPORTED = 0x04,\n+\n+\t/*SE GC*/\n+\tERR_GC_LENGTH_INVALID = 0x41,\n+\tERR_GC_RANDOM_LEN_INVALID = 0x42,\n+\tERR_GC_DATA_LEN_INVALID = 0x43,\n+\tERR_GC_DRBG_TYPE_INVALID = 0x44,\n+\tERR_GC_CTX_LEN_INVALID = 0x45,\n+\tERR_GC_CIPHER_UNSUPPORTED = 0x46,\n+\tERR_GC_AUTH_UNSUPPORTED = 0x47,\n+\tERR_GC_OFFSET_INVALID = 0x48,\n+\tERR_GC_HASH_MODE_UNSUPPORTED = 0x49,\n+\tERR_GC_DRBG_ENTROPY_LEN_INVALID = 0x4a,\n+\tERR_GC_DRBG_ADDNL_LEN_INVALID = 0x4b,\n+\tERR_GC_ICV_MISCOMPARE = 0x4c,\n+\tERR_GC_DATA_UNALIGNED = 0x4d,\n+\n+\t/* API Layer */\n+\tERR_BAD_ALT_CCODE = 0xfd,\n+\tERR_REQ_PENDING = 0xfe,\n+\tERR_REQ_TIMEOUT = 0xff,\n+\n+\tERR_BAD_INPUT_LENGTH = (0x40000000 | 384), /* 0x40000180 */\n+\tERR_BAD_KEY_LENGTH,\n+\tERR_BAD_KEY_HANDLE,\n+\tERR_BAD_CONTEXT_HANDLE,\n+\tERR_BAD_SCALAR_LENGTH,\n+\tERR_BAD_DIGEST_LENGTH,\n+\tERR_BAD_INPUT_ARG,\n+\tERR_BAD_RECORD_PADDING,\n+\tERR_NB_REQUEST_PENDING,\n+\tERR_EIO,\n+\tERR_ENODEV,\n+} mc_error_code_t;\n+\n+/* FC offset_control at start of DPTR in bytes */\n+#define OFF_CTRL_LEN 8 /* bytes */\n+#define SHA1_BLOCK_SIZE 64\n+\n+typedef union {\n+\tuint64_t flags;\n+\tstruct {\n+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__\n+\t\tuint64_t enc_cipher : 4;\n+\t\tuint64_t reserved1 : 1;\n+\t\tuint64_t aes_key : 2;\n+\t\tuint64_t iv_source : 1;\n+\t\tuint64_t hash_type : 4;\n+\t\tuint64_t reserved2 : 3;\n+\t\tuint64_t auth_input_type : 1;\n+\t\tuint64_t mac_len : 8;\n+\t\tuint64_t reserved3 : 8;\n+\t\tuint64_t encr_offset : 16;\n+\t\tuint64_t iv_offset : 8;\n+\t\tuint64_t auth_offset : 8;\n+#else\n+\t\tuint64_t auth_offset : 8;\n+\t\tuint64_t iv_offset : 8;\n+\t\tuint64_t encr_offset : 16;\n+\t\tuint64_t reserved3 : 8;\n+\t\tuint64_t mac_len : 8;\n+\t\tuint64_t auth_input_type : 1;\n+\t\tuint64_t reserved2 : 3;\n+\t\tuint64_t hash_type : 4;\n+\t\tuint64_t iv_source : 1;\n+\t\tuint64_t aes_key : 2;\n+\t\tuint64_t reserved1 : 1;\n+\t\tuint64_t enc_cipher : 4;\n+#endif\n+\t} e;\n+} encr_ctrl_t;\n+\n+typedef struct {\n+\tencr_ctrl_t enc_ctrl;\n+\tuint8_t encr_key[32];\n+\tuint8_t encr_iv[16];\n+} mc_enc_context_t;\n+\n+typedef struct {\n+\tuint8_t ipad[64];\n+\tuint8_t opad[64];\n+} mc_fc_hmac_context_t;\n+\n+typedef struct {\n+\tmc_enc_context_t enc;\n+\tmc_fc_hmac_context_t hmac;\n+} mc_fc_context_t;\n+\n+typedef struct {\n+\tuint8_t encr_auth_iv[16];\n+\tuint8_t ci_key[16];\n+\tuint8_t zuc_const[32];\n+} mc_zuc_snow3g_ctx_t;\n+\n+typedef struct {\n+\tuint8_t reg_A[8];\n+\tuint8_t ci_key[16];\n+} mc_kasumi_ctx_t;\n+\n+#define ENC_CTRL(fctx) fctx.enc.enc_ctrl.e\n+#define AUTH_CTRL(fctx) fctx.auth.auth_ctrl\n+#define P_ENC_CTRL(fctx) fctx->enc.enc_ctrl.e\n+\n+#define MAX_IVLEN 16\n+#define MAX_KEYLEN 32\n+\n+/**\n+ * Enumeration cpt_comp_e\n+ *\n+ * CPT Completion Enumeration\n+ * Enumerates the values of CPT_RES_S[COMPCODE].\n+ */\n+typedef enum {\n+\tCPT_COMP_E_NOTDONE = (0x00),\n+\tCPT_COMP_E_GOOD = (0x01),\n+\tCPT_COMP_E_FAULT = (0x02),\n+\tCPT_COMP_E_SWERR = (0x03),\n+\tCPT_COMP_E_HWERR = (0x04),\n+\tCPT_COMP_E_LAST_ENTRY = (0xFF)\n+} cpt_comp_e_t;\n+\n+/** @endcond */\n+\n+#endif /* _MCODE_DEFINES_H_ */\n", "prefixes": [ "dpdk-dev", "02/16" ] }