get:
Show a patch.

patch:
Update a patch.

put:
Update a patch.

GET /api/patches/40865/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 40865,
    "url": "http://patchwork.dpdk.org/api/patches/40865/?format=api",
    "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/1528476325-15585-5-git-send-email-anoob.joseph@caviumnetworks.com/",
    "project": {
        "id": 1,
        "url": "http://patchwork.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1528476325-15585-5-git-send-email-anoob.joseph@caviumnetworks.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1528476325-15585-5-git-send-email-anoob.joseph@caviumnetworks.com",
    "date": "2018-06-08T16:45:13",
    "name": "[dpdk-dev,04/16] crypto/cpt/base: add hardware enq/deq API for CPT",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "c38bd89805d6de9d4c7e87ee6835126f2b4eee3c",
    "submitter": {
        "id": 893,
        "url": "http://patchwork.dpdk.org/api/people/893/?format=api",
        "name": "Anoob Joseph",
        "email": "anoob.joseph@caviumnetworks.com"
    },
    "delegate": {
        "id": 6690,
        "url": "http://patchwork.dpdk.org/api/users/6690/?format=api",
        "username": "akhil",
        "first_name": "akhil",
        "last_name": "goyal",
        "email": "gakhil@marvell.com"
    },
    "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/1528476325-15585-5-git-send-email-anoob.joseph@caviumnetworks.com/mbox/",
    "series": [
        {
            "id": 58,
            "url": "http://patchwork.dpdk.org/api/series/58/?format=api",
            "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=58",
            "date": "2018-06-08T16:45:09",
            "name": "Adding Cavium's crypto device(CPT) driver",
            "version": 1,
            "mbox": "http://patchwork.dpdk.org/series/58/mbox/"
        }
    ],
    "comments": "http://patchwork.dpdk.org/api/patches/40865/comments/",
    "check": "warning",
    "checks": "http://patchwork.dpdk.org/api/patches/40865/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 0E8641BB0F;\n\tFri,  8 Jun 2018 18:49:00 +0200 (CEST)",
            "from NAM04-SN1-obe.outbound.protection.outlook.com\n\t(mail-eopbgr700086.outbound.protection.outlook.com [40.107.70.86])\n\tby dpdk.org (Postfix) with ESMTP id 73DC51BA9A\n\tfor <dev@dpdk.org>; Fri,  8 Jun 2018 18:48:58 +0200 (CEST)",
            "from ajoseph83.caveonetworks.com.caveonetworks.com (115.113.156.2)\n\tby SN6PR07MB4911.namprd07.prod.outlook.com (2603:10b6:805:3c::29)\n\twith Microsoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.820.15;\n\tFri, 8 Jun 2018 16:48:53 +0000"
        ],
        "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=CAVIUMNETWORKS.onmicrosoft.com; s=selector1-cavium-com;\n\th=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n\tbh=h3U64+nfhDzEAitmABYPlzXMXkJ5u03IoChIh2ut9f0=;\n\tb=hXZOlaw3/+/0Slv0mkstqwlMNQvS/RBuqnA1QinAXKBdtSaXqr51TbZAE7jPsvO/EQyakpmrg52idMpD7qKBgOBH8bV3bEB+h0cj0VUHgvuED22yvEJKRi8xBoBbb2bSsF9DsKBHB2sRTQXC6x1CGfVIHHGJl47b2CvfaaJ8GFg=",
        "Authentication-Results": "spf=none (sender IP is )\n\tsmtp.mailfrom=Anoob.Joseph@cavium.com; ",
        "From": "Anoob Joseph <anoob.joseph@caviumnetworks.com>",
        "To": "Akhil Goyal <akhil.goyal@nxp.com>,\n\tPablo de Lara <pablo.de.lara.guarch@intel.com>,\n\tThomas Monjalon <thomas@monjalon.net>",
        "Cc": "Ankur Dwivedi <ankur.dwivedi@cavium.com>,\n\tJerin Jacob <jerin.jacob@caviumnetworks.com>,\n\tMurthy NSSR <Nidadavolu.Murthy@cavium.com>,\n\tNarayana Prasad <narayanaprasad.athreya@caviumnetworks.com>,\n\tNithin Dabilpuram <nithin.dabilpuram@cavium.com>,\n\tRagothaman Jayaraman <Ragothaman.Jayaraman@cavium.com>,\n\tSrisivasubramanian Srinivasan\n\t<Srisivasubramanian.Srinivasan@cavium.com>, dev@dpdk.org",
        "Date": "Fri,  8 Jun 2018 22:15:13 +0530",
        "Message-Id": "<1528476325-15585-5-git-send-email-anoob.joseph@caviumnetworks.com>",
        "X-Mailer": "git-send-email 2.7.4",
        "In-Reply-To": "<1528476325-15585-1-git-send-email-anoob.joseph@caviumnetworks.com>",
        "References": "<1528476325-15585-1-git-send-email-anoob.joseph@caviumnetworks.com>",
        "MIME-Version": "1.0",
        "Content-Type": "text/plain",
        "X-Originating-IP": "[115.113.156.2]",
        "X-ClientProxiedBy": "BM1PR01CA0071.INDPRD01.PROD.OUTLOOK.COM\n\t(2603:1096:b00:1::11) To SN6PR07MB4911.namprd07.prod.outlook.com\n\t(2603:10b6:805:3c::29)",
        "X-MS-PublicTrafficType": "Email",
        "X-Microsoft-Antispam": "UriScan:; BCL:0; PCL:0;\n\tRULEID:(7020095)(4652020)(5600026)(4534165)(7168020)(4627221)(201703031133081)(201702281549075)(2017052603328)(7153060)(7193020);\n\tSRVR:SN6PR07MB4911; ",
        "X-Microsoft-Exchange-Diagnostics": [
            "1; SN6PR07MB4911;\n\t3:R+OqsF/rSByYvYurEcgfzccvPVFkwxzt0E9j0PcphxTbcFWUU9DEpLWDP4xdjkvEztJKaMLXnfraQfmY4KUqbwmiHrgF72u0JEKiW8GiyzAkYAo/JfSFI3KOhyUG37tAMui69RcLAmGFmMezarNoDJUxunhVV4w+QwhBW5+BAAWEMZds3ArG0ifjE4zAIOakS91hincNM4Br8WusgevErCtd+vP8RFcLIglHHoV5R/K4HV4wjZYNgEmp/qy5XWie;\n\t25:CBXaCcf7nbexC3DGdvyOd0vrlg4XnZ2LyEt8DtS0u8PvNA++lMwNeV6XktGO+vnqCXHtyN5x8fLf2YSlNnbFgMR0t4L/Gkw+rg0mRmHfVFz1rUFuNsJX9EpK26XZJccybSr5xGDOakN4U/toisYXHVv38TnBfXIsS2tScIuEJ8oZyBvShUhDa9OJ02dTLQzdf36yn9XQyq7EpFSRcquqwBpI23xBXRQPrPXZPb522q1NBFzoUzhGpwM8kAZ5f4fuWL4bzroZegXeWgJ0SWg6pB5TXeC5RDmZx/Nu1J4Bl+il+0jaq/+m9M0gtWz3N1gPbuaCD3aq3SbFPtd9djYf2A==;\n\t31:xeA74f66kC560svSSCwgpD/JlO8IACUikMyYpiAmuAhVDtNEBSqmQAQW4Qcsln9iaGvEsRXZ7mfWl9EWiqDtvZkL3QGuo1gsGu/QQz+lUigqkq+9ika8oC7jSI8bLvV/sFjsrUGdNHNvsp3bcCJhurA6Y/Gykm6KHbCsBe5wG6cm7SXZhrSyABpicHr4xnZNq4HhzbqrYdMVNkgfYrpW64Y7VsQW14yI6jJiqOxbwGU=",
            "1; SN6PR07MB4911;\n\t20:TX8qNtyTTjpp0RA11ougndaPQVPxm2oP34kBESvOZhlAUTg2u2PuwPGELUHOrv5rhh4VvgXgZDsWJA+vfd4MAlTDHtqwCRvV9+PfoqPBwzLLDiNu+EsjyojAuve6cvhn8qOQT2nFe0PreiOfcTUT3D0courAbYoRuFZXFYOJ1L4eFrdjlD6G7DzNKaTdHJag3vo5gaHREB/RkX1oza4oek+82k8LPxY/GKJPkhc+KM0CkMj7LVQa/X6XnJnCPsBAUS+ak66j80l9BXJVgeXU+kBNFKSxO1vT4KSCRlQzuMCZDCoKSoF9dhRq7yUl0tN+8fTPbMqUVRGH9DCOMr4LyOtHiMu36Y4CidhNXQwCNRDhyWHzIg2Wb+sZUg1B8yFDF9l39KDHdnTFSKFuBv/7z9Y5IRlY2nWpGtlFxPLwCxpL00GqORsLyyva2XHqxwc4RrE9Ta5jrU7FHOiu1+FqYG/+PL9VvswSWYTvXpEzTh/G/I5MU/a7orBKxSIRTTG19HVZlDVfcSzVVIfDoylyxsC4eUUhw82f/heTTTnk/3ncORTqZE2Nuj1yofIqdEiBs//6XKkPSuRfh1k8wXsgsts/PASIi7rf7NEhhCfheGE=;\n\t4:Uxgc74jQ9fjobJq0yzW54frc2SwRPrWt6xASNQyUORQVzCe60ZPl0COVW7QcX8RhpsJ0uwBRIhziR+4yBsK98GpOhFxJT9gM0skVmIFgYvPHi+nEwfCWXUyx5Qh5llmiYXAvV2/8jDL15e9Qg7/POFD+jaRAXx6ecwHCz6GAwE7/Pf6l34MuGRinjaGLQ8O102N90m/9ddSiAjWgnq0SyREArtADEfjlY4kfh18jUkGXdtPaIPYUnysYhCt3IXvHvIYA7uqeMs5r43qw0fdOZg==",
            "=?us-ascii?Q?1; SN6PR07MB4911;\n\t23:i4O7IMbpXHXLgUgJfBEEsmQ7wUrk5/VS4zcBRFzsa?=\n\tkMqtOeuTKeehQ2UzVCXbRdRVezVJIffET+QNNGPb1XtiTLK4Xbu+n6xZRDWQNwsoGLScwXEMsTNoXlKHWqbOXUrDNAf6ELYkdO9hkZmfgjWDcnUTun1rz/6iKJPwLx+fose5J013LfWseysfPWoJ077nYGPbkuLvm1RgnNh0mul6ZGEoChaQplqfJT6MjNdzxcYz2q+O0TRrr4PdjF3I41s+FDM6VagiQ+TnUCVcbN9mXiWaBPOOrqf0u7h8FPaGWBT+5g47dZ/TPW8dIAn+5N9Yu+sFWAmt+RiDFyM5S7/BFhrW1gipqw3DB2ZzzWA9C14oZlgPJ7yfWKyQF/U1jT6QO6LPhIY0uWQnFY1LknQklcJHAP+Pqt1WAAYOW5uhpIXbRQFPQxuvcZnIEKmOaBJxYtWh8AAsMtk99/bRDxCjdCcmQFvcFftiDK9fJxJ3vMiHjQHlZmHoPnpTfDTo5N0yYanQ1I24Eg1igVKFTXz3ld77ehNC9AjwneRLCR9vrVqnU2xipXgNCAegZqlzu1rIoYKZgfFD5TLEdin8hhIJ58msuo9ZSKsggslnvnV6VBl+LYIsO9e2Qejf7pOxgk5cGsVTjhTicsBs1kgJMlEgO3roOEd03O9mymKj5PHS/h7voRVwV+DxnsuSgNZ5SZBNdCQYJSk0NAj8R5+P7pjOXzLKMTOEwNrwi3irN5ARMPfI42R1BAehZuEdOx23P7T/x/eNohXTHBS1XgY/tydAaSDdf3gf1t7icWyY7G3/6VvitdwrcBgFJ8x1ZYP2ufAzZXQmsT5qgXUQ1J5P2wUr06/NufauNsUNgl2KqyAGJBM/rCkk85sQyU0K2qaz6pGDR8/s5+RFI4ogOCVnZHXH+RTC66lrc6pGCHCmt9pIhSBO87qg7WW6HDunuIT5j+ci04NYGSjixejmZ5H9OW35bMbSdH+ONqFrcTesDgD18yasCn5QzPJL/y39u0y+qRTi9G/BKIhCdF2JcXNHMKn7899kKQjpUes2y6XKPmh+r6DK9HJNyMK8ssDjIcIL/xE5Dq/Tlfpu7ZsazvQD7QehbRKokMmfhAMWu9OONeRDQXPxFAiDekDrimrEfsyyAyH5u/yKNBQVciBM6UQnO0s0MRwNA/+mKuneJ1YpZGNjgR+1V/N26L+3BT4f8JJ4t3GF3g8fAe2WNRa2vHpCPQzljSa8MViFFM6s9XeR+c6/2ELpdBPqbVF4QeWm9prfXB9Wj2W+YCm6Ut+ggFCmkTG1tSSdU7lCzbTvV12vSaAMaA=",
            "1; SN6PR07MB4911;\n\t6:HGTQqqhVMVMV8vRc1F0+cyPgwzVIz1rJQ6rfofYNIhExdvzDzom/VxrXdkEg9qO8P7JeQRHJhNVlRaeXmDO4m2vANq+N5lkuFtnYcxM40BYsv2zlsiDTBsQwCBhyTHN8hDcUFk2/aTeQTvTKDSUiL4VMcmY1nkXrLRRN/NSVaJ1L2WYCMuCGfkUP7fPEvbteRnYYwkAxPcdHN8ymJJ49umMXwljmZg2rkCPBNVLVCz1GQvDOI4CpBo6UYOGgNU7Vj1WUSY/JK9uhhu8gsJm8GXQe0qEsuIOjjK0g9kQ8vw0AEJMLJjvBF4IC6T+zwRLADuxcVoj7KCR2U7L7KA6pjm3YRewSvGhPtTi6K260ySR1PDK+e6BX2Dfm48XdnO2ovocAmgJew9sS+hyNYxdzzIdvIS6MMDskbKz0Y+ofs5mQwxagz0wdlbajjV4O2815n5D7Hnv/+6cFecpGICF36Q==;\n\t5:CR4tn1ig4z64hATi8Qn3lZxNbMTyW0S8v2fwjrxxsBeWHK5tJxSksgbz4BRMVV7cA1zlcRoKqt3amdJeGAXYCWHXoaxqygs3wi0+yeNPXI//D2LEhRppn03GDldHBjmYaFr/B55wkrZYCeIySw8wPvu0RskbMNpxF1ZsDm2viWM=;\n\t24:3SSI1BMvwROl7T3cEup0fUsDvkhu0ogaxP4xUfAZFhkxiAJJV1s8DaN4zqRzXunvchjcm2goOO1i+LC5JDrUS/YmfU3vDP1BQaadfePvOZI=",
            "1; SN6PR07MB4911;\n\t7:fqH+j4nuhCiWxegvOrNdQMI+BpjzvPTc0o+6Eb/7Gg8oV0FAT5ttRxwelYytqIa9OZ5UaFpYFIOcXAehS/r1GjxCjk9u/SABP8KcA/siH7fCPeOXUp39kdBwbY6C1B/8K9TvDekko+hoxlEtHx2poKkPBCCyXW7bq93wZne92RVYYUHZi/Og1zXckLbqjTkHIrSiyaqQYezVsW0iv1jcDRb5pPsfRu3noGgYirb8rpavwgPSf0VnBnYbuwSbALq2"
        ],
        "X-MS-TrafficTypeDiagnostic": "SN6PR07MB4911:",
        "X-Microsoft-Antispam-PRVS": "<SN6PR07MB4911E762D6318D6C2B57910BF87B0@SN6PR07MB4911.namprd07.prod.outlook.com>",
        "X-Exchange-Antispam-Report-Test": "UriScan:;",
        "X-MS-Exchange-SenderADCheck": "1",
        "X-Exchange-Antispam-Report-CFA-Test": "BCL:0; PCL:0;\n\tRULEID:(8211001083)(6040522)(2401047)(8121501046)(5005006)(10201501046)(93006095)(3002001)(3231254)(944501410)(52105095)(149027)(150027)(6041310)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123560045)(20161123562045)(20161123558120)(20161123564045)(6072148)(201708071742011)(7699016);\n\tSRVR:SN6PR07MB4911; BCL:0; PCL:0; RULEID:; SRVR:SN6PR07MB4911; ",
        "X-Forefront-PRVS": "06973FFAD3",
        "X-Forefront-Antispam-Report": "SFV:NSPM;\n\tSFS:(10009020)(376002)(396003)(346002)(39380400002)(366004)(39860400002)(189003)(199004)(26005)(52116002)(956004)(305945005)(8676002)(81156014)(50226002)(8936002)(81166006)(7736002)(68736007)(105586002)(106356001)(3846002)(6116002)(72206003)(478600001)(6486002)(97736004)(6506007)(16586007)(6512007)(53936002)(47776003)(486006)(25786009)(5660300001)(50466002)(48376002)(6666003)(4326008)(54906003)(76176011)(36756003)(110136005)(66066001)(8656006)(2906002)(316002)(55236004)(11346002)(16526019)(386003)(186003)(59450400001)(446003)(476003)(42882007)(44832011)(2616005)(51416003);\n\tDIR:OUT; SFP:1101; SCL:1; SRVR:SN6PR07MB4911;\n\tH:ajoseph83.caveonetworks.com.caveonetworks.com; FPR:; SPF:None;\n\tLANG:en; PTR:InfoNoRecords; MX:1; A:1; ",
        "Received-SPF": "None (protection.outlook.com: cavium.com does not designate\n\tpermitted sender hosts)",
        "X-Microsoft-Antispam-Message-Info": "GbIddRS2urVxRh0AZ8zgzf5QVeL1mIzoZLqk3by/taCsvsNcBtNKzjDWrOu0h5oGml1PAvLysUWNVkh42x3t/U9ZwVrb0HZhbE9zr3Zn0UMwa9XaIjYHskBGI5utGVbG9RhWGqu6oq0JZN+1SkrKiVF/mzCmpi6TjKLfRg586wwCPqm/hYebNIwgGyqcLt5f",
        "SpamDiagnosticOutput": "1:99",
        "SpamDiagnosticMetadata": "NSPM",
        "X-MS-Office365-Filtering-Correlation-Id": "a6da77ce-a7f6-4283-d2c5-08d5cd5fb9fc",
        "X-OriginatorOrg": "caviumnetworks.com",
        "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "08 Jun 2018 16:48:53.1908\n\t(UTC)",
        "X-MS-Exchange-CrossTenant-Network-Message-Id": "a6da77ce-a7f6-4283-d2c5-08d5cd5fb9fc",
        "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted",
        "X-MS-Exchange-CrossTenant-Id": "711e4ccf-2e9b-4bcf-a551-4094005b6194",
        "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "SN6PR07MB4911",
        "Subject": "[dpdk-dev] [PATCH 04/16] crypto/cpt/base: add hardware enq/deq API\n\tfor CPT",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://dpdk.org/ml/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "From: Ankur Dwivedi <ankur.dwivedi@cavium.com>\n\nAdds hardware enqueue/dequeue API of instructions to a queue pair\nfor Cavium CPT device.\n\nSigned-off-by: Ankur Dwivedi <ankur.dwivedi@cavium.com>\nSigned-off-by: Murthy NSSR <Nidadavolu.Murthy@cavium.com>\nSigned-off-by: Nithin Dabilpuram <nithin.dabilpuram@cavium.com>\nSigned-off-by: Ragothaman Jayaraman <Ragothaman.Jayaraman@cavium.com>\nSigned-off-by: Srisivasubramanian Srinivasan <Srisivasubramanian.Srinivasan@cavium.com>\n---\n drivers/crypto/cpt/base/cpt.h             | 102 +++++++\n drivers/crypto/cpt/base/cpt_device.c      |   4 +-\n drivers/crypto/cpt/base/cpt_request_mgr.c | 424 ++++++++++++++++++++++++++++++\n drivers/crypto/cpt/base/cpt_request_mgr.h |  75 ++++++\n 4 files changed, 603 insertions(+), 2 deletions(-)\n create mode 100644 drivers/crypto/cpt/base/cpt.h\n create mode 100644 drivers/crypto/cpt/base/cpt_request_mgr.c\n create mode 100644 drivers/crypto/cpt/base/cpt_request_mgr.h",
    "diff": "diff --git a/drivers/crypto/cpt/base/cpt.h b/drivers/crypto/cpt/base/cpt.h\nnew file mode 100644\nindex 0000000..11407ae\n--- /dev/null\n+++ b/drivers/crypto/cpt/base/cpt.h\n@@ -0,0 +1,102 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2017 Cavium, Inc\n+ */\n+\n+#ifndef __BASE_CPT_H__\n+#define __BASE_CPT_H__\n+\n+/* Linux Includes */\n+#include <endian.h>\n+#include <stdint.h>\n+#include <string.h>\n+#include <stdio.h>\n+#include <stdbool.h>\n+#include <errno.h>\n+#include <sys/cdefs.h>\n+#include <unistd.h>\n+#include <assert.h>\n+\n+/* DPDK includes */\n+#include <rte_byteorder.h>\n+#include <rte_common.h>\n+#include <rte_errno.h>\n+#include <rte_memory.h>\n+#include <rte_prefetch.h>\n+\n+#include \"../cpt_pmd_logs.h\"\n+#include \"mcode_defines.h\"\n+\n+/** @cond __INTERNAL_DOCUMENTATION__ */\n+\n+/* Declarations */\n+typedef struct cpt_instance cpt_instance_t;\n+\n+/*\n+ * Generic Defines\n+ */\n+\n+/* Buffer pointer */\n+typedef struct buf_ptr {\n+\tvoid *vaddr;\n+\tphys_addr_t dma_addr;\n+\tuint32_t size;\n+\tuint32_t resv;\n+} buf_ptr_t;\n+\n+/* IOV Pointer */\n+typedef struct{\n+\tint buf_cnt;\n+\tbuf_ptr_t bufs[0];\n+} iov_ptr_t;\n+\n+typedef struct app_data {\n+\tuint64_t pktout;\n+\tvoid *marker;\n+} app_data_t;\n+\n+/* Instance operations */\n+\n+/* Enqueue an SE/AE request */\n+int cpt_enqueue_req(cpt_instance_t *inst, void *req, uint8_t flags,\n+\t      void *event, uint64_t event_flags);\n+\n+/* Dequeue completed SE requests as burst */\n+int32_t cpt_dequeue_burst(cpt_instance_t *instance, uint16_t cnt,\n+\t\t\t  void *resp[], uint8_t cc[]);\n+\n+/* Marks event as done in event driven mode */\n+int32_t cpt_event_mark_done(void *marker, uint8_t *op_error);\n+\n+/* Checks queue full condition */\n+uint16_t cpt_queue_full(cpt_instance_t *instance);\n+\n+/* Misc */\n+uint32_t cpt_get_instance_count(void);\n+\n+#define ENQ_FLAG_SYNC\t\t0x01\n+#define ENQ_FLAG_EVENT\t\t0x02\n+#define ENQ_FLAG_NODOORBELL\t0x04\n+#define ENQ_FLAG_ONLY_DOORBELL\t0x08\n+\n+\n+#define OCTTX_EVENT_TAG(__flags) (__flags & 0xffffffff)\n+#define OCTTX_EVENT_GRP(__flags) ((__flags >> 32) & 0xffff)\n+#define OCTTX_EVENT_TT(__flags) ((__flags >> 48) & 0xff)\n+\n+#define OCTTX_EVENT_FLAGS(__tag, __grp, __tt)    \\\n+\t(((uint64_t)__tag & 0xffffffff) |        \\\n+\t (((uint64_t)__grp & 0xffff) << 32) |    \\\n+\t (((uint64_t)__tt & 0xff) << 48))\n+\n+\n+/* cpt instance */\n+struct cpt_instance {\n+\t/* 0th cache line */\n+\tuint32_t queue_id;\n+\tuint64_t rsvd;\n+};\n+\n+#define __hot __attribute__((hot))\n+/** @endcond */\n+\n+#endif /* __BASE_CPT_H__ */\ndiff --git a/drivers/crypto/cpt/base/cpt_device.c b/drivers/crypto/cpt/base/cpt_device.c\nindex b7cd5b5..a50e5b8 100644\n--- a/drivers/crypto/cpt/base/cpt_device.c\n+++ b/drivers/crypto/cpt/base/cpt_device.c\n@@ -193,7 +193,7 @@ int cptvf_get_resource(struct cpt_vf *dev,\n \tuint64_t *next_ptr;\n \tuint64_t pg_sz = sysconf(_SC_PAGESIZE);\n \n-\tPMD_DRV_LOG(DEBUG, \"Initializing csp resource %s\\n\", cptvf->dev_name);\n+\tPMD_DRV_LOG(DEBUG, \"Initializing cpt resource %s\\n\", cptvf->dev_name);\n \n \tcpt_instance = &cptvf->instance;\n \n@@ -323,7 +323,7 @@ int cptvf_put_resource(cpt_instance_t *instance)\n \t\treturn -EINVAL;\n \t}\n \n-\tPMD_DRV_LOG(DEBUG, \"Releasing csp device %s\\n\", cptvf->dev_name);\n+\tPMD_DRV_LOG(DEBUG, \"Releasing cpt device %s\\n\", cptvf->dev_name);\n \n \trz = (struct rte_memzone *)instance->rsvd;\n \trte_memzone_free(rz);\ndiff --git a/drivers/crypto/cpt/base/cpt_request_mgr.c b/drivers/crypto/cpt/base/cpt_request_mgr.c\nnew file mode 100644\nindex 0000000..8b9b1ff\n--- /dev/null\n+++ b/drivers/crypto/cpt/base/cpt_request_mgr.c\n@@ -0,0 +1,424 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2017 Cavium, Inc\n+ */\n+\n+#include \"cpt_request_mgr.h\"\n+#include \"cpt_debug.h\"\n+#include <rte_atomic.h>\n+\n+#define MOD_INC(i, l)   ((i) == (l - 1) ? (i) = 0 : (i)++)\n+\n+#define __hot __attribute__((hot))\n+\n+static inline uint64_t cpu_cycles(void)\n+{\n+\treturn rte_get_timer_cycles();\n+}\n+\n+static inline uint64_t cpu_cycles_freq(void)\n+{\n+\treturn rte_get_timer_hz();\n+}\n+\n+static inline void *\n+get_cpt_inst(struct command_queue *cqueue, void *req)\n+{\n+\t(void)req;\n+\tPMD_TX_LOG(DEBUG, \"CPT queue idx %u, req %p\\n\", cqueue->idx, req);\n+\treturn &cqueue->qhead[cqueue->idx * CPT_INST_SIZE];\n+}\n+\n+static inline void\n+mark_cpt_inst(struct cpt_vf *cptvf,\n+\t      struct command_queue *queue,\n+\t      uint32_t ring_door_bell)\n+{\n+#ifdef CMD_DEBUG\n+\t/* DEBUG */\n+\t{\n+\t\tuint32_t i = queue->idx * CPT_INST_SIZE;\n+\t\tcpt_inst_s_t *cmd = (void *)&queue->qhead[i];\n+\t\tuint64_t *p = (void *)&queue->qhead[i];\n+\n+\t\tPRINT(\"\\nQUEUE parameters:\");\n+\t\tPRINT(\"Queue index           = %u\\n\",\n+\t\t      queue->idx);\n+\t\tPRINT(\"Queue HEAD            = %p\\n\",\n+\t\t      queue->qhead);\n+\t\tPRINT(\"Command Entry         = %p\\n\",\n+\t\t      cmd);\n+\n+\t\tPRINT(\"\\nCPT_INST_S format:\");\n+\t\tPRINT(\"cmd->s.doneint = %x\\n\", cmd->s.doneint);\n+\t\tPRINT(\"cmd->s.res_addr  = %lx\\n\", cmd->s.res_addr);\n+\t\tPRINT(\"cmd->s.grp       = %x\\n\", cmd->s.grp);\n+\t\tPRINT(\"cmd->s.tag       = %x\\n\", cmd->s.tag);\n+\t\tPRINT(\"cmd->s.tt        = %x\\n\", cmd->s.tt);\n+\t\tPRINT(\"cmd->s.wq_ptr    = %lx\\n\", cmd->s.wq_ptr);\n+\t\tPRINT(\"cmd->s.ei0       = %lx\\n\", cmd->s.ei0);\n+\t\tPRINT(\"cmd->s.ei1       = %lx\\n\", cmd->s.ei1);\n+\t\tPRINT(\"cmd->s.ei2       = %lx\\n\", cmd->s.ei2);\n+\t\tPRINT(\"cmd->s.ei3       = %lx\\n\", cmd->s.ei3);\n+\n+\t\tPRINT(\"\\nCommand dump from queue HEAD:\");\n+\t\tfor (i = 0; i < CPT_INST_SIZE / 8; i++)\n+\t\t\tPRINT(\"%lx\\n\", p[i]);\n+\t}\n+#endif\n+\tif (unlikely(++queue->idx >= DEFAULT_CMD_QCHUNK_SIZE)) {\n+\t\tuint32_t cchunk = queue->cchunk;\n+\t\tMOD_INC(cchunk, DEFAULT_CMD_QCHUNKS);\n+\t\tqueue->qhead = queue->chead[cchunk].head;\n+\t\tqueue->idx = 0;\n+\t\tqueue->cchunk = cchunk;\n+\t}\n+\n+\tif (ring_door_bell) {\n+\t\t/* Memory barrier to flush pending writes */\n+\t\trte_smp_wmb();\n+\t\tcptvf_write_vq_doorbell(cptvf, ring_door_bell);\n+\t}\n+}\n+\n+static inline uint8_t\n+check_nb_command_id(cpt_request_info_t *user_req, struct cpt_vf *cptvf)\n+{\n+\tuint8_t ret = ERR_REQ_PENDING;\n+\tvolatile cpt_res_s_t *cptres;\n+\n+\tcptres = (volatile cpt_res_s_t *)user_req->completion_addr;\n+\n+\tif (unlikely(cptres->s.compcode == CPT_COMP_E_NOTDONE)) {\n+\t\t/*\n+\t\t * Wait for some time for this command to get completed\n+\t\t * before timing out\n+\t\t */\n+\t\tif (cpu_cycles() < user_req->time_out)\n+\t\t\treturn ret;\n+\t\t/*\n+\t\t * TODO: See if alternate caddr can be used to not loop\n+\t\t * longer than needed.\n+\t\t */\n+\t\tif ((cptres->s.compcode == CPT_COMP_E_NOTDONE) &&\n+\t\t    (user_req->extra_time < TIME_IN_RESET_COUNT)) {\n+\t\t\tuser_req->extra_time++;\n+\t\t\treturn ret;\n+\t\t}\n+\n+\t\tif (cptres->s.compcode != CPT_COMP_E_NOTDONE)\n+\t\t\tgoto complete;\n+\n+\t\tret = ERR_REQ_TIMEOUT;\n+\t\tPMD_DRV_LOG_RAW(ERR, \"Request %p timedout\\n\", user_req);\n+\t\tcptvf_poll_misc(cptvf);\n+\t\tdump_cpt_request_sglist(&user_req->dbg_inst,\n+\t\t\t\t\t\"Response Packet Gather in\", 1, 1);\n+\t\tgoto exit;\n+\t}\n+\n+complete:\n+\tif (likely(cptres->s.compcode == CPT_COMP_E_GOOD)) {\n+\t\tret = 0; /* success */\n+\t\tPMD_RX_LOG(DEBUG, \"MC status %.8x\\n\",\n+\t\t\t   *((volatile uint32_t *)user_req->alternate_caddr));\n+\t\tPMD_RX_LOG(DEBUG, \"HW status %.8x\\n\",\n+\t\t\t   *((volatile uint32_t *)user_req->completion_addr));\n+\t} else if ((cptres->s.compcode == CPT_COMP_E_SWERR) ||\n+\t\t   (cptres->s.compcode == CPT_COMP_E_FAULT)) {\n+\t\tret = (uint8_t)*user_req->alternate_caddr;\n+\t\tif (!ret)\n+\t\t\tret = ERR_BAD_ALT_CCODE;\n+\t\tPMD_RX_LOG(DEBUG, \"Request %p : failed with %s : err code :\"\n+\t\t\t   \"%x\\n\", user_req,\n+\t\t\t   (cptres->s.compcode == CPT_COMP_E_FAULT) ?\n+\t\t\t   \"DMA Fault\" : \"Software error\", ret);\n+\t} else {\n+\t\tPMD_DRV_LOG_RAW(ERR, \"Request %p : unexpected completion code\"\n+\t\t\t   \" %d\\n\",\n+\t\t\t   user_req, cptres->s.compcode);\n+\t\tret = (uint8_t)*user_req->alternate_caddr;\n+\t}\n+\n+exit:\n+\tdump_cpt_request_sglist(&user_req->dbg_inst,\n+\t\t\t\t\"Response Packet Scatter Out\", 1, 0);\n+\treturn ret;\n+}\n+\n+\n+/*\n+ * cpt_enqueue_req()\n+ *\n+ * SE & AE request enqueue function\n+ */\n+int32_t __hot\n+cpt_enqueue_req(cpt_instance_t *instance, void *req, uint8_t flags,\n+\t\tvoid *event, uint64_t event_flags)\n+{\n+\tstruct pending_queue *pqueue;\n+\tstruct cpt_vf *cptvf;\n+\tcpt_inst_s_t *cpt_ist_p = NULL;\n+\tcpt_request_info_t *user_req = (cpt_request_info_t *)req;\n+\tstruct command_queue *cqueue;\n+\tint32_t ret = 0;\n+\n+#ifdef CPTVF_STRICT_PARAM_CHECK\n+\tif (unlikely(!instance)) {\n+\t\tPMD_DRV_LOG_RAW(ERR, \"Invalid inputs (instance: %p, req: %p)\\n\",\n+\t\t\t   instance, req);\n+\t\treturn -EINVAL;\n+\t}\n+#endif\n+\n+\tcptvf = (struct cpt_vf *)instance;\n+\tpqueue = &cptvf->pqueue;\n+\n+\tif (unlikely(!req)) {\n+\t\t/* ring only pending doorbells */\n+\t\tif ((flags & ENQ_FLAG_ONLY_DOORBELL) && pqueue->p_doorbell) {\n+\t\t\t/* Memory barrier to flush pending writes */\n+\t\t\trte_smp_wmb();\n+\t\t\tcptvf_write_vq_doorbell(cptvf, pqueue->p_doorbell);\n+\t\t\tpqueue->p_doorbell = 0;\n+\t\t}\n+\t\treturn 0;\n+\t}\n+\n+#if defined(ATOMIC_THROTTLING_COUNTER)\n+\t/* Ask the application to try again later */\n+\tif (unlikely(cpt_pmd_pcount_load(&pqueue->pending_count) >=\n+\t\t     DEFAULT_CMD_QLEN)) {\n+\t\treturn -EAGAIN;\n+\t}\n+#else\n+\tif (unlikely(pqueue->pending_count >= DEFAULT_CMD_QLEN))\n+\t\treturn -EAGAIN;\n+#endif\n+\tcqueue = &cptvf->cqueue;\n+\tcpt_ist_p = get_cpt_inst(cqueue, req);\n+\trte_prefetch_non_temporal(cpt_ist_p);\n+\n+\t/* EI0, EI1, EI2, EI3 are already prepared */\n+\t/* HW W0 */\n+\tcpt_ist_p->u[0] = 0;\n+\t/* HW W1 */\n+\tcpt_ist_p->s.res_addr = user_req->comp_baddr;\n+\t/* HW W2 */\n+\tcpt_ist_p->u[2] = 0;\n+\t/* HW W3 */\n+\tcpt_ist_p->s.wq_ptr = 0;\n+\n+\t/* MC EI0 */\n+\tcpt_ist_p->s.ei0 = user_req->ist.ei0;\n+\t/* MC EI1 */\n+\tcpt_ist_p->s.ei1 = user_req->ist.ei1;\n+\t/* MC EI2 */\n+\tcpt_ist_p->s.ei2 = user_req->ist.ei2;\n+\t/* MC EI3 */\n+\tcpt_ist_p->s.ei3 = user_req->ist.ei3;\n+\n+\tPMD_TX_LOG(DEBUG, \"req: %p op: %p dma_mode 0x%x se_req %u\\n\",\n+\t\t   req,\n+\t\t   user_req->op,\n+\t\t   user_req->dma_mode,\n+\t\t   user_req->se_req);\n+\n+#ifdef CPT_DEBUG\n+\t{\n+\t\tvq_cmd_word0_t vq_cmd_w0;\n+\t\tvq_cmd_word3_t vq_cmd_w3;\n+\n+\t\tvq_cmd_w3.u64 = cpt_ist_p->s.ei3;\n+\t\tvq_cmd_w0.u64 = be64toh(cpt_ist_p->s.ei0);\n+\t\tuser_req->dbg_inst = *cpt_ist_p;\n+\n+\t\tif (vq_cmd_w3.s.cptr) {\n+\t\t\tPMD_TX_LOG(DEBUG, \"Context Handle: 0x%016lx\\n\",\n+\t\t\t\t   (uint64_t)vq_cmd_w3.s.cptr);\n+\t\t\t/* Dump max context i.e 448 bytes */\n+\t\t\tcpt_dump_buffer(\"CONTEXT\",\n+\t\t\t\t\tos_iova2va((uint64_t)vq_cmd_w3.s.cptr),\n+\t\t\t\t\t448);\n+\t\t}\n+\n+\t\tdump_cpt_request_info(user_req, cpt_ist_p);\n+\t\tdump_cpt_request_sglist(cpt_ist_p, \"Request (src)\", 1, 1);\n+\t\tdump_cpt_request_sglist(cpt_ist_p, \"Request (dst)\", 0, 0);\n+\t\tcpt_dump_buffer(\"VQ command word0\", &cpt_ist_p->u[4],\n+\t\t\t\tsizeof(vq_cmd_w0));\n+\t\tcpt_dump_buffer(\"VQ command word1\", &cpt_ist_p->u[5],\n+\t\t\t\tsizeof(uint64_t));\n+\t\tcpt_dump_buffer(\"VQ command word2\", &cpt_ist_p->u[6],\n+\t\t\t\tsizeof(uint64_t));\n+\t\tcpt_dump_buffer(\"VQ command word3\", &cpt_ist_p->u[7],\n+\t\t\t\tsizeof(vq_cmd_w3));\n+\t}\n+#endif\n+\n+\tif (likely(!(flags & ENQ_FLAG_SYNC))) {\n+\t\tvoid *op = user_req->op;\n+\n+\t\tif (unlikely(flags & ENQ_FLAG_EVENT)) {\n+\t\t\tapp_data_t *app_data = op;\n+\n+\t\t\t/* Event based completion */\n+\t\t\tcpt_ist_p->s.tag = OCTTX_EVENT_TAG(event_flags);\n+\t\t\tcpt_ist_p->s.grp = OCTTX_EVENT_GRP(event_flags);\n+\t\t\tcpt_ist_p->s.tt = OCTTX_EVENT_TT(event_flags);\n+\t\t\tcpt_ist_p->s.wq_ptr = (uint64_t)event;\n+\n+#if defined(ATOMIC_THROTTLING_COUNTER)\n+\t\t\tapp_data->marker = user_req;\n+\t\t\t__atomic_fetch_add(&pqueue->pending_count,\n+\t\t\t\t\t   1, __ATOMIC_RELAXED);\n+#else\n+\t\t\trid_t *rid_e;\n+\t\t\t/*\n+\t\t\t * Mark it as in progress in pending queue, software\n+\t\t\t * will mark it when completion is received\n+\t\t\t */\n+\t\t\trid_e = &pqueue->rid_queue[pqueue->enq_tail];\n+\t\t\trid_e->rid = (uint64_t)user_req;\n+\t\t\t/* rid_e->op = op; */\n+\t\t\tMOD_INC(pqueue->enq_tail, DEFAULT_CMD_QLEN);\n+\t\t\tapp_data->marker = rid_e;\n+#endif\n+\n+\t\t\tcpt_dump_buffer(\"CPT Instruction with wqe\", cpt_ist_p,\n+\t\t\t\t\tsizeof(*cpt_ist_p));\n+\n+\t\t\tmark_cpt_inst(cptvf, cqueue, 1);\n+\n+\t\t} else {\n+\t\t\tuint32_t doorbell = 0;\n+\n+\t\t\tif (likely(flags & ENQ_FLAG_NODOORBELL))\n+\t\t\t\tpqueue->p_doorbell++;\n+\t\t\telse\n+\t\t\t\tdoorbell = ++pqueue->p_doorbell;\n+\n+\t\t\t/* Fill time_out cycles */\n+\t\t\tuser_req->time_out = cpu_cycles() +\n+\t\t\t\tDEFAULT_COMMAND_TIMEOUT * cpu_cycles_freq();\n+\t\t\tuser_req->extra_time = 0;\n+\n+\t\t\tcpt_dump_buffer(\"CPT Instruction\", cpt_ist_p,\n+\t\t\t\t\tsizeof(*cpt_ist_p));\n+\n+\t\t\t/* Default mode of software queue */\n+\t\t\tmark_cpt_inst(cptvf, cqueue, doorbell);\n+\n+\t\t\tpqueue->p_doorbell -= doorbell;\n+\t\t\tpqueue->rid_queue[pqueue->enq_tail].rid =\n+\t\t\t\t(uint64_t)user_req;\n+\t\t\t/* pqueue->rid_queue[pqueue->enq_tail].op = op; */\n+\t\t\t/* We will use soft queue length here to limit\n+\t\t\t * requests\n+\t\t\t */\n+\t\t\tMOD_INC(pqueue->enq_tail, DEFAULT_CMD_QLEN);\n+\t\t\tpqueue->pending_count += 1;\n+\t\t}\n+\n+\t\tPMD_TX_LOG(DEBUG, \"Submitted NB cmd with request: %p op: %p\\n\",\n+\t\t\t   user_req, op);\n+\t} else {\n+\t\t/*\n+\t\t * Synchronous operation,\n+\t\t * hold until completion / timeout\n+\t\t */\n+\t\t/* Fill time_out cycles */\n+\t\tuser_req->time_out = cpu_cycles() +\n+\t\t\tDEFAULT_COMMAND_TIMEOUT * cpu_cycles_freq();\n+\t\tuser_req->extra_time = 0;\n+\n+\t\tcpt_dump_buffer(\"CPT Instruction\", cpt_ist_p,\n+\t\t\t\tsizeof(*cpt_ist_p));\n+\n+\t\t/* Default mode of software queue */\n+\t\tmark_cpt_inst(cptvf, cqueue, 1);\n+\n+\t\tdo {\n+\t\t\t/* TODO: should we pause */\n+\t\t\tret = check_nb_command_id(user_req, cptvf);\n+\t\t\tcptvf_poll_misc(cptvf);\n+#if 0\n+\t\t\tPMD_TX_LOG(DEBUG, \"Doorbell count for cptvf %s: %u\\n\",\n+\t\t\t\t   cptvf->dev_name,\n+\t\t\t\t   cptvf_read_vq_doorbell(cptvf));\n+#endif\n+\t\t} while (ret == ERR_REQ_PENDING);\n+\n+\t\tPMD_TX_LOG(DEBUG, \"Completed blocking cmd req: 0x%016llx, rc \"\n+\t\t\t   \"0x%x\\n\", (unsigned long long)user_req, ret);\n+\t}\n+\n+\treturn ret;\n+}\n+\n+\n+int32_t __hot\n+cpt_dequeue_burst(cpt_instance_t *instance, uint16_t cnt,\n+\t\t  void *resp[], uint8_t cc[])\n+{\n+\tstruct cpt_vf *cptvf = (struct cpt_vf *)instance;\n+\tstruct pending_queue *pqueue = &cptvf->pqueue;\n+\tcpt_request_info_t *user_req;\n+\trid_t *rid_e;\n+\tint i, count, pcount;\n+\tuint8_t ret;\n+\n+\tpcount = pqueue->pending_count;\n+\tcount = (cnt > pcount) ? pcount : cnt;\n+\n+\tfor (i = 0; i < count; i++) {\n+\t\trid_e = &pqueue->rid_queue[pqueue->deq_head];\n+\t\tuser_req = (cpt_request_info_t *)(rid_e->rid);\n+\n+\t\tif (likely((i+1) < count))\n+\t\t\trte_prefetch_non_temporal((void *)rid_e[1].rid);\n+\n+\t\tret = check_nb_command_id(user_req, cptvf);\n+\n+\t\tif (unlikely(ret == ERR_REQ_PENDING)) {\n+\t\t\t/* Stop checking for completions */\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\t/* Return completion code and op handle */\n+\t\tcc[i] = (uint8_t)ret;\n+\t\tresp[i] = user_req->op;\n+\t\tPMD_RX_LOG(DEBUG, \"Request %p Op %p completed with code %d\",\n+\t\t\t   user_req, user_req->op, ret);\n+\n+\t\tMOD_INC(pqueue->deq_head, DEFAULT_CMD_QLEN);\n+\t\tpqueue->pending_count -= 1;\n+\t}\n+\n+\treturn i;\n+}\n+\n+uint16_t __hot\n+cpt_queue_full(cpt_instance_t *instance)\n+{\n+\tstruct cpt_vf *cptvf;\n+\tstruct pending_queue *pqueue;\n+\tuint16_t avail;\n+\n+\tcptvf = (struct cpt_vf *)instance;\n+\tpqueue = &cptvf->pqueue;\n+#if defined(ATOMIC_THROTTLING_COUNTER)\n+\tavail = DEFAULT_CMD_QLEN - cpt_pmd_pcount_load(&pqueue->pending_count);\n+\t/* Ask the application to try again later */\n+\tif (avail <= 0)\n+\t\treturn 0;\n+\n+\treturn avail;\n+#else\n+\tavail = DEFAULT_CMD_QLEN - pqueue->pending_count;\n+\t/*\n+\t * This will be NULL if instruction\n+\t * that was sent earlier which this entry was complete\n+\t */\n+\treturn avail;\n+#endif\n+}\ndiff --git a/drivers/crypto/cpt/base/cpt_request_mgr.h b/drivers/crypto/cpt/base/cpt_request_mgr.h\nnew file mode 100644\nindex 0000000..dfa4046\n--- /dev/null\n+++ b/drivers/crypto/cpt/base/cpt_request_mgr.h\n@@ -0,0 +1,75 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2017 Cavium, Inc\n+ */\n+\n+#ifndef __REQUEST_MANGER_H\n+#define __REQUEST_MANGER_H\n+\n+#include \"cpt8xxx_device.h\"\n+\n+#define TIME_IN_RESET_COUNT  5\n+#define COMPLETION_CODE_SIZE 8\n+#define COMPLETION_CODE_INIT 0\n+\n+#define SG_LIST_HDR_SIZE  (8u)\n+#define SG_ENTRY_SIZE sizeof(sg_comp_t)\n+\n+#define AE_CORE_REQ 0\n+#define SE_CORE_REQ 1\n+\n+#define CTRL_DMA_MODE_SGIO\t2\t/* DMA Mode but SGIO is already setup */\n+\n+#define MRS(reg) \\\n+\t({ \\\n+\t uint64_t val; \\\n+\t __asm volatile(\"mrs %0, \" #reg : \"=r\" (val)); \\\n+\t val; \\\n+\t })\n+\n+int calculate_pad(uint8_t *ipad, uint8_t *opad, auth_type_t hash_type,\n+\t      uint8_t *key, uint32_t keylen);\n+\n+typedef union opcode_info {\n+\tuint16_t flags;\n+\tstruct {\n+\t\tuint8_t major;\n+\t\tuint8_t minor;\n+\t} s;\n+} opcode_info_t;\n+\n+typedef struct sglist_comp {\n+\tunion {\n+\t\tuint64_t len;\n+\t\tstruct {\n+\t\t\tuint16_t len[4];\n+\t\t} s;\n+\t} u;\n+\tuint64_t ptr[4];\n+} sg_comp_t;\n+\n+struct cpt_request_info {\n+\t/* fast path fields */\n+\tuint64_t dma_mode\t: 2;\t/**< DMA mode */\n+\tuint64_t se_req\t\t: 1;\t/**< To SE core */\n+\tuint64_t comp_baddr\t: 61;\n+\tvolatile uint64_t *completion_addr;\n+\tvolatile uint64_t *alternate_caddr;\n+\tvoid *op; /** Reference to operation */\n+\tstruct {\n+\t\tuint64_t ei0;\n+\t\tuint64_t ei1;\n+\t\tuint64_t ei2;\n+\t\tuint64_t ei3;\n+\t} ist;\n+\n+\t/* slow path fields */\n+\tuint64_t time_out;\n+\tuint8_t extra_time;\n+#ifdef CPT_DEBUG\n+\tcpt_inst_s_t dbg_inst;\n+#endif\n+\n+};\n+\n+typedef struct cpt_request_info cpt_request_info_t;\n+#endif\n",
    "prefixes": [
        "dpdk-dev",
        "04/16"
    ]
}