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GET /api/patches/40869/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 40869,
    "url": "http://patchwork.dpdk.org/api/patches/40869/?format=api",
    "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/1528476325-15585-9-git-send-email-anoob.joseph@caviumnetworks.com/",
    "project": {
        "id": 1,
        "url": "http://patchwork.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
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        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
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        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1528476325-15585-9-git-send-email-anoob.joseph@caviumnetworks.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1528476325-15585-9-git-send-email-anoob.joseph@caviumnetworks.com",
    "date": "2018-06-08T16:45:17",
    "name": "[dpdk-dev,08/16] crypto/cpt/base: add request prepare API for Kasumi",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "494ae50de08af26396012abd588851ea6034a8e9",
    "submitter": {
        "id": 893,
        "url": "http://patchwork.dpdk.org/api/people/893/?format=api",
        "name": "Anoob Joseph",
        "email": "anoob.joseph@caviumnetworks.com"
    },
    "delegate": {
        "id": 6690,
        "url": "http://patchwork.dpdk.org/api/users/6690/?format=api",
        "username": "akhil",
        "first_name": "akhil",
        "last_name": "goyal",
        "email": "gakhil@marvell.com"
    },
    "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/1528476325-15585-9-git-send-email-anoob.joseph@caviumnetworks.com/mbox/",
    "series": [
        {
            "id": 58,
            "url": "http://patchwork.dpdk.org/api/series/58/?format=api",
            "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=58",
            "date": "2018-06-08T16:45:09",
            "name": "Adding Cavium's crypto device(CPT) driver",
            "version": 1,
            "mbox": "http://patchwork.dpdk.org/series/58/mbox/"
        }
    ],
    "comments": "http://patchwork.dpdk.org/api/patches/40869/comments/",
    "check": "success",
    "checks": "http://patchwork.dpdk.org/api/patches/40869/checks/",
    "tags": {},
    "related": [],
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        "From": "Anoob Joseph <anoob.joseph@caviumnetworks.com>",
        "To": "Akhil Goyal <akhil.goyal@nxp.com>,\n\tPablo de Lara <pablo.de.lara.guarch@intel.com>,\n\tThomas Monjalon <thomas@monjalon.net>",
        "Cc": "Murthy NSSR <Nidadavolu.Murthy@cavium.com>,\n\tAnkur Dwivedi <ankur.dwivedi@cavium.com>,\n\tJerin Jacob <jerin.jacob@caviumnetworks.com>,\n\tNarayana Prasad <narayanaprasad.athreya@caviumnetworks.com>,\n\tNithin Dabilpuram <nithin.dabilpuram@cavium.com>,\n\tRagothaman Jayaraman <Ragothaman.Jayaraman@cavium.com>,\n\tSrisivasubramanian Srinivasan\n\t<Srisivasubramanian.Srinivasan@cavium.com>, dev@dpdk.org",
        "Date": "Fri,  8 Jun 2018 22:15:17 +0530",
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        "Subject": "[dpdk-dev] [PATCH 08/16] crypto/cpt/base: add request prepare API\n\tfor Kasumi",
        "X-BeenThere": "dev@dpdk.org",
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    },
    "content": "From: Murthy NSSR <Nidadavolu.Murthy@cavium.com>\n\nThese functions help in preparing symmetric crypto request\nfor Kasumi of both cipher and auth but not cipher+auth in single\nxform.\n\nSigned-off-by: Ankur Dwivedi <ankur.dwivedi@cavium.com>\nSigned-off-by: Murthy NSSR <Nidadavolu.Murthy@cavium.com>\nSigned-off-by: Nithin Dabilpuram <nithin.dabilpuram@cavium.com>\nSigned-off-by: Ragothaman Jayaraman <Ragothaman.Jayaraman@cavium.com>\nSigned-off-by: Srisivasubramanian Srinivasan <Srisivasubramanian.Srinivasan@cavium.com>\n---\n drivers/crypto/cpt/base/cpt_ops.c | 545 ++++++++++++++++++++++++++++++++++++++\n 1 file changed, 545 insertions(+)",
    "diff": "diff --git a/drivers/crypto/cpt/base/cpt_ops.c b/drivers/crypto/cpt/base/cpt_ops.c\nindex ff7522a..15c3413 100644\n--- a/drivers/crypto/cpt/base/cpt_ops.c\n+++ b/drivers/crypto/cpt/base/cpt_ops.c\n@@ -1933,6 +1933,545 @@ static inline int  __attribute__((always_inline))\n \treturn 0;\n }\n \n+static int\n+cpt_kasumi_enc_prep(uint32_t req_flags,\n+\t\t    uint64_t d_offs,\n+\t\t    uint64_t d_lens,\n+\t\t    fc_params_t *params,\n+\t\t    void *op,\n+\t\t    void **prep_req)\n+{\n+\tuint32_t size;\n+\tint32_t inputlen = 0, outputlen = 0;\n+\tstruct cpt_ctx *cpt_ctx;\n+\tuint32_t mac_len = 0;\n+\tuint8_t i = 0;\n+\tcpt_request_info_t *req;\n+\tbuf_ptr_t *buf_p;\n+\tuint32_t encr_offset, auth_offset;\n+\tuint32_t encr_data_len, auth_data_len;\n+\tint flags, m_size;\n+\tuint8_t *iv_s, *iv_d, iv_len = 8;\n+\tuint8_t dir = 0;\n+\tvoid *m_vaddr, *c_vaddr;\n+\tuint64_t m_dma, c_dma;\n+\tuint64_t *offset_vaddr, offset_dma;\n+\tvq_cmd_word0_t vq_cmd_w0;\n+\tvq_cmd_word3_t vq_cmd_w3;\n+\topcode_info_t opcode;\n+\tuint8_t *in_buffer;\n+\tuint32_t g_size_bytes, s_size_bytes;\n+\tuint64_t dptr_dma, rptr_dma;\n+\tsg_comp_t *gather_comp;\n+\tsg_comp_t *scatter_comp;\n+\n+\tbuf_p = &params->meta_buf;\n+#ifdef CPTVF_STRICT_PARAM_CHECK\n+\tif (!params || !buf_p->vaddr || !buf_p->size)\n+\t\treturn ERR_BAD_INPUT_ARG;\n+#endif\n+\tm_vaddr = buf_p->vaddr;\n+\tm_dma = buf_p->dma_addr;\n+\tm_size = buf_p->size;\n+\n+\tencr_offset = ENCR_OFFSET(d_offs) / 8;\n+\tauth_offset = AUTH_OFFSET(d_offs) / 8;\n+\tencr_data_len = ENCR_DLEN(d_lens);\n+\tauth_data_len = AUTH_DLEN(d_lens);\n+\n+\tcpt_ctx = params->ctx_buf.vaddr;\n+\tflags = cpt_ctx->zsk_flags;\n+\tmac_len = cpt_ctx->mac_len;\n+\n+#ifdef CPTVF_STRICT_PARAM_CHECK\n+\tif (flags == 0x0) {\n+\t\t/* F8 Mode */\n+\t\tif (auth_offset || auth_data_len)\n+\t\t\treturn ERR_BAD_INPUT_ARG;\n+\n+\t\tif (!params->iv_buf)\n+\t\t\treturn ERR_BAD_INPUT_ARG;\n+\t} else if (flags == 0x1) {\n+\t\t/* F9 mode */\n+\t\tif (encr_offset || encr_data_len)\n+\t\t\treturn ERR_BAD_INPUT_ARG;\n+\n+\t\tif (!params->auth_iv_buf)\n+\t\t\treturn ERR_BAD_INPUT_ARG;\n+\t} else {\n+\t\treturn ERR_EIO;\n+\t}\n+#endif\n+\tif (flags == 0x0)\n+\t\tiv_s = params->iv_buf;\n+\telse\n+\t\tiv_s = params->auth_iv_buf;\n+\n+\tdir = iv_s[8] & 0x1;\n+\n+\t/*\n+\t * Save initial space that followed app data for completion code &\n+\t * alternate completion code to fall in same cache line as app data\n+\t */\n+\tm_vaddr = (uint8_t *)m_vaddr + COMPLETION_CODE_SIZE;\n+\tm_dma += COMPLETION_CODE_SIZE;\n+\tsize = (uint8_t *)RTE_PTR_ALIGN((uint8_t *)m_vaddr, 16) -\n+\t\t(uint8_t *)m_vaddr;\n+\n+\tc_vaddr = (uint8_t *)m_vaddr + size;\n+\tc_dma = m_dma + size;\n+\tsize += sizeof(cpt_res_s_t);\n+\n+\tm_vaddr = (uint8_t *)m_vaddr + size;\n+\tm_dma += size;\n+\tm_size -= size;\n+\n+\t/* Reserve memory for cpt request info */\n+\treq = m_vaddr;\n+\n+\tsize = sizeof(cpt_request_info_t);\n+\tm_vaddr = (uint8_t *)m_vaddr + size;\n+\tm_dma += size;\n+\tm_size -= size;\n+\n+\t/* Initialising ctrl and opcode\n+\t * fields for cpt request\n+\t */\n+\n+\treq->se_req = SE_CORE_REQ;\n+\treq->dma_mode = CTRL_DMA_MODE_SGIO;\n+\n+\topcode.s.major = MAJOR_OP_KASUMI | DMA_MODE;\n+\n+\t/* indicates ECB/CBC, direction, ctx from cptr, iv from dptr */\n+\topcode.s.minor = ((1 << 6) | (cpt_ctx->k_ecb << 5) |\n+\t\t\t  (dir << 4) | (0 << 3) | (flags & 0x7));\n+\n+\t/*\n+\t * GP op header, lengths are expected in bits.\n+\t */\n+\tvq_cmd_w0.u64 = 0;\n+\tvq_cmd_w0.s.param1 = htobe16(encr_data_len);\n+\tvq_cmd_w0.s.param2 = htobe16(auth_data_len);\n+\tvq_cmd_w0.s.opcode = htobe16(opcode.flags);\n+\n+\t/* consider iv len */\n+\tif (flags == 0x0) {\n+\t\tencr_offset += iv_len;\n+\t\tauth_offset += iv_len;\n+\t}\n+\n+\t/* save space for offset ctrl and iv */\n+\toffset_vaddr = m_vaddr;\n+\toffset_dma = m_dma;\n+\n+\tm_vaddr = (uint8_t *)m_vaddr + OFF_CTRL_LEN + iv_len;\n+\tm_dma += OFF_CTRL_LEN + iv_len;\n+\tm_size -= OFF_CTRL_LEN + iv_len;\n+\n+\t/* DPTR has SG list */\n+\tin_buffer = m_vaddr;\n+\tdptr_dma = m_dma;\n+\n+\t((uint16_t *)in_buffer)[0] = 0;\n+\t((uint16_t *)in_buffer)[1] = 0;\n+\n+\t/* TODO Add error check if space will be sufficient */\n+\tgather_comp = (sg_comp_t *)((uint8_t *)m_vaddr + 8);\n+\n+\t/*\n+\t * Input Gather List\n+\t */\n+\ti = 0;\n+\n+\t/* Offset control word followed by iv */\n+\n+\tif (flags == 0x0) {\n+\t\tinputlen = encr_offset +\n+\t\t\t(RTE_ALIGN(encr_data_len, 8) / 8);\n+\t\toutputlen = inputlen;\n+\t\t/* iv offset is 0 */\n+\t\t*offset_vaddr = htobe64((uint64_t)encr_offset << 16);\n+\t} else {\n+\t\tinputlen = auth_offset +\n+\t\t\t(RTE_ALIGN(auth_data_len, 8) / 8);\n+\t\toutputlen = mac_len;\n+\t\t/* iv offset is 0 */\n+\t\t*offset_vaddr = htobe64((uint64_t)auth_offset);\n+\t}\n+\n+\ti = fill_sg_comp(gather_comp, i, offset_dma,\n+\t\t\t offset_vaddr, OFF_CTRL_LEN + iv_len);\n+\n+\t/* IV */\n+\tiv_d = (uint8_t *)offset_vaddr + OFF_CTRL_LEN;\n+\tmemcpy(iv_d, iv_s, iv_len);\n+\n+\t/* input data */\n+\tsize = inputlen - iv_len;\n+\tif (size) {\n+#ifdef CPTVF_STRICT_PARAM_CHECK\n+\t\tif (!params->src_iov)\n+\t\t\treturn ERR_BAD_INPUT_ARG;\n+#endif\n+\t\ti = fill_sg_comp_from_iov(gather_comp, i,\n+\t\t\t\t\t  params->src_iov, 0,\n+\t\t\t\t\t  &size, NULL, 0);\n+\n+\t\tif (size)\n+\t\t\treturn ERR_BAD_INPUT_ARG;\n+\t}\n+\t((uint16_t *)in_buffer)[2] = htobe16(i);\n+\tg_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);\n+\n+\t/*\n+\t * Output Scatter List\n+\t */\n+\n+\ti = 0;\n+\tscatter_comp =\n+\t\t(sg_comp_t *)((uint8_t *)gather_comp + g_size_bytes);\n+\n+\tif (flags == 0x1) {\n+\t\t/* IV in SLIST only for F8 */\n+\t\tiv_len = 0;\n+\t}\n+\n+\t/* IV */\n+\tif (iv_len) {\n+\n+\t\ti = fill_sg_comp(scatter_comp, i,\n+\t\t\t\t offset_dma + OFF_CTRL_LEN,\n+\t\t\t\t (uint8_t *)offset_vaddr + OFF_CTRL_LEN,\n+\t\t\t\t iv_len);\n+\t}\n+\n+\t/* Add output data */\n+\tif (req_flags & VALID_MAC_BUF) {\n+\t\tsize = outputlen - iv_len - mac_len;\n+\t\tif (size) {\n+#ifdef CPTVF_STRICT_PARAM_CHECK\n+\t\t\tif (!params->dst_iov)\n+\t\t\t\treturn ERR_BAD_INPUT_ARG;\n+#endif\n+\t\t\ti = fill_sg_comp_from_iov(scatter_comp, i,\n+\t\t\t\t\t\t  params->dst_iov, 0,\n+\t\t\t\t\t\t  &size, NULL, 0);\n+\n+\t\t\tif (size)\n+\t\t\t\treturn ERR_BAD_INPUT_ARG;\n+\t\t}\n+\n+\t\t/* mac data */\n+\t\tif (mac_len) {\n+\t\t\ti = fill_sg_comp_from_buf(scatter_comp, i,\n+\t\t\t\t\t\t  &params->mac_buf);\n+\t\t}\n+\t} else {\n+\t\t/* Output including mac */\n+\t\tsize = outputlen - iv_len;\n+\t\tif (size) {\n+#ifdef CPTVF_STRICT_PARAM_CHECK\n+\t\t\tif (!params->dst_iov)\n+\t\t\t\treturn ERR_BAD_INPUT_ARG;\n+#endif\n+\t\t\ti = fill_sg_comp_from_iov(scatter_comp, i,\n+\t\t\t\t\t\t  params->dst_iov, 0,\n+\t\t\t\t\t\t  &size, NULL, 0);\n+\n+\t\t\tif (size)\n+\t\t\t\treturn ERR_BAD_INPUT_ARG;\n+\t\t}\n+\t}\n+\t((uint16_t *)in_buffer)[3] = htobe16(i);\n+\ts_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);\n+\n+\tsize = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE;\n+\n+\t/* This is DPTR len incase of SG mode */\n+\tvq_cmd_w0.s.dlen = htobe16(size);\n+\n+\tm_vaddr = (uint8_t *)m_vaddr + size;\n+\tm_dma += size;\n+\tm_size -= size;\n+\n+\t/* cpt alternate completion address saved earlier */\n+\treq->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8);\n+\t*req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT);\n+\trptr_dma = c_dma - 8;\n+\n+\treq->ist.ei1 = dptr_dma;\n+\treq->ist.ei2 = rptr_dma;\n+\n+\t/* First 16-bit swap then 64-bit swap */\n+\t/* TODO: HACK: Reverse the vq_cmd and cpt_req bit field definitions\n+\t * to eliminate all the swapping\n+\t */\n+\tvq_cmd_w0.u64 = htobe64(vq_cmd_w0.u64);\n+\n+\t/* vq command w3 */\n+\tvq_cmd_w3.u64 = 0;\n+\tvq_cmd_w3.s.grp = 0;\n+\tvq_cmd_w3.s.cptr = params->ctx_buf.dma_addr +\n+\t\toffsetof(struct cpt_ctx, k_ctx);\n+\n+\t/* 16 byte aligned cpt res address */\n+\treq->completion_addr = (uint64_t *)((uint8_t *)c_vaddr);\n+\t*req->completion_addr = COMPLETION_CODE_INIT;\n+\treq->comp_baddr  = c_dma;\n+\n+\t/* Fill microcode part of instruction */\n+\treq->ist.ei0 = vq_cmd_w0.u64;\n+\treq->ist.ei3 = vq_cmd_w3.u64;\n+\n+\treq->op = op;\n+\n+#ifdef CPTVF_STRICT_PARAM_CHECK\n+\tif (!(m_size >= 0)) {\n+\t\tPMD_TX_LOG(ERR, \"!!! Buffer Overflow %d\\n\",\n+\t\t\t   m_size);\n+\t\tabort();\n+\t}\n+#endif\n+\t*prep_req = req;\n+\treturn 0;\n+}\n+\n+\n+static inline int\n+cpt_kasumi_dec_prep(uint32_t req_flags,\n+\t\t    uint64_t d_offs,\n+\t\t    uint64_t d_lens,\n+\t\t    fc_params_t *params,\n+\t\t    void *op,\n+\t\t    void **prep_req)\n+{\n+\tuint32_t size;\n+\tint32_t inputlen = 0, outputlen;\n+\tstruct cpt_ctx *cpt_ctx;\n+\tuint8_t i = 0, iv_len = 8;\n+\tcpt_request_info_t *req;\n+\tbuf_ptr_t *buf_p;\n+\tuint32_t encr_offset;\n+\tuint32_t encr_data_len;\n+\tint flags, m_size;\n+\tuint8_t dir = 0;\n+\tvoid *m_vaddr, *c_vaddr;\n+\tuint64_t m_dma, c_dma;\n+\tuint64_t *offset_vaddr, offset_dma;\n+\tvq_cmd_word0_t vq_cmd_w0;\n+\tvq_cmd_word3_t vq_cmd_w3;\n+\topcode_info_t opcode;\n+\tuint8_t *in_buffer;\n+\tuint32_t g_size_bytes, s_size_bytes;\n+\tuint64_t dptr_dma, rptr_dma;\n+\tsg_comp_t *gather_comp;\n+\tsg_comp_t *scatter_comp;\n+\n+\t(void)req_flags;\n+\tbuf_p = &params->meta_buf;\n+#ifdef CPTVF_STRICT_PARAM_CHECK\n+\tif (!params || !buf_p->vaddr || !buf_p->size)\n+\t\treturn ERR_BAD_INPUT_ARG;\n+#endif\n+\tm_vaddr = buf_p->vaddr;\n+\tm_dma = buf_p->dma_addr;\n+\tm_size = buf_p->size;\n+\n+\tencr_offset = ENCR_OFFSET(d_offs) / 8;\n+\tencr_data_len = ENCR_DLEN(d_lens);\n+\n+\tcpt_ctx = params->ctx_buf.vaddr;\n+\tflags = cpt_ctx->zsk_flags;\n+#ifdef CPTVF_STRICT_PARAM_CHECK\n+\tif (!params->iv_buf)\n+\t\treturn ERR_BAD_INPUT_ARG;\n+#endif\n+#ifdef CPTVF_STRICT_PARAM_CHECK\n+\tif (flags != 0) {\n+\t\t/* Dec not supported for F9 */\n+\t\treturn ERR_BAD_INPUT_ARG;\n+\t}\n+#endif\n+\t/*\n+\t * Save initial space that followed app data for completion code &\n+\t * alternate completion code to fall in same cache line as app data\n+\t */\n+\tm_vaddr = (uint8_t *)m_vaddr + COMPLETION_CODE_SIZE;\n+\tm_dma += COMPLETION_CODE_SIZE;\n+\tsize = (uint8_t *)RTE_PTR_ALIGN((uint8_t *)m_vaddr, 16) -\n+\t\t(uint8_t *)m_vaddr;\n+\n+\tc_vaddr = (uint8_t *)m_vaddr + size;\n+\tc_dma = m_dma + size;\n+\tsize += sizeof(cpt_res_s_t);\n+\n+\tm_vaddr = (uint8_t *)m_vaddr + size;\n+\tm_dma += size;\n+\tm_size -= size;\n+\n+\t/* Reserve memory for cpt request info */\n+\treq = m_vaddr;\n+\n+\tsize = sizeof(cpt_request_info_t);\n+\tm_vaddr = (uint8_t *)m_vaddr + size;\n+\tm_dma += size;\n+\tm_size -= size;\n+\n+\t/* Initialising ctrl and opcode\n+\t * fields for cpt req\n+\t */\n+\n+\treq->se_req = SE_CORE_REQ;\n+\treq->dma_mode = CTRL_DMA_MODE_SGIO;\n+\n+\topcode.s.major = MAJOR_OP_KASUMI | DMA_MODE;\n+\n+\t/* indicates ECB/CBC, direction, ctx from cptr, iv from dptr */\n+\topcode.s.minor = ((1 << 6) | (cpt_ctx->k_ecb << 5) |\n+\t\t\t  (dir << 4) | (0 << 3) | (flags & 0x7));\n+\n+\t/*\n+\t * GP op header, lengths are expected in bits.\n+\t */\n+\tvq_cmd_w0.u64 = 0;\n+\tvq_cmd_w0.s.param1 = htobe16(encr_data_len);\n+\tvq_cmd_w0.s.opcode = htobe16(opcode.flags);\n+\n+\t/* consider iv len */\n+\tencr_offset += iv_len;\n+\n+\tinputlen = iv_len + (RTE_ALIGN(encr_data_len, 8) / 8);\n+\toutputlen = inputlen;\n+\n+\t/* save space for offset ctrl & iv */\n+\toffset_vaddr = m_vaddr;\n+\toffset_dma = m_dma;\n+\n+\tm_vaddr = (uint8_t *)m_vaddr + OFF_CTRL_LEN + iv_len;\n+\tm_dma += OFF_CTRL_LEN + iv_len;\n+\tm_size -= OFF_CTRL_LEN + iv_len;\n+\n+\t/* DPTR has SG list */\n+\tin_buffer = m_vaddr;\n+\tdptr_dma = m_dma;\n+\n+\t((uint16_t *)in_buffer)[0] = 0;\n+\t((uint16_t *)in_buffer)[1] = 0;\n+\n+\t/* TODO Add error check if space will be sufficient */\n+\tgather_comp = (sg_comp_t *)((uint8_t *)m_vaddr + 8);\n+\n+\t/*\n+\t * Input Gather List\n+\t */\n+\ti = 0;\n+\n+\t/* Offset control word followed by iv */\n+\t*offset_vaddr = htobe64((uint64_t)encr_offset << 16);\n+\n+\ti = fill_sg_comp(gather_comp, i, offset_dma, offset_vaddr,\n+\t\t\t OFF_CTRL_LEN + iv_len);\n+\n+\n+\t/* IV */\n+\tmemcpy((uint8_t *)offset_vaddr + OFF_CTRL_LEN,\n+\t       params->iv_buf, iv_len);\n+\n+\t/* Add input data */\n+\tsize = inputlen - iv_len;\n+\tif (size) {\n+#ifdef CPTVF_STRICT_PARAM_CHECK\n+\t\tif (!params->src_iov)\n+\t\t\treturn ERR_BAD_INPUT_ARG;\n+#endif\n+\t\ti = fill_sg_comp_from_iov(gather_comp, i,\n+\t\t\t\t\t  params->src_iov,\n+\t\t\t\t\t  0, &size, NULL, 0);\n+\t\tif (size)\n+\t\t\treturn ERR_BAD_INPUT_ARG;\n+\t}\n+\t((uint16_t *)in_buffer)[2] = htobe16(i);\n+\tg_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);\n+\n+\t/*\n+\t * Output Scatter List\n+\t */\n+\n+\ti = 0;\n+\tscatter_comp =\n+\t\t(sg_comp_t *)((uint8_t *)gather_comp + g_size_bytes);\n+\n+\t/* IV */\n+\ti = fill_sg_comp(scatter_comp, i,\n+\t\t\t offset_dma + OFF_CTRL_LEN,\n+\t\t\t (uint8_t *)offset_vaddr + OFF_CTRL_LEN,\n+\t\t\t iv_len);\n+\n+\t/* Add output data */\n+\tsize = outputlen - iv_len;\n+\tif (size) {\n+#ifdef CPTVF_STRICT_PARAM_CHECK\n+\t\tif (!params->dst_iov)\n+\t\t\treturn ERR_BAD_INPUT_ARG;\n+#endif\n+\t\ti = fill_sg_comp_from_iov(scatter_comp, i,\n+\t\t\t\t\t  params->dst_iov, 0,\n+\t\t\t\t\t  &size, NULL, 0);\n+\t\tif (size)\n+\t\t\treturn ERR_BAD_INPUT_ARG;\n+\t}\n+\t((uint16_t *)in_buffer)[3] = htobe16(i);\n+\ts_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);\n+\n+\tsize = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE;\n+\n+\t/* This is DPTR len incase of SG mode */\n+\tvq_cmd_w0.s.dlen = htobe16(size);\n+\n+\tm_vaddr = (uint8_t *)m_vaddr + size;\n+\tm_dma += size;\n+\tm_size -= size;\n+\n+\t/* cpt alternate completion address saved earlier */\n+\treq->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8);\n+\t*req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT);\n+\trptr_dma = c_dma - 8;\n+\n+\treq->ist.ei1 = dptr_dma;\n+\treq->ist.ei2 = rptr_dma;\n+\n+\t/* First 16-bit swap then 64-bit swap */\n+\t/* TODO: HACK: Reverse the vq_cmd and cpt_req bit field definitions\n+\t * to eliminate all the swapping\n+\t */\n+\tvq_cmd_w0.u64 = htobe64(vq_cmd_w0.u64);\n+\n+\t/* vq command w3 */\n+\tvq_cmd_w3.u64 = 0;\n+\tvq_cmd_w3.s.grp = 0;\n+\tvq_cmd_w3.s.cptr = params->ctx_buf.dma_addr +\n+\t\toffsetof(struct cpt_ctx, k_ctx);\n+\n+\t/* 16 byte aligned cpt res address */\n+\treq->completion_addr = (uint64_t *)((uint8_t *)c_vaddr);\n+\t*req->completion_addr = COMPLETION_CODE_INIT;\n+\treq->comp_baddr  = c_dma;\n+\n+\t/* Fill microcode part of instruction */\n+\treq->ist.ei0 = vq_cmd_w0.u64;\n+\treq->ist.ei3 = vq_cmd_w3.u64;\n+\n+\treq->op = op;\n+\n+#ifdef CPTVF_STRICT_PARAM_CHECK\n+\tif (!(m_size >= 0))\n+\t\tabort();\n+#endif\n+\t*prep_req = req;\n+\treturn 0;\n+}\n+\n void *\n cpt_fc_dec_hmac_prep(uint32_t flags,\n \t\t     uint64_t d_offs,\n@@ -1953,6 +2492,9 @@ static inline int  __attribute__((always_inline))\n \t} else if (fc_type == ZUC_SNOW3G) {\n \t\tret = cpt_zuc_snow3g_dec_prep(flags, d_offs, d_lens,\n \t\t\t\t\t      fc_params, op, &prep_req);\n+\t} else if (fc_type == KASUMI) {\n+\t\tret = cpt_kasumi_dec_prep(flags, d_offs, d_lens,\n+\t\t\t\t\t  fc_params, op, &prep_req);\n \t} else {\n \t\t/*\n \t\t * For AUTH_ONLY case,\n@@ -1986,6 +2528,9 @@ static inline int  __attribute__((always_inline))\n \t} else if (fc_type == ZUC_SNOW3G) {\n \t\tret = cpt_zuc_snow3g_enc_prep(flags, d_offs, d_lens,\n \t\t\t\t\t      fc_params, op, &prep_req);\n+\t} else if (fc_type == KASUMI) {\n+\t\tret = cpt_kasumi_enc_prep(flags, d_offs, d_lens,\n+\t\t\t\t\t  fc_params, op, &prep_req);\n \t} else {\n \t\tret = ERR_EIO;\n \t}\n",
    "prefixes": [
        "dpdk-dev",
        "08/16"
    ]
}