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GET /api/patches/40926/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 40926,
    "url": "http://patchwork.dpdk.org/api/patches/40926/?format=api",
    "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/d5adad26fbf4a702e8de9ade119cd40e2c5eee9c.1528469677.git.rahul.lakkireddy@chelsio.com/",
    "project": {
        "id": 1,
        "url": "http://patchwork.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<d5adad26fbf4a702e8de9ade119cd40e2c5eee9c.1528469677.git.rahul.lakkireddy@chelsio.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/d5adad26fbf4a702e8de9ade119cd40e2c5eee9c.1528469677.git.rahul.lakkireddy@chelsio.com",
    "date": "2018-06-08T17:58:11",
    "name": "[dpdk-dev,1/7] net/cxgbe: query firmware for filter resources",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": true,
    "hash": "21b711d0c4962bc881761776824d3db51ee4b28c",
    "submitter": {
        "id": 241,
        "url": "http://patchwork.dpdk.org/api/people/241/?format=api",
        "name": "Rahul Lakkireddy",
        "email": "rahul.lakkireddy@chelsio.com"
    },
    "delegate": {
        "id": 319,
        "url": "http://patchwork.dpdk.org/api/users/319/?format=api",
        "username": "fyigit",
        "first_name": "Ferruh",
        "last_name": "Yigit",
        "email": "ferruh.yigit@amd.com"
    },
    "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/d5adad26fbf4a702e8de9ade119cd40e2c5eee9c.1528469677.git.rahul.lakkireddy@chelsio.com/mbox/",
    "series": [
        {
            "id": 63,
            "url": "http://patchwork.dpdk.org/api/series/63/?format=api",
            "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=63",
            "date": "2018-06-08T17:58:10",
            "name": "cxgbe: add support to offload flows via rte_flow",
            "version": 1,
            "mbox": "http://patchwork.dpdk.org/series/63/mbox/"
        }
    ],
    "comments": "http://patchwork.dpdk.org/api/patches/40926/comments/",
    "check": "success",
    "checks": "http://patchwork.dpdk.org/api/patches/40926/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 969471CFF8;\n\tFri,  8 Jun 2018 19:59:12 +0200 (CEST)",
            "from stargate.chelsio.com (stargate.chelsio.com [12.32.117.8])\n\tby dpdk.org (Postfix) with ESMTP id CC7C11CFF7\n\tfor <dev@dpdk.org>; Fri,  8 Jun 2018 19:59:11 +0200 (CEST)",
            "from localhost (scalar.blr.asicdesigners.com [10.193.185.94])\n\tby stargate.chelsio.com (8.13.8/8.13.8) with ESMTP id w58Hx8FF017288; \n\tFri, 8 Jun 2018 10:59:08 -0700"
        ],
        "From": "Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>",
        "To": "dev@dpdk.org",
        "Cc": "shaguna@chelsio.com, kumaras@chelsio.com, indranil@chelsio.com,\n\tnirranjan@chelsio.com",
        "Date": "Fri,  8 Jun 2018 23:28:11 +0530",
        "Message-Id": "<d5adad26fbf4a702e8de9ade119cd40e2c5eee9c.1528469677.git.rahul.lakkireddy@chelsio.com>",
        "X-Mailer": "git-send-email 2.5.3",
        "In-Reply-To": [
            "<cover.1528469677.git.rahul.lakkireddy@chelsio.com>",
            "<cover.1528469677.git.rahul.lakkireddy@chelsio.com>"
        ],
        "References": [
            "<cover.1528469677.git.rahul.lakkireddy@chelsio.com>",
            "<cover.1528469677.git.rahul.lakkireddy@chelsio.com>"
        ],
        "Subject": "[dpdk-dev] [PATCH 1/7] net/cxgbe: query firmware for filter\n\tresources",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://dpdk.org/ml/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "From: Shagun Agrawal <shaguna@chelsio.com>\n\nFetch available filter resources from firmware and allocate table for\nbook-keeping and managing filters in hardware. Also define the hardware\nfilter specification (ch_filter_specification) used to describe each\nfilter rule.\n\nSigned-off-by: Shagun Agrawal <shaguna@chelsio.com>\nSigned-off-by: Kumar Sanghvi <kumaras@chelsio.com>\nSigned-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>\n---\n drivers/net/cxgbe/base/adapter.h        |   4 ++\n drivers/net/cxgbe/base/t4fw_interface.h |   6 ++\n drivers/net/cxgbe/cxgbe_filter.h        |  97 +++++++++++++++++++++++++++++\n drivers/net/cxgbe/cxgbe_main.c          | 106 ++++++++++++++++++++++++++++++++\n drivers/net/cxgbe/cxgbe_ofld.h          |  27 ++++++++\n 5 files changed, 240 insertions(+)\n create mode 100644 drivers/net/cxgbe/cxgbe_filter.h\n create mode 100644 drivers/net/cxgbe/cxgbe_ofld.h",
    "diff": "diff --git a/drivers/net/cxgbe/base/adapter.h b/drivers/net/cxgbe/base/adapter.h\nindex 55cb2e91c..1a0f96e40 100644\n--- a/drivers/net/cxgbe/base/adapter.h\n+++ b/drivers/net/cxgbe/base/adapter.h\n@@ -11,9 +11,11 @@\n #include <rte_bus_pci.h>\n #include <rte_mbuf.h>\n #include <rte_io.h>\n+#include <rte_ethdev.h>\n \n #include \"cxgbe_compat.h\"\n #include \"t4_regs_values.h\"\n+#include \"cxgbe_ofld.h\"\n \n enum {\n \tMAX_ETH_QSETS = 64,           /* # of Ethernet Tx/Rx queue sets */\n@@ -306,6 +308,8 @@ struct adapter {\n \tunsigned int vpd_flag;\n \n \tint use_unpacked_mode; /* unpacked rx mode state */\n+\n+\tstruct tid_info tids;     /* Info used to access TID related tables */\n };\n \n /**\ndiff --git a/drivers/net/cxgbe/base/t4fw_interface.h b/drivers/net/cxgbe/base/t4fw_interface.h\nindex 852e8f3c7..95b2aec48 100644\n--- a/drivers/net/cxgbe/base/t4fw_interface.h\n+++ b/drivers/net/cxgbe/base/t4fw_interface.h\n@@ -489,6 +489,10 @@ enum fw_params_mnem {\n enum fw_params_param_dev {\n \tFW_PARAMS_PARAM_DEV_CCLK\t= 0x00, /* chip core clock in khz */\n \tFW_PARAMS_PARAM_DEV_PORTVEC\t= 0x01, /* the port vector */\n+\tFW_PARAMS_PARAM_DEV_NTID        = 0x02, /* reads the number of TIDs\n+\t\t\t\t\t\t * allocated by the device's\n+\t\t\t\t\t\t * Lookup Engine\n+\t\t\t\t\t\t */\n \tFW_PARAMS_PARAM_DEV_FWREV\t= 0x0B, /* fw version */\n \tFW_PARAMS_PARAM_DEV_TPREV\t= 0x0C, /* tp version */\n \tFW_PARAMS_PARAM_DEV_ULPTX_MEMWRITE_DSGL = 0x17,\n@@ -498,6 +502,8 @@ enum fw_params_param_dev {\n  * physical and virtual function parameters\n  */\n enum fw_params_param_pfvf {\n+\tFW_PARAMS_PARAM_PFVF_FILTER_START = 0x05,\n+\tFW_PARAMS_PARAM_PFVF_FILTER_END = 0x06,\n \tFW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31,\n \tFW_PARAMS_PARAM_PFVF_PORT_CAPS32 = 0x3A\n };\ndiff --git a/drivers/net/cxgbe/cxgbe_filter.h b/drivers/net/cxgbe/cxgbe_filter.h\nnew file mode 100644\nindex 000000000..d69c79e80\n--- /dev/null\n+++ b/drivers/net/cxgbe/cxgbe_filter.h\n@@ -0,0 +1,97 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2014-2018 Chelsio Communications.\n+ * All rights reserved.\n+ */\n+\n+#ifndef _CXGBE_FILTER_H_\n+#define _CXGBE_FILTER_H_\n+\n+#include \"t4_msg.h\"\n+/*\n+ * Defined bit width of user definable filter tuples\n+ */\n+#define ETHTYPE_BITWIDTH 16\n+#define FRAG_BITWIDTH 1\n+#define MACIDX_BITWIDTH 9\n+#define FCOE_BITWIDTH 1\n+#define IPORT_BITWIDTH 3\n+#define MATCHTYPE_BITWIDTH 3\n+#define PROTO_BITWIDTH 8\n+#define TOS_BITWIDTH 8\n+#define PF_BITWIDTH 8\n+#define VF_BITWIDTH 8\n+#define IVLAN_BITWIDTH 16\n+#define OVLAN_BITWIDTH 16\n+\n+/*\n+ * Filter matching rules.  These consist of a set of ingress packet field\n+ * (value, mask) tuples.  The associated ingress packet field matches the\n+ * tuple when ((field & mask) == value).  (Thus a wildcard \"don't care\" field\n+ * rule can be constructed by specifying a tuple of (0, 0).)  A filter rule\n+ * matches an ingress packet when all of the individual individual field\n+ * matching rules are true.\n+ *\n+ * Partial field masks are always valid, however, while it may be easy to\n+ * understand their meanings for some fields (e.g. IP address to match a\n+ * subnet), for others making sensible partial masks is less intuitive (e.g.\n+ * MPS match type) ...\n+ */\n+struct ch_filter_tuple {\n+\t/*\n+\t * Compressed header matching field rules.  The TP_VLAN_PRI_MAP\n+\t * register selects which of these fields will participate in the\n+\t * filter match rules -- up to a maximum of 36 bits.  Because\n+\t * TP_VLAN_PRI_MAP is a global register, all filters must use the same\n+\t * set of fields.\n+\t */\n+\tuint32_t ethtype:ETHTYPE_BITWIDTH;\t/* Ethernet type */\n+\tuint32_t frag:FRAG_BITWIDTH;\t\t/* IP fragmentation header */\n+\tuint32_t ivlan_vld:1;\t\t\t/* inner VLAN valid */\n+\tuint32_t ovlan_vld:1;\t\t\t/* outer VLAN valid */\n+\tuint32_t pfvf_vld:1;\t\t\t/* PF/VF valid */\n+\tuint32_t macidx:MACIDX_BITWIDTH;\t/* exact match MAC index */\n+\tuint32_t fcoe:FCOE_BITWIDTH;\t\t/* FCoE packet */\n+\tuint32_t iport:IPORT_BITWIDTH;\t\t/* ingress port */\n+\tuint32_t matchtype:MATCHTYPE_BITWIDTH;\t/* MPS match type */\n+\tuint32_t proto:PROTO_BITWIDTH;\t\t/* protocol type */\n+\tuint32_t tos:TOS_BITWIDTH;\t\t/* TOS/Traffic Type */\n+\tuint32_t pf:PF_BITWIDTH;\t\t/* PCI-E PF ID */\n+\tuint32_t vf:VF_BITWIDTH;\t\t/* PCI-E VF ID */\n+\tuint32_t ivlan:IVLAN_BITWIDTH;\t\t/* inner VLAN */\n+\tuint32_t ovlan:OVLAN_BITWIDTH;\t\t/* outer VLAN */\n+\n+\t/*\n+\t * Uncompressed header matching field rules.  These are always\n+\t * available for field rules.\n+\t */\n+\tuint8_t lip[16];\t/* local IP address (IPv4 in [3:0]) */\n+\tuint8_t fip[16];\t/* foreign IP address (IPv4 in [3:0]) */\n+\tuint16_t lport;\t\t/* local port */\n+\tuint16_t fport;\t\t/* foreign port */\n+\n+\t/* reservations for future additions */\n+\tuint8_t rsvd[12];\n+};\n+\n+/*\n+ * Filter specification\n+ */\n+struct ch_filter_specification {\n+\t/* Filter rule value/mask pairs. */\n+\tstruct ch_filter_tuple val;\n+\tstruct ch_filter_tuple mask;\n+};\n+\n+/*\n+ * Host shadow copy of ingress filter entry.  This is in host native format\n+ * and doesn't match the ordering or bit order, etc. of the hardware or the\n+ * firmware command.\n+ */\n+struct filter_entry {\n+\t/*\n+\t * The filter itself.\n+\t */\n+\tstruct ch_filter_specification fs;\n+};\n+\n+#endif /* _CXGBE_FILTER_H_ */\ndiff --git a/drivers/net/cxgbe/cxgbe_main.c b/drivers/net/cxgbe/cxgbe_main.c\nindex 54eb23dfb..9880257d2 100644\n--- a/drivers/net/cxgbe/cxgbe_main.c\n+++ b/drivers/net/cxgbe/cxgbe_main.c\n@@ -38,6 +38,22 @@\n #include \"t4_msg.h\"\n #include \"cxgbe.h\"\n \n+/**\n+ * Allocate a chunk of memory. The allocated memory is cleared.\n+ */\n+void *t4_alloc_mem(size_t size)\n+{\n+\treturn rte_zmalloc(NULL, size, 0);\n+}\n+\n+/**\n+ * Free memory allocated through t4_alloc_mem().\n+ */\n+void t4_free_mem(void *addr)\n+{\n+\trte_free(addr);\n+}\n+\n /*\n  * Response queue handler for the FW event queue.\n  */\n@@ -169,6 +185,59 @@ int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us,\n \treturn 0;\n }\n \n+/**\n+ * Free TID tables.\n+ */\n+static void tid_free(struct tid_info *t)\n+{\n+\tif (t->tid_tab) {\n+\t\tif (t->ftid_bmap)\n+\t\t\trte_bitmap_free(t->ftid_bmap);\n+\n+\t\tif (t->ftid_bmap_array)\n+\t\t\tt4_os_free(t->ftid_bmap_array);\n+\n+\t\tt4_os_free(t->tid_tab);\n+\t}\n+\n+\tmemset(t, 0, sizeof(struct tid_info));\n+}\n+\n+/**\n+ * Allocate and initialize the TID tables.  Returns 0 on success.\n+ */\n+static int tid_init(struct tid_info *t)\n+{\n+\tsize_t size;\n+\tunsigned int ftid_bmap_size;\n+\tunsigned int max_ftids = t->nftids;\n+\n+\tftid_bmap_size = rte_bitmap_get_memory_footprint(t->nftids);\n+\tsize = t->ntids * sizeof(*t->tid_tab) +\n+\t\tmax_ftids * sizeof(*t->ftid_tab);\n+\n+\tt->tid_tab = t4_os_alloc(size);\n+\tif (!t->tid_tab)\n+\t\treturn -ENOMEM;\n+\n+\tt->ftid_tab = (struct filter_entry *)&t->tid_tab[t->ntids];\n+\tt->ftid_bmap_array = t4_os_alloc(ftid_bmap_size);\n+\tif (!t->ftid_bmap_array) {\n+\t\ttid_free(t);\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\tt4_os_lock_init(&t->ftid_lock);\n+\tt->ftid_bmap = rte_bitmap_init(t->nftids, t->ftid_bmap_array,\n+\t\t\t\t       ftid_bmap_size);\n+\tif (!t->ftid_bmap) {\n+\t\ttid_free(t);\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\treturn 0;\n+}\n+\n static inline bool is_x_1g_port(const struct link_config *lc)\n {\n \treturn (lc->pcaps & FW_PORT_CAP32_SPEED_1G) != 0;\n@@ -706,6 +775,7 @@ static int adap_init0_config(struct adapter *adapter, int reset)\n \n static int adap_init0(struct adapter *adap)\n {\n+\tstruct fw_caps_config_cmd caps_cmd;\n \tint ret = 0;\n \tu32 v, port_vec;\n \tenum dev_state state;\n@@ -822,6 +892,35 @@ static int adap_init0(struct adapter *adap)\n \t V_FW_PARAMS_PARAM_Y(0) | \\\n \t V_FW_PARAMS_PARAM_Z(0))\n \n+\tparams[0] = FW_PARAM_PFVF(FILTER_START);\n+\tparams[1] = FW_PARAM_PFVF(FILTER_END);\n+\tret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val);\n+\tif (ret < 0)\n+\t\tgoto bye;\n+\tadap->tids.ftid_base = val[0];\n+\tadap->tids.nftids = val[1] - val[0] + 1;\n+\n+\t/*\n+\t * Get device capabilities so we can determine what resources we need\n+\t * to manage.\n+\t */\n+\tmemset(&caps_cmd, 0, sizeof(caps_cmd));\n+\tcaps_cmd.op_to_write = htonl(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |\n+\t\t\t\t     F_FW_CMD_REQUEST | F_FW_CMD_READ);\n+\tcaps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));\n+\tret = t4_wr_mbox(adap, adap->mbox, &caps_cmd, sizeof(caps_cmd),\n+\t\t\t &caps_cmd);\n+\tif (ret < 0)\n+\t\tgoto bye;\n+\n+\t/* query tid-related parameters */\n+\tparams[0] = FW_PARAM_DEV(NTID);\n+\tret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,\n+\t\t\t      params, val);\n+\tif (ret < 0)\n+\t\tgoto bye;\n+\tadap->tids.ntids = val[0];\n+\n \t/* If we're running on newer firmware, let it know that we're\n \t * prepared to deal with encapsulated CPL messages.  Older\n \t * firmware won't understand this and we'll just get\n@@ -1307,6 +1406,7 @@ void cxgbe_close(struct adapter *adapter)\n \tif (adapter->flags & FULL_INIT_DONE) {\n \t\tif (is_pf4(adapter))\n \t\t\tt4_intr_disable(adapter);\n+\t\ttid_free(&adapter->tids);\n \t\tt4_sge_tx_monitor_stop(adapter);\n \t\tt4_free_sge_resources(adapter);\n \t\tfor_each_port(adapter, i) {\n@@ -1469,6 +1569,12 @@ int cxgbe_probe(struct adapter *adapter)\n \tprint_adapter_info(adapter);\n \tprint_port_info(adapter);\n \n+\tif (tid_init(&adapter->tids) < 0) {\n+\t\t/* Disable filtering support */\n+\t\tdev_warn(adapter, \"could not allocate TID table, \"\n+\t\t\t \"filter support disabled. Continuing\\n\");\n+\t}\n+\n \terr = init_rss(adapter);\n \tif (err)\n \t\tgoto out_free;\ndiff --git a/drivers/net/cxgbe/cxgbe_ofld.h b/drivers/net/cxgbe/cxgbe_ofld.h\nnew file mode 100644\nindex 000000000..57b4eb15b\n--- /dev/null\n+++ b/drivers/net/cxgbe/cxgbe_ofld.h\n@@ -0,0 +1,27 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2014-2018 Chelsio Communications.\n+ * All rights reserved.\n+ */\n+\n+#ifndef _CXGBE_OFLD_H_\n+#define _CXGBE_OFLD_H_\n+\n+#include <rte_bitmap.h>\n+\n+#include \"cxgbe_filter.h\"\n+\n+/*\n+ * Holds the size, base address, free list start, etc of filter TID.\n+ * The tables themselves are allocated dynamically.\n+ */\n+struct tid_info {\n+\tvoid **tid_tab;\n+\tunsigned int ntids;\n+\tstruct filter_entry *ftid_tab;\t/* Normal filters */\n+\tstruct rte_bitmap *ftid_bmap;\n+\tuint8_t *ftid_bmap_array;\n+\tunsigned int nftids;\n+\tunsigned int ftid_base;\n+\trte_spinlock_t ftid_lock;\n+};\n+#endif /* _CXGBE_OFLD_H_ */\n",
    "prefixes": [
        "dpdk-dev",
        "1/7"
    ]
}