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GET /api/patches/41640/?format=api
http://patchwork.dpdk.org/api/patches/41640/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/1530087896-64357-1-git-send-email-wei.zhao1@intel.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1530087896-64357-1-git-send-email-wei.zhao1@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1530087896-64357-1-git-send-email-wei.zhao1@intel.com", "date": "2018-06-27T08:24:56", "name": "[v5] net/fm10k: add support for check descriptor status APIs", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "6116ded43075fa8b08712e7dbfa2e2b56f7d1465", "submitter": { "id": 495, "url": "http://patchwork.dpdk.org/api/people/495/?format=api", "name": "Zhao1, Wei", "email": "wei.zhao1@intel.com" }, "delegate": { "id": 1540, "url": "http://patchwork.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/1530087896-64357-1-git-send-email-wei.zhao1@intel.com/mbox/", "series": [ { "id": 253, "url": "http://patchwork.dpdk.org/api/series/253/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=253", "date": "2018-06-27T08:24:56", "name": "[v5] net/fm10k: add support for check descriptor status APIs", "version": 5, "mbox": "http://patchwork.dpdk.org/series/253/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/41640/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/41640/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 511351BE9C;\n\tWed, 27 Jun 2018 10:45:56 +0200 (CEST)", "from mga03.intel.com (mga03.intel.com [134.134.136.65])\n\tby dpdk.org (Postfix) with ESMTP id 4648B1BE98\n\tfor <dev@dpdk.org>; Wed, 27 Jun 2018 10:45:53 +0200 (CEST)", "from fmsmga003.fm.intel.com ([10.253.24.29])\n\tby orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t27 Jun 2018 01:45:52 -0700", "from dpdk6.bj.intel.com ([172.16.182.94])\n\tby FMSMGA003.fm.intel.com with ESMTP; 27 Jun 2018 01:45:50 -0700" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.51,278,1526367600\"; d=\"scan'208\";a=\"60508556\"", "From": "Wei Zhao <wei.zhao1@intel.com>", "To": "dev@dpdk.org", "Cc": "qi.z.zhang@intel.com,\n\tZhao Wei <wei.zhao1@intel.com>", "Date": "Wed, 27 Jun 2018 16:24:56 +0800", "Message-Id": "<1530087896-64357-1-git-send-email-wei.zhao1@intel.com>", "X-Mailer": "git-send-email 2.7.5", "In-Reply-To": "<1529655607-38664-1-git-send-email-wei.zhao1@intel.com>", "References": "<1529655607-38664-1-git-send-email-wei.zhao1@intel.com>", "Subject": "[dpdk-dev] [PATCH v5] net/fm10k: add support for check descriptor\n\tstatus APIs", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Zhao Wei <wei.zhao1@intel.com>\n\nrte_eth_rx_descritpr_status and rte_eth_tx_descriptor_status\nare supported by fm10K.\n\nSigned-off-by: Wei Zhao <wei.zhao1@intel.com>\n---\n\nv2:\n-fix DD check error in tx descriptor\n\nv3:\n-fix DD check index error\n\nv4:\n-fix error in RS bit list poll\n\nv5:\n-rebase code to branch and delete useless variable\n---\n doc/guides/rel_notes/release_18_08.rst | 6 +++\n drivers/net/fm10k/fm10k.h | 7 +++\n drivers/net/fm10k/fm10k_ethdev.c | 2 +\n drivers/net/fm10k/fm10k_rxtx.c | 78 ++++++++++++++++++++++++++++++++++\n 4 files changed, 93 insertions(+)", "diff": "diff --git a/doc/guides/rel_notes/release_18_08.rst b/doc/guides/rel_notes/release_18_08.rst\nindex bc01242..951d1aa 100644\n--- a/doc/guides/rel_notes/release_18_08.rst\n+++ b/doc/guides/rel_notes/release_18_08.rst\n@@ -46,6 +46,12 @@ New Features\n Flow API support has been added to CXGBE Poll Mode Driver to offload\n flows to Chelsio T5/T6 NICs.\n \n+* **Added fm10k ethernet driver to support check descriptor status APIs.**\n+\n+ Fm10k nic need to support check descriptor status APIs, they are\n+ rte_eth_rx_descriptor_status and rte_eth_tx_descriptor_status.\n+ add ops pointer with new function which enable feature.\n+\n \n API Changes\n -----------\ndiff --git a/drivers/net/fm10k/fm10k.h b/drivers/net/fm10k/fm10k.h\nindex ef30780..1bc2c18 100644\n--- a/drivers/net/fm10k/fm10k.h\n+++ b/drivers/net/fm10k/fm10k.h\n@@ -329,6 +329,13 @@ uint16_t fm10k_recv_scattered_pkts(void *rx_queue,\n int\n fm10k_dev_rx_descriptor_done(void *rx_queue, uint16_t offset);\n \n+int\n+fm10k_dev_rx_descriptor_status(void *rx_queue, uint16_t offset);\n+\n+int\n+fm10k_dev_tx_descriptor_status(void *rx_queue, uint16_t offset);\n+\n+\n uint16_t fm10k_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,\n \tuint16_t nb_pkts);\n \ndiff --git a/drivers/net/fm10k/fm10k_ethdev.c b/drivers/net/fm10k/fm10k_ethdev.c\nindex 3ff1b0e..ea2f2bf 100644\n--- a/drivers/net/fm10k/fm10k_ethdev.c\n+++ b/drivers/net/fm10k/fm10k_ethdev.c\n@@ -2837,6 +2837,8 @@ static const struct eth_dev_ops fm10k_eth_dev_ops = {\n \t.tx_queue_setup\t\t= fm10k_tx_queue_setup,\n \t.tx_queue_release\t= fm10k_tx_queue_release,\n \t.rx_descriptor_done\t= fm10k_dev_rx_descriptor_done,\n+\t.rx_descriptor_status = fm10k_dev_rx_descriptor_status,\n+\t.tx_descriptor_status = fm10k_dev_tx_descriptor_status,\n \t.rx_queue_intr_enable\t= fm10k_dev_rx_queue_intr_enable,\n \t.rx_queue_intr_disable\t= fm10k_dev_rx_queue_intr_disable,\n \t.reta_update\t\t= fm10k_reta_update,\ndiff --git a/drivers/net/fm10k/fm10k_rxtx.c b/drivers/net/fm10k/fm10k_rxtx.c\nindex 9320748..4a5b46e 100644\n--- a/drivers/net/fm10k/fm10k_rxtx.c\n+++ b/drivers/net/fm10k/fm10k_rxtx.c\n@@ -389,6 +389,84 @@ fm10k_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)\n \treturn ret;\n }\n \n+int\n+fm10k_dev_rx_descriptor_status(void *rx_queue, uint16_t offset)\n+{\n+\tvolatile union fm10k_rx_desc *rxdp;\n+\tstruct fm10k_rx_queue *rxq = rx_queue;\n+\tuint16_t nb_hold, trigger_last;\n+\tuint16_t desc;\n+\tint ret;\n+\n+\tif (unlikely(offset >= rxq->nb_desc)) {\n+\t\tPMD_DRV_LOG(ERR, \"Invalid RX descriptor offset %u\", offset);\n+\t\treturn 0;\n+\t}\n+\n+\tif (rxq->next_trigger < rxq->alloc_thresh)\n+\t\ttrigger_last = rxq->next_trigger +\n+\t\t\t\t\trxq->nb_desc - rxq->alloc_thresh;\n+\telse\n+\t\ttrigger_last = rxq->next_trigger - rxq->alloc_thresh;\n+\n+\tif (rxq->next_dd < trigger_last)\n+\t\tnb_hold = rxq->next_dd + rxq->nb_desc - trigger_last;\n+\telse\n+\t\tnb_hold = rxq->next_dd - trigger_last;\n+\n+\tif (offset >= rxq->nb_desc - nb_hold)\n+\t\treturn RTE_ETH_RX_DESC_UNAVAIL;\n+\n+\tdesc = rxq->next_dd + offset;\n+\tif (desc >= rxq->nb_desc)\n+\t\tdesc -= rxq->nb_desc;\n+\n+\trxdp = &rxq->hw_ring[desc];\n+\n+\tret = !!(rxdp->w.status &\n+\t\t\trte_cpu_to_le_16(FM10K_RXD_STATUS_DD));\n+\n+\treturn ret;\n+}\n+\n+int\n+fm10k_dev_tx_descriptor_status(void *tx_queue, uint16_t offset)\n+{\n+\tvolatile struct fm10k_tx_desc *txdp;\n+\tstruct fm10k_tx_queue *txq = tx_queue;\n+\tuint16_t desc;\n+\tuint16_t next_rs = txq->nb_desc;\n+\tstruct fifo rs_tracker = txq->rs_tracker;\n+\tstruct fifo *r = &rs_tracker;\n+\n+\tif (unlikely(offset >= txq->nb_desc))\n+\t\treturn -EINVAL;\n+\n+\tdesc = txq->next_free + offset;\n+\t/* go to next desc that has the RS bit */\n+\tdesc = (desc / txq->rs_thresh + 1) *\n+\t\ttxq->rs_thresh - 1;\n+\n+\tif (desc >= txq->nb_desc) {\n+\t\tdesc -= txq->nb_desc;\n+\t\tif (desc >= txq->nb_desc)\n+\t\t\tdesc -= txq->nb_desc;\n+\t}\n+\n+\tr->head = r->list;\n+\tfor ( ; r->head != r->endp; ) {\n+\t\tif (*r->head >= desc && *r->head < next_rs)\n+\t\t\tnext_rs = *r->head;\n+\t\t++r->head;\n+\t}\n+\n+\ttxdp = &txq->hw_ring[next_rs];\n+\tif (txdp->flags & FM10K_TXD_FLAG_DONE)\n+\t\treturn RTE_ETH_TX_DESC_DONE;\n+\n+\treturn RTE_ETH_TX_DESC_FULL;\n+}\n+\n /*\n * Free multiple TX mbuf at a time if they are in the same pool\n *\n", "prefixes": [ "v5" ] }{ "id": 41640, "url": "