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GET /api/patches/41784/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 41784,
    "url": "http://patchwork.dpdk.org/api/patches/41784/?format=api",
    "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20180628031940.17397-14-johndale@cisco.com/",
    "project": {
        "id": 1,
        "url": "http://patchwork.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20180628031940.17397-14-johndale@cisco.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20180628031940.17397-14-johndale@cisco.com",
    "date": "2018-06-28T03:19:40",
    "name": "[14/14] net/enic: cap Rx packet processing to end of desc ring",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "36de3893fd6e1f64a692fc7b9e46643764d6afb2",
    "submitter": {
        "id": 359,
        "url": "http://patchwork.dpdk.org/api/people/359/?format=api",
        "name": "John Daley (johndale)",
        "email": "johndale@cisco.com"
    },
    "delegate": {
        "id": 319,
        "url": "http://patchwork.dpdk.org/api/users/319/?format=api",
        "username": "fyigit",
        "first_name": "Ferruh",
        "last_name": "Yigit",
        "email": "ferruh.yigit@amd.com"
    },
    "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20180628031940.17397-14-johndale@cisco.com/mbox/",
    "series": [
        {
            "id": 279,
            "url": "http://patchwork.dpdk.org/api/series/279/?format=api",
            "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=279",
            "date": "2018-06-28T03:19:27",
            "name": "[01/14] net/enic: fix receive packet types",
            "version": 1,
            "mbox": "http://patchwork.dpdk.org/series/279/mbox/"
        }
    ],
    "comments": "http://patchwork.dpdk.org/api/patches/41784/comments/",
    "check": "success",
    "checks": "http://patchwork.dpdk.org/api/patches/41784/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id C92111B446;\n\tThu, 28 Jun 2018 05:27:45 +0200 (CEST)",
            "from rcdn-iport-8.cisco.com (rcdn-iport-8.cisco.com [173.37.86.79])\n\tby dpdk.org (Postfix) with ESMTP id EFB861B445\n\tfor <dev@dpdk.org>; Thu, 28 Jun 2018 05:27:44 +0200 (CEST)",
            "from rcdn-core-10.cisco.com ([173.37.93.146])\n\tby rcdn-iport-8.cisco.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t28 Jun 2018 03:27:44 +0000",
            "from cisco.com (savbu-usnic-a.cisco.com [10.193.184.48])\n\tby rcdn-core-10.cisco.com (8.14.5/8.14.5) with ESMTP id\n\tw5S3RiY3023780; Thu, 28 Jun 2018 03:27:44 GMT",
            "by cisco.com (Postfix, from userid 392789)\n\tid 06C9220F2001; Wed, 27 Jun 2018 20:27:43 -0700 (PDT)"
        ],
        "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n\td=cisco.com; i=@cisco.com; l=3124; q=dns/txt; s=iport;\n\tt=1530156465; x=1531366065;\n\th=from:to:cc:subject:date:message-id:in-reply-to: references;\n\tbh=tFT+IT8nHTeXMmyBBF1ew4ZNW03b3oMn4UJNBHKmzIk=;\n\tb=gddhn/xxFjUssKf5HmpcaCF6jTvapNwM91u4xHqN3kShY2NDCGroKJqi\n\tkRxQdzxvMvPZfClPE/weuzu+dNFtOtek45EULNloQE2H4gUoVFe0pnnYD\n\t6KJ0nlwey6Q4TzjaWpGX9qGbcuKiS67ukxugVpir1e8wU2ueWDrrOfJfG Y=;",
        "X-IronPort-AV": "E=Sophos;i=\"5.51,281,1526342400\"; d=\"scan'208\";a=\"414338894\"",
        "From": "John Daley <johndale@cisco.com>",
        "To": "ferruh.yigit@intel.com",
        "Cc": "dev@dpdk.org, John Daley <johndale@cisco.com>",
        "Date": "Wed, 27 Jun 2018 20:19:40 -0700",
        "Message-Id": "<20180628031940.17397-14-johndale@cisco.com>",
        "X-Mailer": "git-send-email 2.16.2",
        "In-Reply-To": "<20180628031940.17397-1-johndale@cisco.com>",
        "References": "<20180628031940.17397-1-johndale@cisco.com>",
        "Subject": "[dpdk-dev] [PATCH 14/14] net/enic: cap Rx packet processing to end\n\tof desc ring",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "In the default Rx handler stop processing packets at the end of\nthe completion ring so that wrapping doesn't have to be checked\nin the inner while loop.\n\nAlso, check the color bit in the completion without using a conditional.\n\nSigned-off-by: John Daley <johndale@cisco.com>\nReviewed-by: Hyong Youb Kim <hyonkim@cisco.com>\n---\n drivers/net/enic/enic_rxtx.c | 25 ++++++++++++++-----------\n 1 file changed, 14 insertions(+), 11 deletions(-)",
    "diff": "diff --git a/drivers/net/enic/enic_rxtx.c b/drivers/net/enic/enic_rxtx.c\nindex e0f93dd5e..7ae03f31b 100644\n--- a/drivers/net/enic/enic_rxtx.c\n+++ b/drivers/net/enic/enic_rxtx.c\n@@ -310,7 +310,7 @@ enic_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,\n \tstruct vnic_rq *rq;\n \tstruct enic *enic = vnic_dev_priv(sop_rq->vdev);\n \tuint16_t cq_idx;\n-\tuint16_t rq_idx;\n+\tuint16_t rq_idx, max_rx;\n \tuint16_t rq_num;\n \tstruct rte_mbuf *nmb, *rxmb;\n \tuint16_t nb_rx = 0;\n@@ -325,19 +325,23 @@ enic_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,\n \tcq = &enic->cq[enic_cq_rq(enic, sop_rq->index)];\n \tcq_idx = cq->to_clean;\t\t/* index of cqd, rqd, mbuf_table */\n \tcqd_ptr = (struct cq_desc *)(cq->ring.descs) + cq_idx;\n+\tcolor = cq->last_color;\n \n \tdata_rq = &enic->rq[sop_rq->data_queue_idx];\n \n-\twhile (nb_rx < nb_pkts) {\n+\t/* Receive until the end of the ring, at most. */\n+\tmax_rx = RTE_MIN(nb_pkts, cq->ring.desc_count - cq_idx);\n+\n+\twhile (max_rx) {\n \t\tvolatile struct rq_enet_desc *rqd_ptr;\n \t\tstruct cq_desc cqd;\n \t\tuint8_t packet_error;\n \t\tuint16_t ciflags;\n \n+\t\tmax_rx--;\n+\n \t\t/* Check for pkts available */\n-\t\tcolor = (cqd_ptr->type_color >> CQ_DESC_COLOR_SHIFT)\n-\t\t\t& CQ_DESC_COLOR_MASK;\n-\t\tif (color == cq->last_color)\n+\t\tif ((cqd_ptr->type_color & CQ_DESC_COLOR_MASK_NOSHIFT) == color)\n \t\t\tbreak;\n \n \t\t/* Get the cq descriptor and extract rq info from it */\n@@ -361,13 +365,7 @@ enic_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,\n \t\t/* Get the mbuf to return and replace with one just allocated */\n \t\trxmb = rq->mbuf_ring[rq_idx];\n \t\trq->mbuf_ring[rq_idx] = nmb;\n-\n-\t\t/* Increment cqd, rqd, mbuf_table index */\n \t\tcq_idx++;\n-\t\tif (unlikely(cq_idx == cq->ring.desc_count)) {\n-\t\t\tcq_idx = 0;\n-\t\t\tcq->last_color = cq->last_color ? 0 : 1;\n-\t\t}\n \n \t\t/* Prefetch next mbuf & desc while processing current one */\n \t\tcqd_ptr = (struct cq_desc *)(cq->ring.descs) + cq_idx;\n@@ -419,6 +417,7 @@ enic_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,\n \t\tfirst_seg->packet_type =\n \t\t\tenic_cq_rx_flags_to_pkt_type(&cqd, tnl);\n \t\tenic_cq_rx_to_pkt_flags(&cqd, first_seg);\n+\n \t\t/* Wipe the outer types set by enic_cq_rx_flags_to_pkt_type() */\n \t\tif (tnl) {\n \t\t\tfirst_seg->packet_type &= ~(RTE_PTYPE_L3_MASK |\n@@ -438,6 +437,10 @@ enic_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,\n \t\t/* store the mbuf address into the next entry of the array */\n \t\trx_pkts[nb_rx++] = first_seg;\n \t}\n+\tif (unlikely(cq_idx == cq->ring.desc_count)) {\n+\t\tcq_idx = 0;\n+\t\tcq->last_color ^= CQ_DESC_COLOR_MASK_NOSHIFT;\n+\t}\n \n \tsop_rq->pkt_first_seg = first_seg;\n \tsop_rq->pkt_last_seg = last_seg;\n",
    "prefixes": [
        "14/14"
    ]
}