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GET /api/patches/41796/?format=api
{ "id": 41796, "url": "http://patchwork.dpdk.org/api/patches/41796/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/1530169969-6708-1-git-send-email-motih@mellanox.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1530169969-6708-1-git-send-email-motih@mellanox.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1530169969-6708-1-git-send-email-motih@mellanox.com", "date": "2018-06-28T07:12:49", "name": "net/mlx5: add support for 32bit systems", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "905c1d4a39dba864a1dece0f7778334e1a6303d3", "submitter": { "id": 748, "url": "http://patchwork.dpdk.org/api/people/748/?format=api", "name": "Moti Haimovsky", "email": "motih@mellanox.com" }, "delegate": { "id": 6624, "url": "http://patchwork.dpdk.org/api/users/6624/?format=api", "username": "shahafs", "first_name": "Shahaf", "last_name": "Shuler", "email": "shahafs@mellanox.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/1530169969-6708-1-git-send-email-motih@mellanox.com/mbox/", "series": [ { "id": 285, "url": "http://patchwork.dpdk.org/api/series/285/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=285", "date": "2018-06-28T07:12:49", "name": "net/mlx5: add support for 32bit systems", "version": 1, "mbox": "http://patchwork.dpdk.org/series/285/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/41796/comments/", "check": "fail", "checks": "http://patchwork.dpdk.org/api/patches/41796/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id D29365398;\n\tThu, 28 Jun 2018 09:13:15 +0200 (CEST)", "from EUR01-VE1-obe.outbound.protection.outlook.com\n\t(mail-ve1eur01on0089.outbound.protection.outlook.com [104.47.1.89])\n\tby dpdk.org (Postfix) with ESMTP id DD3F65689\n\tfor <dev@dpdk.org>; Thu, 28 Jun 2018 09:13:14 +0200 (CEST)", "from localhost.localdomain (37.142.13.130) by\n\tVI1PR05MB4447.eurprd05.prod.outlook.com (2603:10a6:803:43::10) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n\t15.20.906.24; Thu, 28 Jun 2018 07:13:11 +0000" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Mellanox.com;\n\ts=selector1;\n\th=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n\tbh=p/xvhtwsMSNaYifBU6pbgJ/eLqfDmy9NzXLv7iU2RSE=;\n\tb=Rc2UBWfw3FK4VRojR0BU73OtQgaxRRnOijVSuh0eWzMtKx3rFIpFBXRDUT7JSsR6OdKsALL1QM3LNXyNsSpfXhFZ2Yoi0s33P/pHtdsGrAC45y3tpSo0LGIFqmUnDqy5vBlkSbj8FHx+mrHcT3VY7y95Vxj7/dilQa81ehmDlOU=", "From": "Moti Haimovsky <motih@mellanox.com>", "To": "yskoh@mellanox.com,\n\tadrien.mazarguil@6wind.com", "Cc": "dev@dpdk.org,\n\tMoti Haimovsky <motih@mellanox.com>", "Date": "Thu, 28 Jun 2018 10:12:49 +0300", "Message-Id": "<1530169969-6708-1-git-send-email-motih@mellanox.com>", "X-Mailer": "git-send-email 1.7.1", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[37.142.13.130]", "X-ClientProxiedBy": "HE1PR0701CA0060.eurprd07.prod.outlook.com\n\t(2603:10a6:3:9e::28) To VI1PR05MB4447.eurprd05.prod.outlook.com\n\t(2603:10a6:803:43::10)", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "1217e6dc-db75-4440-4495-08d5dcc69c5a", "X-MS-Office365-Filtering-HT": "Tenant", "X-Microsoft-Antispam": "UriScan:; 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", "X-MS-Exchange-SenderADCheck": "1", "X-Exchange-Antispam-Report-CFA-Test": "BCL:0; PCL:0;\n\tRULEID:(8211001083)(6040522)(2401047)(5005006)(8121501046)(93006095)(93001095)(10201501046)(3002001)(3231254)(944501410)(52105095)(6055026)(149027)(150027)(6041310)(20161123560045)(20161123562045)(20161123558120)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123564045)(6072148)(201708071742011)(7699016);\n\tSRVR:VI1PR05MB4447; BCL:0; PCL:0; RULEID:; SRVR:VI1PR05MB4447; ", "X-Forefront-PRVS": "0717E25089", "X-Forefront-Antispam-Report": "SFV:NSPM;\n\tSFS:(10009020)(6069001)(366004)(136003)(376002)(39860400002)(396003)(346002)(189003)(199004)(305945005)(7736002)(316002)(6346003)(8676002)(81156014)(16586007)(81166006)(51416003)(52116002)(25786009)(6506007)(386003)(26005)(478600001)(2906002)(68736007)(6666003)(575784001)(86362001)(50226002)(1857600001)(8936002)(16526019)(5660300001)(36756003)(6486002)(6306002)(6512007)(50466002)(106356001)(107886003)(14444005)(48376002)(486006)(476003)(956004)(2616005)(53936002)(105586002)(97736004)(4326008)(66066001)(3846002)(6116002)(47776003)(966005);\n\tDIR:OUT; SFP:1101; SCL:1; SRVR:VI1PR05MB4447; H:localhost.localdomain;\n\tFPR:; \n\tSPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; ", "Received-SPF": "None (protection.outlook.com: mellanox.com does not designate\n\tpermitted sender hosts)", "Authentication-Results": "spf=none (sender IP is )\n\tsmtp.mailfrom=motih@mellanox.com; ", "X-Microsoft-Antispam-Message-Info": "EczYeo7iB6eCNA/h3DLuAHSEWMuIs97X65Q7XawXK1XHg080+XuyKd2l8kPhpM8eABlN7pgx66VkW/Hn9Zv2kyJboYkEJcHEbPs6lCKQ79wUGk5TV9VV91z6+e/yHwUntlUEbJmJKYUgi1c4xs2ruZ3b+xbZ3oKzcm5TVDUBvLT7xV3E8spiLIpp2VBWIG0qTMaV1v4ZtwXZ/bCTk9hwSUx7R3EHrCbWyJ1kVJjh5CifUDu5n/NAjYa89hG5vQ+zBXkvKFp3HAdTYo6gkGy7NVzXsFmnpPSK2Be9YpJAlY9ZsvEQIhWUk5SgKkLsNG4WhFpngsPCGwXuo7QoFGfFyOY/VD6D13Fq/XRgl834XR4=", "SpamDiagnosticOutput": "1:99", "SpamDiagnosticMetadata": "NSPM", "X-OriginatorOrg": "Mellanox.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "28 Jun 2018 07:13:11.6382\n\t(UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "1217e6dc-db75-4440-4495-08d5dcc69c5a", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "a652971c-7d2e-4d9b-a6a4-d149256f461b", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "VI1PR05MB4447", "Subject": "[dpdk-dev] [PATCH] net/mlx5: add support for 32bit systems", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This patch adds support for building and running mlx5 PMD on\n32bit systems such as i686.\n\nThe main issue to tackle was handling the 32bit access to the UAR\nas quoted from the mlx5 PRM:\nQP and CQ DoorBells require 64-bit writes. For best performance, it\nis recommended to execute the QP/CQ DoorBell as a single 64-bit write\noperation. For platforms that do not support 64 bit writes, it is\npossible to issue the 64 bits DoorBells through two consecutive writes,\neach write 32 bits, as described below:\n* The order of writing each of the Dwords is from lower to upper\n addresses.\n* No other DoorBell can be rung (or even start ringing) in the midst of\n an on-going write of a DoorBell over a given UAR page.\nThe last rule implies that in a multi-threaded environment, the access\nto a UAR page (which can be accessible by all threads in the process)\nmust be synchronized (for example, using a semaphore) unless an atomic\nwrite of 64 bits in a single bus operation is guaranteed. Such a\nsynchronization is not required for when ringing DoorBells on different\nUAR pages.\n\nSigned-off-by: Moti Haimovsky <motih@mellanox.com>\n---\n doc/guides/nics/features/mlx5.ini | 1 +\n doc/guides/nics/mlx5.rst | 11 +++++++\n drivers/net/mlx5/mlx5.c | 8 ++++-\n drivers/net/mlx5/mlx5.h | 5 +++\n drivers/net/mlx5/mlx5_defs.h | 18 ++++++++--\n drivers/net/mlx5/mlx5_rxq.c | 6 +++-\n drivers/net/mlx5/mlx5_rxtx.c | 22 +++++++------\n drivers/net/mlx5/mlx5_rxtx.h | 69 ++++++++++++++++++++++++++++++++++++++-\n drivers/net/mlx5/mlx5_txq.c | 13 +++++++-\n 9 files changed, 137 insertions(+), 16 deletions(-)", "diff": "diff --git a/doc/guides/nics/features/mlx5.ini b/doc/guides/nics/features/mlx5.ini\nindex e75b14b..b28b43e 100644\n--- a/doc/guides/nics/features/mlx5.ini\n+++ b/doc/guides/nics/features/mlx5.ini\n@@ -43,5 +43,6 @@ Multiprocess aware = Y\n Other kdrv = Y\n ARMv8 = Y\n Power8 = Y\n+x86-32 = Y\n x86-64 = Y\n Usage doc = Y\ndiff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst\nindex 7dd9c1c..cb9d5d8 100644\n--- a/doc/guides/nics/mlx5.rst\n+++ b/doc/guides/nics/mlx5.rst\n@@ -50,6 +50,8 @@ Features\n --------\n \n - Multi arch support: x86_64, POWER8, ARMv8.\n+- Support for i686 is available only when working with\n+ rdma-core version 18.0 or above, built with 32bit support.\n - Multiple TX and RX queues.\n - Support for scattered TX and RX frames.\n - IPv4, IPv6, TCPv4, TCPv6, UDPv4 and UDPv6 RSS on any number of queues.\n@@ -136,6 +138,11 @@ Limitations\n enabled (``rxq_cqe_comp_en``) at the same time, RSS hash result is not fully\n supported. Some Rx packets may not have PKT_RX_RSS_HASH.\n \n+- Building for i686 is only supported with:\n+\n+ - rdma-core version 18.0 or above built with 32bit support.\n+ - Kernel version 4.14.41 or above.\n+\n Statistics\n ----------\n \n@@ -477,6 +484,10 @@ RMDA Core with Linux Kernel\n - Minimal kernel version : v4.14 or the most recent 4.14-rc (see `Linux installation documentation`_)\n - Minimal rdma-core version: v15+ commit 0c5f5765213a (\"Merge pull request #227 from yishaih/tm\")\n (see `RDMA Core installation documentation`_)\n+- When building for i686 use:\n+\n+ - rdma-core version 18.0 or above built with 32bit support.\n+ - Kernel version 4.14.41 or above.\n \n .. _`Linux installation documentation`: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable.git/plain/Documentation/admin-guide/README.rst\n .. _`RDMA Core installation documentation`: https://raw.githubusercontent.com/linux-rdma/rdma-core/master/README.md\ndiff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c\nindex f0e6ed7..5d0f706 100644\n--- a/drivers/net/mlx5/mlx5.c\n+++ b/drivers/net/mlx5/mlx5.c\n@@ -567,7 +567,7 @@\n \trte_memseg_walk(find_lower_va_bound, &addr);\n \n \t/* keep distance to hugepages to minimize potential conflicts. */\n-\taddr = RTE_PTR_SUB(addr, MLX5_UAR_OFFSET + MLX5_UAR_SIZE);\n+\taddr = RTE_PTR_SUB(addr, (uintptr_t)(MLX5_UAR_OFFSET + MLX5_UAR_SIZE));\n \t/* anonymous mmap, no real memory consumption. */\n \taddr = mmap(addr, MLX5_UAR_SIZE,\n \t\t PROT_NONE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);\n@@ -953,6 +953,12 @@\n \t\tpriv->port = port;\n \t\tpriv->pd = pd;\n \t\tpriv->mtu = ETHER_MTU;\n+#ifndef RTE_ARCH_64\n+\t\t/* Initialize UAR access locks for 32bit implementations. */\n+\t\trte_spinlock_init(&priv->uar_lock_cq);\n+\t\tfor (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)\n+\t\t\trte_spinlock_init(&priv->uar_lock[i]);\n+#endif\n \t\terr = mlx5_args(&config, pci_dev->device.devargs);\n \t\tif (err) {\n \t\t\terr = rte_errno;\ndiff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex 997b04a..2da32cd 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -198,6 +198,11 @@ struct priv {\n \t/* Context for Verbs allocator. */\n \tint nl_socket; /* Netlink socket. */\n \tuint32_t nl_sn; /* Netlink message sequence number. */\n+#ifndef RTE_ARCH_64\n+\trte_spinlock_t uar_lock_cq; /* CQs share a common distinct UAR */\n+\trte_spinlock_t uar_lock[MLX5_UAR_PAGE_NUM_MAX];\n+\t/* UAR same-page access control required in 32bit implementations. */\n+#endif\n };\n \n #define PORT_ID(priv) ((priv)->dev_data->port_id)\ndiff --git a/drivers/net/mlx5/mlx5_defs.h b/drivers/net/mlx5/mlx5_defs.h\nindex 5bbbec2..f6ec415 100644\n--- a/drivers/net/mlx5/mlx5_defs.h\n+++ b/drivers/net/mlx5/mlx5_defs.h\n@@ -87,14 +87,28 @@\n #define MLX5_LINK_STATUS_TIMEOUT 10\n \n /* Reserved address space for UAR mapping. */\n-#define MLX5_UAR_SIZE (1ULL << 32)\n+#define MLX5_UAR_SIZE (1ULL << (sizeof(uintptr_t) * 4))\n \n /* Offset of reserved UAR address space to hugepage memory. Offset is used here\n * to minimize possibility of address next to hugepage being used by other code\n * in either primary or secondary process, failing to map TX UAR would make TX\n * packets invisible to HW.\n */\n-#define MLX5_UAR_OFFSET (1ULL << 32)\n+#define MLX5_UAR_OFFSET (1ULL << (sizeof(uintptr_t) * 4))\n+\n+/* Maximum number of UAR pages used by a port,\n+ * These are the size and mask for an array of mutexes used to synchronize\n+ * the access to port's UARs on platforms that do not support 64 bit writes.\n+ * In such systems it is possible to issue the 64 bits DoorBells through two\n+ * consecutive writes, each write 32 bits. The access to a UAR page (which can\n+ * be accessible by all threads in the process) must be synchronized\n+ * (for example, using a semaphore). Such a synchronization is not required\n+ * when ringing DoorBells on different UAR pages.\n+ * A port with 512 Tx queues uses 8, 4kBytes, UAR pages which are shared\n+ * among the ports.\n+ */\n+#define MLX5_UAR_PAGE_NUM_MAX 64\n+#define MLX5_UAR_PAGE_NUM_MASK ((MLX5_UAR_PAGE_NUM_MAX) - 1)\n \n /* Log 2 of the default number of strides per WQE for Multi-Packet RQ. */\n #define MLX5_MPRQ_STRIDE_NUM_N 6U\ndiff --git a/drivers/net/mlx5/mlx5_rxq.c b/drivers/net/mlx5/mlx5_rxq.c\nindex 08dd559..820048f 100644\n--- a/drivers/net/mlx5/mlx5_rxq.c\n+++ b/drivers/net/mlx5/mlx5_rxq.c\n@@ -643,7 +643,8 @@\n \tdoorbell = (uint64_t)doorbell_hi << 32;\n \tdoorbell |= rxq->cqn;\n \trxq->cq_db[MLX5_CQ_ARM_DB] = rte_cpu_to_be_32(doorbell_hi);\n-\trte_write64(rte_cpu_to_be_64(doorbell), cq_db_reg);\n+\tmlx5_uar_write64(rte_cpu_to_be_64(doorbell),\n+\t\t\t cq_db_reg, rxq->uar_lock_cq);\n }\n \n /**\n@@ -1445,6 +1446,9 @@ struct mlx5_rxq_ctrl *\n \ttmpl->rxq.elts_n = log2above(desc);\n \ttmpl->rxq.elts =\n \t\t(struct rte_mbuf *(*)[1 << tmpl->rxq.elts_n])(tmpl + 1);\n+#ifndef RTE_ARCH_64\n+\ttmpl->rxq.uar_lock_cq = &priv->uar_lock_cq;\n+#endif\n \ttmpl->idx = idx;\n \trte_atomic32_inc(&tmpl->refcnt);\n \tLIST_INSERT_HEAD(&priv->rxqsctrl, tmpl, next);\ndiff --git a/drivers/net/mlx5/mlx5_rxtx.c b/drivers/net/mlx5/mlx5_rxtx.c\nindex a7ed8d8..ec35ea0 100644\n--- a/drivers/net/mlx5/mlx5_rxtx.c\n+++ b/drivers/net/mlx5/mlx5_rxtx.c\n@@ -495,6 +495,7 @@\n \tvolatile struct mlx5_wqe_ctrl *last_wqe = NULL;\n \tunsigned int segs_n = 0;\n \tconst unsigned int max_inline = txq->max_inline;\n+\tuint64_t addr_64;\n \n \tif (unlikely(!pkts_n))\n \t\treturn 0;\n@@ -711,12 +712,12 @@\n \t\t\tds = 3;\n use_dseg:\n \t\t\t/* Add the remaining packet as a simple ds. */\n-\t\t\taddr = rte_cpu_to_be_64(addr);\n+\t\t\taddr_64 = rte_cpu_to_be_64(addr);\n \t\t\t*dseg = (rte_v128u32_t){\n \t\t\t\trte_cpu_to_be_32(length),\n \t\t\t\tmlx5_tx_mb2mr(txq, buf),\n-\t\t\t\taddr,\n-\t\t\t\taddr >> 32,\n+\t\t\t\taddr_64,\n+\t\t\t\taddr_64 >> 32,\n \t\t\t};\n \t\t\t++ds;\n \t\t\tif (!segs_n)\n@@ -750,12 +751,12 @@\n \t\ttotal_length += length;\n #endif\n \t\t/* Store segment information. */\n-\t\taddr = rte_cpu_to_be_64(rte_pktmbuf_mtod(buf, uintptr_t));\n+\t\taddr_64 = rte_cpu_to_be_64(rte_pktmbuf_mtod(buf, uintptr_t));\n \t\t*dseg = (rte_v128u32_t){\n \t\t\trte_cpu_to_be_32(length),\n \t\t\tmlx5_tx_mb2mr(txq, buf),\n-\t\t\taddr,\n-\t\t\taddr >> 32,\n+\t\t\taddr_64,\n+\t\t\taddr_64 >> 32,\n \t\t};\n \t\t(*txq->elts)[++elts_head & elts_m] = buf;\n \t\tif (--segs_n)\n@@ -1450,6 +1451,7 @@\n \tunsigned int mpw_room = 0;\n \tunsigned int inl_pad = 0;\n \tuint32_t inl_hdr;\n+\tuint64_t addr_64;\n \tstruct mlx5_mpw mpw = {\n \t\t.state = MLX5_MPW_STATE_CLOSED,\n \t};\n@@ -1586,13 +1588,13 @@\n \t\t\t\t\t((uintptr_t)mpw.data.raw +\n \t\t\t\t\t inl_pad);\n \t\t\t(*txq->elts)[elts_head++ & elts_m] = buf;\n-\t\t\taddr = rte_cpu_to_be_64(rte_pktmbuf_mtod(buf,\n-\t\t\t\t\t\t\t\t uintptr_t));\n+\t\t\taddr_64 = rte_cpu_to_be_64(\n+\t\t\t\t\trte_pktmbuf_mtod(buf, uintptr_t));\n \t\t\t*dseg = (rte_v128u32_t) {\n \t\t\t\trte_cpu_to_be_32(length),\n \t\t\t\tmlx5_tx_mb2mr(txq, buf),\n-\t\t\t\taddr,\n-\t\t\t\taddr >> 32,\n+\t\t\t\taddr_64,\n+\t\t\t\taddr_64 >> 32,\n \t\t\t};\n \t\t\tmpw.data.raw = (volatile void *)(dseg + 1);\n \t\t\tmpw.total_len += (inl_pad + sizeof(*dseg));\ndiff --git a/drivers/net/mlx5/mlx5_rxtx.h b/drivers/net/mlx5/mlx5_rxtx.h\nindex 0007be0..2448d73 100644\n--- a/drivers/net/mlx5/mlx5_rxtx.h\n+++ b/drivers/net/mlx5/mlx5_rxtx.h\n@@ -26,6 +26,8 @@\n #include <rte_common.h>\n #include <rte_hexdump.h>\n #include <rte_atomic.h>\n+#include <rte_spinlock.h>\n+#include <rte_io.h>\n \n #include \"mlx5_utils.h\"\n #include \"mlx5.h\"\n@@ -115,6 +117,10 @@ struct mlx5_rxq_data {\n \tvoid *cq_uar; /* CQ user access region. */\n \tuint32_t cqn; /* CQ number. */\n \tuint8_t cq_arm_sn; /* CQ arm seq number. */\n+#ifndef RTE_ARCH_64\n+\trte_spinlock_t *uar_lock_cq;\n+\t/* CQ (UAR) access lock required for 32bit implementations */\n+#endif\n \tuint32_t tunnel; /* Tunnel information. */\n } __rte_cache_aligned;\n \n@@ -196,6 +202,10 @@ struct mlx5_txq_data {\n \tvolatile void *bf_reg; /* Blueflame register remapped. */\n \tstruct rte_mbuf *(*elts)[]; /* TX elements. */\n \tstruct mlx5_txq_stats stats; /* TX queue counters. */\n+#ifndef RTE_ARCH_64\n+\trte_spinlock_t *uar_lock;\n+\t/* UAR access lock required for 32bit implementations */\n+#endif\n } __rte_cache_aligned;\n \n /* Verbs Rx queue elements. */\n@@ -348,6 +358,63 @@ uint16_t mlx5_rx_burst_vec(void *dpdk_txq, struct rte_mbuf **pkts,\n uint32_t mlx5_rx_addr2mr_bh(struct mlx5_rxq_data *rxq, uintptr_t addr);\n uint32_t mlx5_tx_addr2mr_bh(struct mlx5_txq_data *txq, uintptr_t addr);\n \n+/**\n+ * Provide safe 64bit store operation to mlx5 UAR region for both 32bit and\n+ * 64bit architectures.\n+ *\n+ * @param val\n+ * value to write in CPU endian format.\n+ * @param addr\n+ * Address to write to.\n+ * @param lock\n+ * Address of the lock to use for that UAR access.\n+ */\n+static __rte_always_inline void\n+__mlx5_uar_write64_relaxed(uint64_t val, volatile void *addr,\n+\t\t\t rte_spinlock_t *lock __rte_unused)\n+{\n+#ifdef RTE_ARCH_64\n+\trte_write64_relaxed(val, addr);\n+#else /* !RTE_ARCH_64 */\n+\trte_spinlock_lock(lock);\n+\trte_write32_relaxed(val, addr);\n+\trte_io_wmb();\n+\trte_write32_relaxed(val >> 32,\n+\t\t\t (volatile void *)((volatile char *)addr + 4));\n+\trte_spinlock_unlock(lock);\n+#endif\n+}\n+\n+/**\n+ * Provide safe 64bit store operation to mlx5 UAR region for both 32bit and\n+ * 64bit architectures while guaranteeing the order of execution with the\n+ * code being executed.\n+ *\n+ * @param val\n+ * value to write in CPU endian format.\n+ * @param addr\n+ * Address to write to.\n+ * @param lock\n+ * Address of the lock to use for that UAR access.\n+ */\n+static __rte_always_inline void\n+__mlx5_uar_write64(uint64_t val, volatile void *addr, rte_spinlock_t *lock)\n+{\n+\trte_io_wmb();\n+\t__mlx5_uar_write64_relaxed(val, addr, lock);\n+}\n+\n+/* Assist macros, used instead of directly calling the functions they wrap. */\n+#ifdef RTE_ARCH_64\n+#define mlx5_uar_write64_relaxed(val, dst, lock) \\\n+\t\t__mlx5_uar_write64_relaxed(val, dst, NULL)\n+#define mlx5_uar_write64(val, dst, lock) __mlx5_uar_write64(val, dst, NULL)\n+#else\n+#define mlx5_uar_write64_relaxed(val, dst, lock) \\\n+\t\t__mlx5_uar_write64_relaxed(val, dst, lock)\n+#define mlx5_uar_write64(val, dst, lock) __mlx5_uar_write64(val, dst, lock)\n+#endif\n+\n #ifndef NDEBUG\n /**\n * Verify or set magic value in CQE.\n@@ -614,7 +681,7 @@ uint16_t mlx5_rx_burst_vec(void *dpdk_txq, struct rte_mbuf **pkts,\n \t*txq->qp_db = rte_cpu_to_be_32(txq->wqe_ci);\n \t/* Ensure ordering between DB record and BF copy. */\n \trte_wmb();\n-\t*dst = *src;\n+\tmlx5_uar_write64_relaxed(*src, dst, txq->uar_lock);\n \tif (cond)\n \t\trte_wmb();\n }\ndiff --git a/drivers/net/mlx5/mlx5_txq.c b/drivers/net/mlx5/mlx5_txq.c\nindex 669b913..dc786d4 100644\n--- a/drivers/net/mlx5/mlx5_txq.c\n+++ b/drivers/net/mlx5/mlx5_txq.c\n@@ -255,6 +255,9 @@\n \tstruct mlx5_txq_ctrl *txq_ctrl;\n \tint already_mapped;\n \tsize_t page_size = sysconf(_SC_PAGESIZE);\n+#ifndef RTE_ARCH_64\n+\tunsigned int lock_idx;\n+#endif\n \n \tmemset(pages, 0, priv->txqs_n * sizeof(uintptr_t));\n \t/*\n@@ -281,7 +284,7 @@\n \t\t}\n \t\t/* new address in reserved UAR address space. */\n \t\taddr = RTE_PTR_ADD(priv->uar_base,\n-\t\t\t\t uar_va & (MLX5_UAR_SIZE - 1));\n+\t\t\t\t uar_va & (uintptr_t)(MLX5_UAR_SIZE - 1));\n \t\tif (!already_mapped) {\n \t\t\tpages[pages_n++] = uar_va;\n \t\t\t/* fixed mmap to specified address in reserved\n@@ -305,6 +308,12 @@\n \t\telse\n \t\t\tassert(txq_ctrl->txq.bf_reg ==\n \t\t\t RTE_PTR_ADD((void *)addr, off));\n+#ifndef RTE_ARCH_64\n+\t\t/* Assign a UAR lock according to UAR page number */\n+\t\tlock_idx = (txq_ctrl->uar_mmap_offset / page_size) &\n+\t\t\t MLX5_UAR_PAGE_NUM_MASK;\n+\t\ttxq->uar_lock = &priv->uar_lock[lock_idx];\n+#endif\n \t}\n \treturn 0;\n }\n@@ -511,6 +520,8 @@ struct mlx5_txq_ibv *\n \trte_atomic32_inc(&txq_ibv->refcnt);\n \tif (qp.comp_mask & MLX5DV_QP_MASK_UAR_MMAP_OFFSET) {\n \t\ttxq_ctrl->uar_mmap_offset = qp.uar_mmap_offset;\n+\t\tDRV_LOG(DEBUG, \"port %u: uar_mmap_offset 0x%lx\",\n+\t\t\tdev->data->port_id, txq_ctrl->uar_mmap_offset);\n \t} else {\n \t\tDRV_LOG(ERR,\n \t\t\t\"port %u failed to retrieve UAR info, invalid\"\n", "prefixes": [] }