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GET /api/patches/43169/?format=api
{ "id": 43169, "url": "http://patchwork.dpdk.org/api/patches/43169/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/1531850150-21767-1-git-send-email-fiona.trahe@intel.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1531850150-21767-1-git-send-email-fiona.trahe@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1531850150-21767-1-git-send-email-fiona.trahe@intel.com", "date": "2018-07-17T17:55:49", "name": "[1/2] common/qat: add sgl header", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "9399560dc9f0a7b4f502f59bd13a66deeb534709", "submitter": { "id": 423, "url": "http://patchwork.dpdk.org/api/people/423/?format=api", "name": "Fiona Trahe", "email": "fiona.trahe@intel.com" }, "delegate": { "id": 22, "url": "http://patchwork.dpdk.org/api/users/22/?format=api", "username": "pdelarag", "first_name": "Pablo", "last_name": "de Lara Guarch", "email": "pablo.de.lara.guarch@intel.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/1531850150-21767-1-git-send-email-fiona.trahe@intel.com/mbox/", "series": [ { "id": 642, "url": "http://patchwork.dpdk.org/api/series/642/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=642", "date": "2018-07-17T17:55:49", "name": "[1/2] common/qat: add sgl header", "version": 1, "mbox": "http://patchwork.dpdk.org/series/642/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/43169/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/43169/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id E615C2BD3;\n\tTue, 17 Jul 2018 19:56:13 +0200 (CEST)", "from mga17.intel.com (mga17.intel.com [192.55.52.151])\n\tby dpdk.org (Postfix) with ESMTP id 4807F160\n\tfor <dev@dpdk.org>; Tue, 17 Jul 2018 19:56:11 +0200 (CEST)", "from fmsmga007.fm.intel.com ([10.253.24.52])\n\tby fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t17 Jul 2018 10:56:09 -0700", "from sivswdev01.ir.intel.com (HELO localhost.localdomain)\n\t([10.237.217.45])\n\tby fmsmga007.fm.intel.com with ESMTP; 17 Jul 2018 10:55:54 -0700" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.51,366,1526367600\"; d=\"scan'208\";a=\"55071824\"", "From": "Fiona Trahe <fiona.trahe@intel.com>", "To": "dev@dpdk.org", "Cc": "pablo.de.lara.guarch@intel.com, fiona.trahe@intel.com,\n\ttomaszx.jozwiak@intel.com", "Date": "Tue, 17 Jul 2018 18:55:49 +0100", "Message-Id": "<1531850150-21767-1-git-send-email-fiona.trahe@intel.com>", "X-Mailer": "git-send-email 1.7.0.7", "Subject": "[dpdk-dev] [PATCH 1/2] common/qat: add sgl header", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This patch refactors the sgl struct so it includes a flexible\narray of flat buffers as sym and compress PMDs can have\ndifferent size sgls.\n\nSigned-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>\nSigned-off-by: Fiona Trahe <fiona.trahe@intel.com>\n---\n drivers/common/qat/qat_common.c | 53 ++++++++++++++++++++++++++++++-----------\n drivers/common/qat/qat_common.h | 23 ++++++++++--------\n drivers/crypto/qat/qat_sym.c | 12 ++++++----\n drivers/crypto/qat/qat_sym.h | 14 +++++++++--\n 4 files changed, 71 insertions(+), 31 deletions(-)", "diff": "diff --git a/drivers/common/qat/qat_common.c b/drivers/common/qat/qat_common.c\nindex c206d3b..c25372d 100644\n--- a/drivers/common/qat/qat_common.c\n+++ b/drivers/common/qat/qat_common.c\n@@ -8,40 +8,53 @@\n \n int\n qat_sgl_fill_array(struct rte_mbuf *buf, uint64_t buf_start,\n-\t\tstruct qat_sgl *list, uint32_t data_len)\n+\t\tvoid *list_in, uint32_t data_len,\n+\t\tconst int32_t max_segs)\n {\n \tint nr = 1;\n-\n-\tuint32_t buf_len = rte_pktmbuf_iova(buf) -\n-\t\t\tbuf_start + rte_pktmbuf_data_len(buf);\n+\tstruct qat_sgl *list = (struct qat_sgl *)list_in;\n+\t/* buf_start allows the first buffer to start at an address before or\n+\t * after the mbuf data start. It's used to either optimally align the\n+\t * dma to 64 or to start dma from an offset.\n+\t */\n+\tuint32_t buf_len;\n+\tuint32_t first_buf_len = rte_pktmbuf_data_len(buf) +\n+\t\t\t(rte_pktmbuf_mtophys(buf) - buf_start);\n+#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG\n+\tuint8_t *virt_addr[max_segs];\n+\tvirt_addr[0] = rte_pktmbuf_mtod(buf, uint8_t*) +\n+\t\t\t(rte_pktmbuf_mtophys(buf) - buf_start);\n+#endif\n \n \tlist->buffers[0].addr = buf_start;\n \tlist->buffers[0].resrvd = 0;\n-\tlist->buffers[0].len = buf_len;\n+\tlist->buffers[0].len = first_buf_len;\n \n-\tif (data_len <= buf_len) {\n+\tif (data_len <= first_buf_len) {\n \t\tlist->num_bufs = nr;\n \t\tlist->buffers[0].len = data_len;\n-\t\treturn 0;\n+\t\tgoto sgl_end;\n \t}\n \n \tbuf = buf->next;\n+\tbuf_len = first_buf_len;\n \twhile (buf) {\n-\t\tif (unlikely(nr == QAT_SGL_MAX_NUMBER)) {\n-\t\t\tQAT_LOG(ERR,\n-\t\t\t\t\"QAT PMD exceeded size of QAT SGL entry(%u)\",\n-\t\t\t\t\tQAT_SGL_MAX_NUMBER);\n+\t\tif (unlikely(nr == max_segs)) {\n+\t\t\tQAT_DP_LOG(ERR, \"Exceeded max segments in QAT SGL (%u)\",\n+\t\t\t\t\tmax_segs);\n \t\t\treturn -EINVAL;\n \t\t}\n \n \t\tlist->buffers[nr].len = rte_pktmbuf_data_len(buf);\n \t\tlist->buffers[nr].resrvd = 0;\n-\t\tlist->buffers[nr].addr = rte_pktmbuf_iova(buf);\n-\n+\t\tlist->buffers[nr].addr = rte_pktmbuf_mtophys(buf);\n+#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG\n+\t\tvirt_addr[nr] = rte_pktmbuf_mtod(buf, uint8_t*);\n+#endif\n \t\tbuf_len += list->buffers[nr].len;\n \t\tbuf = buf->next;\n \n-\t\tif (buf_len > data_len) {\n+\t\tif (buf_len >= data_len) {\n \t\t\tlist->buffers[nr].len -=\n \t\t\t\tbuf_len - data_len;\n \t\t\tbuf = NULL;\n@@ -50,6 +63,18 @@ qat_sgl_fill_array(struct rte_mbuf *buf, uint64_t buf_start,\n \t}\n \tlist->num_bufs = nr;\n \n+sgl_end:\n+#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG\n+\tQAT_DP_LOG(INFO, \"SGL with %d buffers:\", list->num_bufs);\n+\tfor (uint8_t i = 0; i < list->num_bufs; i++) {\n+\t\tQAT_DP_LOG(INFO, \"QAT SGL buf %d, len = %d, iova = 0x%012lx\",\n+\t\t\t\ti, list->buffers[i].len,\n+\t\t\t\tlist->buffers[i].addr);\n+\t\tQAT_DP_HEXDUMP_LOG(DEBUG, \"qat SGL\",\n+\t\t\t\tvirt_addr[i], list->buffers[i].len);\n+\t}\n+#endif\n+\n \treturn 0;\n }\n \ndiff --git a/drivers/common/qat/qat_common.h b/drivers/common/qat/qat_common.h\nindex db85d54..e6da7fb 100644\n--- a/drivers/common/qat/qat_common.h\n+++ b/drivers/common/qat/qat_common.h\n@@ -10,11 +10,6 @@\n \n /**< Intel(R) QAT device name for PCI registration */\n #define QAT_PCI_NAME\tqat\n-/*\n- * Maximum number of SGL entries\n- */\n-#define QAT_SGL_MAX_NUMBER\t16\n-\n #define QAT_64_BTYE_ALIGN_MASK (~0x3f)\n \n /* Intel(R) QuickAssist Technology device generation is enumerated\n@@ -31,6 +26,7 @@ enum qat_service_type {\n \tQAT_SERVICE_COMPRESSION,\n \tQAT_SERVICE_INVALID\n };\n+\n #define QAT_MAX_SERVICES\t\t(QAT_SERVICE_INVALID)\n \n /**< Common struct for scatter-gather list operations */\n@@ -40,11 +36,17 @@ struct qat_flat_buf {\n \tuint64_t addr;\n } __rte_packed;\n \n+#define qat_sgl_hdr struct { \\\n+\tuint64_t resrvd; \\\n+\tuint32_t num_bufs; \\\n+\tuint32_t num_mapped_bufs; \\\n+}\n+\n+__extension__\n struct qat_sgl {\n-\tuint64_t resrvd;\n-\tuint32_t num_bufs;\n-\tuint32_t num_mapped_bufs;\n-\tstruct qat_flat_buf buffers[QAT_SGL_MAX_NUMBER];\n+\tqat_sgl_hdr;\n+\t/* flexible array of flat buffers*/\n+\tstruct qat_flat_buf buffers[0];\n } __rte_packed __rte_cache_aligned;\n \n /** Common, i.e. not service-specific, statistics */\n@@ -64,7 +66,8 @@ struct qat_pci_device;\n \n int\n qat_sgl_fill_array(struct rte_mbuf *buf, uint64_t buf_start,\n-\t\tstruct qat_sgl *list, uint32_t data_len);\n+\t\tvoid *list_in, uint32_t data_len,\n+\t\tconst int32_t max_segs);\n void\n qat_stats_get(struct qat_pci_device *dev,\n \t\tstruct qat_common_stats *stats,\ndiff --git a/drivers/crypto/qat/qat_sym.c b/drivers/crypto/qat/qat_sym.c\nindex 4ed7d95..8273968 100644\n--- a/drivers/crypto/qat/qat_sym.c\n+++ b/drivers/crypto/qat/qat_sym.c\n@@ -495,8 +495,9 @@ qat_sym_build_request(void *in_op, uint8_t *out_msg,\n \t\tICP_QAT_FW_COMN_PTR_TYPE_SET(qat_req->comn_hdr.comn_req_flags,\n \t\t\t\tQAT_COMN_PTR_TYPE_SGL);\n \t\tret = qat_sgl_fill_array(op->sym->m_src, src_buf_start,\n-\t\t\t\t&cookie->qat_sgl_src,\n-\t\t\t\tqat_req->comn_mid.src_length);\n+\t\t\t\t\t&cookie->qat_sgl_src,\n+\t\t\t\t\tqat_req->comn_mid.src_length,\n+\t\t\t\t\tQAT_SYM_SGL_MAX_NUMBER);\n \n \t\tif (unlikely(ret)) {\n \t\t\tQAT_DP_LOG(ERR, \"QAT PMD Cannot fill sgl array\");\n@@ -509,9 +510,10 @@ qat_sym_build_request(void *in_op, uint8_t *out_msg,\n \t\t\t\tcookie->qat_sgl_src_phys_addr;\n \t\telse {\n \t\t\tret = qat_sgl_fill_array(op->sym->m_dst,\n-\t\t\t\t\tdst_buf_start,\n-\t\t\t\t\t&cookie->qat_sgl_dst,\n-\t\t\t\t\t\tqat_req->comn_mid.dst_length);\n+\t\t\t\t\t\t dst_buf_start,\n+\t\t\t\t\t\t &cookie->qat_sgl_dst,\n+\t\t\t\t\t\t qat_req->comn_mid.dst_length,\n+\t\t\t\t\t\t QAT_SYM_SGL_MAX_NUMBER);\n \n \t\t\tif (unlikely(ret)) {\n \t\t\t\tQAT_DP_LOG(ERR, \"QAT PMD can't fill sgl array\");\ndiff --git a/drivers/crypto/qat/qat_sym.h b/drivers/crypto/qat/qat_sym.h\nindex e4e1ae8..bc6426c 100644\n--- a/drivers/crypto/qat/qat_sym.h\n+++ b/drivers/crypto/qat/qat_sym.h\n@@ -21,11 +21,21 @@\n */\n #define BPI_MAX_ENCR_IV_LEN ICP_QAT_HW_AES_BLK_SZ\n \n+/*\n+ * Maximum number of SGL entries\n+ */\n+#define QAT_SYM_SGL_MAX_NUMBER\t16\n+\n struct qat_sym_session;\n \n+struct qat_sym_sgl {\n+\tqat_sgl_hdr;\n+\tstruct qat_flat_buf buffers[QAT_SYM_SGL_MAX_NUMBER];\n+} __rte_packed __rte_cache_aligned;\n+\n struct qat_sym_op_cookie {\n-\tstruct qat_sgl qat_sgl_src;\n-\tstruct qat_sgl qat_sgl_dst;\n+\tstruct qat_sym_sgl qat_sgl_src;\n+\tstruct qat_sym_sgl qat_sgl_dst;\n \tphys_addr_t qat_sgl_src_phys_addr;\n \tphys_addr_t qat_sgl_dst_phys_addr;\n };\n", "prefixes": [ "1/2" ] }